coreboot June 2009

coreboot@coreboot.org

84 participants
500 discussions

Re: [coreboot] I've got this message...
by Rick Ant 26 Jun '09

26 Jun '09

where can i find the VGA BIOS ? ========== You can NOT use a qemu bios on hardware. I hope that is not what you are trying to do. It won't work. ========== Then which BIOS that should I use so I can embed linux in FLASH ROM chip? Thanks --- On Wed, 6/24/09, ron minnich <rminnich(a)gmail.com> wrote: From: ron minnich <rminnich(a)gmail.com> Subject: Re: [coreboot] I've got this message... To: "Rick Ant" <rick_077(a)yahoo.com> Cc: coreboot(a)coreboot.org Date: Wednesday, June 24, 2009, 10:32 PM there is a problem, you are missing a vga bios maybe. You can NOT use a qemu bios on hardware. I hope that is not what you are trying to do. It won't work. ron

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Re: [coreboot] Integrate the kernel into 49LF004...
by Rick Ant 26 Jun '09

26 Jun '09

Thanks for the info here's the info of my machine : Step 1... Board vendor : unknown Processor : Intel Pentium III Northbridge : Intel 82810 Southbridge : Intel 82801 AA BIOS Chip : SST 49LF004 Network Chip : RTL 8100C Memory Bank : 1 Bank DDR SDRAM, I put on 128 Mbyte Step 2 : lspci -tvnn result: -[00]-+-00.0 8086:7120 +-01.0 8086:7121 +-1e.0-[01]----0a.0 10ec:8139 +-1f.0 8086:2410 +-1f.1 8086:2411 +-1f.2 8086:2412 +-1f.3 8086:2413 \-1f.5 8086:2415 Step 3 : Super I/O chip on this board : Winbond W83627 HG - AW Step 4 : BIOS Device : SST 49LF004B 512 Kbytes EEPROM Where can I download BuildROM ? --- On Thu, 6/25/09, Cristi Magherusan <Cristi.Magherusan(a)net.utcluj.ro> wrote: From: Cristi Magherusan <Cristi.Magherusan(a)net.utcluj.ro> Subject: Re: [coreboot] Integrate the kernel into 49LF004... To: "Rick Ant" <rick_077(a)yahoo.com> Cc: coreboot(a)coreboot.org Date: Thursday, June 25, 2009, 6:25 AM On Wed, 2009-06-24 at 19:04 -0700, Rick Ant wrote: > Hello, > > Is it possible for me to integrate the Linux Kernel Into the Flash ROM > 49LF004 and starting the X-server ? > > Thanks > Hello, Yes it's possible: http://www.youtube.com/watch?v=nuzRsXKm_NQ Buildrom is able to include the kernel, but it is unable to include the X server inside the payload. LBDistro was able to do it, but it's unmaintained since a couple of years so it may not work at all. You can also take a look at my AVATT project, which is using buildroot to help compiling userland programs. I modified buildrom to use images generated by buildroot as payload. This should make very straightforward including X or anything provided by buildroot inside the payload, with the expense of some extra time(~30 minutes) spent on compiling the toolchain, but only for the first time. You can find my code at http://cristi.indefero.net/p/avatt/ Regards, Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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Re: [coreboot] [flashrom] getting SST SST49LF020A working
by Carl-Daniel Hailfinger 26 Jun '09

26 Jun '09

Hi Simon, thank you for your report. On 10.06.2009 15:01, Simon Wunderlich wrote: > we are using flashrom to flash our bios from the running linux system. > The SST SST49LF020A is currently in state "untested" in on your Wiki. In the > source code, a page size of 16 * 1024 > is configured, which is not correct for this chip (WRITE and ERASE fails). I > could see in the hexdump that the regions > 0x1000 - 0x1FFF, 0x3000 - 0x3FFFF, 0x5000 - 0x5FFFF ... have not been > erased. > After changing the page size to 4 * 1024 in flashchips.c, writing and > erasing works fine. Reading also worked with the > wrong page size. I guess PROBE works fine too since the chip is detected. > > Hope that helps you to complete your list of supported chips. :) > Can you please try the attached patch? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> If it works, can you respond with a line saying Acked-by: Simon Wunderlich <simon.wunderlich(a)saxnet.de> Thanks! Regards, Carl-Daniel -- http://www.hailfinger.org/ Index: flashrom-sst49lf020a/flashchips.c =================================================================== --- flashrom-sst49lf020a/flashchips.c (Revision 632) +++ flashrom-sst49lf020a/flashchips.c (Arbeitskopie) @@ -2160,8 +2160,8 @@ .manufacture_id = SST_ID, .model_id = SST_49LF020A, .total_size = 256, - .page_size = 16 * 1024, - .tested = TEST_UNTESTED, + .page_size = 4 * 1024, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .erase = erase_49lf040,

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build service results for r4374
by coreboot information 26 Jun '09

26 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4374 to the coreboot repository. This caused the following changes: Change Log: Don't dump 0x07 registers, they're useless as they change every time some software wants to do an LDN access (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4374&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4374&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4373
by coreboot information 26 Jun '09

26 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4373 to the coreboot repository. This caused the following changes: Change Log: This adds register definitions for all logical devices on the SMSC LPC47U33x, allowing 'superiotool -d' to work. Also, some consistency string fixes. Signed-off-by: Michael Gold <mgold(a)ncf.ca> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4373&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4373&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4374 - trunk/util/superiotool
by svn＠coreboot.org 26 Jun '09

26 Jun '09

Author: uwe Date: 2009-06-26 17:53:07 +0200 (Fri, 26 Jun 2009) New Revision: 4374 Modified: trunk/util/superiotool/smsc.c Log: Don't dump 0x07 registers, they're useless as they change every time some software wants to do an LDN access (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2009-06-26 15:25:04 UTC (rev 4373) +++ trunk/util/superiotool/smsc.c 2009-06-26 15:53:07 UTC (rev 4374) @@ -470,9 +470,9 @@ {EOT}}}, {0x74, "LPC47M182", { /* Only for LD_NUM = 0 */ {NOLDN, NULL, - {0x02,0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27, + {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27, 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x00,RSVD,0x00,0x74,RSVD,0x00,RSVD,0x44,MISC,0x00, + {0x00,RSVD,0x74,RSVD,0x00,RSVD,0x44,MISC,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,

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A bunch of superiotool dumps
by sim0n 26 Jun '09

26 Jun '09

Hi, I've prepared some superiotool dumps of different machines (servers, workstations). The command was run like this: superiotool -d --extra-dump You'll find the dumps at: http://simon.trypill.org/downloads/coreboot/superio_dumps They currently include boards from: Asus Gigabyte Intel Dell Supermicro Tyan The name of each dump indicates the board name (for Dell, server-name) I hope somebody finds this helpful :-) -- regards, sim0n

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build service results for r4372
by coreboot information 26 Jun '09

26 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4372 to the coreboot repository. This caused the following changes: Change Log: Add dump information for F71862FG and F71863FG. Signed-off-by: Arjan Koers <0h3q2rmn2bdb(a)list.nospam.xutrox.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4372&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4372&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] superiotool: SMSC LPC47U33x dump support
by Michael Gold 26 Jun '09

26 Jun '09

This adds register definitions for all logical devices on the SMSC LPC47U33x, allowing 'superiotool -d' to work. Signed-off-by: Michael Gold <mgold(a)ncf.ca>

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[v2] r4373 - trunk/util/superiotool
by svn＠coreboot.org 26 Jun '09

26 Jun '09

Author: uwe Date: 2009-06-26 17:25:04 +0200 (Fri, 26 Jun 2009) New Revision: 4373 Modified: trunk/util/superiotool/nsc.c trunk/util/superiotool/smsc.c trunk/util/superiotool/winbond.c Log: This adds register definitions for all logical devices on the SMSC LPC47U33x, allowing 'superiotool -d' to work. Also, some consistency string fixes. Signed-off-by: Michael Gold <mgold(a)ncf.ca> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2009-06-26 15:16:21 UTC (rev 4372) +++ trunk/util/superiotool/nsc.c 2009-06-26 15:25:04 UTC (rev 4373) @@ -498,7 +498,7 @@ 0xf1,0xf2,0xf3,0xf6,0xf7,EOT}, {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00, 0x00,0x00,0x00,MISC,0x00,EOT}}, - {0x14, "Health Monitoring and Control (HMC)", + {0x14, "Health monitoring and control (HMC)", {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75, 0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2009-06-26 15:16:21 UTC (rev 4372) +++ trunk/util/superiotool/smsc.c 2009-06-26 15:25:04 UTC (rev 4373) @@ -43,7 +43,7 @@ 0xf5,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00, 0x00,EOT}}, - {0x1, "Power Management (PM1)", + {0x1, "Power management (PM1)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, {0x3, "Parallel port", @@ -63,7 +63,7 @@ {0x7, "Keyboard", {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, - {0x8, "Embedded Controller (EC)", + {0x8, "Embedded controller (EC)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x62,EOT}}, {0x9, "Mailbox", @@ -81,7 +81,7 @@ 0xf5,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00, 0x00,EOT}}, - {0x1, "Power Management (PM1)", + {0x1, "Power management (PM1)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, {0x3, "Parallel port", @@ -101,7 +101,7 @@ {0x7, "Keyboard", {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, - {0x8, "Embedded Controller (EC)", + {0x8, "Embedded controller (EC)", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x62,EOT}}, {0x9, "Mailbox", @@ -347,6 +347,37 @@ {0x52, "LPC47B37x", { {EOT}}}, {0x54, "LPC47U33x", { + {NOLDN, NULL, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2a,0x2b, + 0x2c,0x2d,0x2e,0x2f,EOT}, + {RSVD,0x54,NANA,0x00,0x00,0x04,MISC,MISC,NANA,NANA, + NANA,NANA,NANA,NANA,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, + EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,0x00, + EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "MIDI port (MPU-401)", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x03,0x30,0x05,EOT}}, + {0x7, "Keyboard", + {0x30,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x9, "Game port", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "Runtime registers", + {0x30,0x60,0x61,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,NANA,NANA,EOT}}, + {0xb, "SMBus", + {0x30,0x60,0x61,0x70,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, {EOT}}}, {0x56, "LPC47B34x", { {EOT}}}, @@ -380,7 +411,7 @@ {0x9, "Game port", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, - {0xa, "Power Management Events (PME)", + {0xa, "Power management events (PME)", {0x30,0x60,0x61,0xf0,0xf1,EOT}, {0x00,0x00,0x00,NANA,RSVD,EOT}}, {0xb, "MPU-401", @@ -417,7 +448,7 @@ {0x9, "Game port", {0x30,0x60,0x61,EOT}, {0x00,0x00,0x00,EOT}}, - {0xa, "Power Management Events (PME)", + {0xa, "Power management events (PME)", {0x30,0x60,0x61,0xf0,EOT}, {0x00,0x00,0x00,NANA,EOT}}, {0xb, "MPU-401", @@ -457,7 +488,7 @@ {0x3, "COM1", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,EOT}}, - {0x4, "Power Control", + {0x4, "Power control", {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, {0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, {0x5, "Mouse", Modified: trunk/util/superiotool/winbond.c =================================================================== --- trunk/util/superiotool/winbond.c 2009-06-26 15:16:21 UTC (rev 4372) +++ trunk/util/superiotool/winbond.c 2009-06-26 15:25:04 UTC (rev 4373) @@ -324,7 +324,7 @@ {0x7, "Game port, MIDI port, GPIO 1", {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,EOT}}, - {0x8, "GPIO 2, Watchdog timer", + {0x8, "GPIO 2, watchdog timer", {0x30,0xf0,0xf1,0xf2,0xf3,0xf5,0xf6,0xf6,0xf7,EOT}, {0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x9, "GPIO 3",

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coreboot June 2009