coreboot June 2009

coreboot@coreboot.org

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500 discussions

[v2] r4329 - trunk/coreboot-v2/util/cbfstool

by svn＠coreboot.org

Author: oxygene Date: 2009-06-01 22:02:21 +0200 (Mon, 01 Jun 2009) New Revision: 4329 Modified: trunk/coreboot-v2/util/cbfstool/util.c Log: cbfstool reacts to a too large bootblock file by stopping with an error code now. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/util/cbfstool/util.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/util.c 2009-06-01 01:38:29 UTC (rev 4328) +++ trunk/coreboot-v2/util/cbfstool/util.c 2009-06-01 20:02:21 UTC (rev 4329) @@ -222,7 +222,8 @@ rom->header->align = htonl(align); rom->header->offset = htonl(0); - add_bootblock(rom, bootblockname); + if (add_bootblock(rom, bootblockname) == -1) + return -1; /* Write the cbfs master header address at the end of the ROM. */

11 years, 11 months

[PATCH] use coreboot.rom for CBFS images, but default to smaller size

by Patrick Georgi

Hi, attached patch changes the bootblock generation for CBFS images. It uses coreboot.rom (padded and all), but defaults to smaller fallback/normal image sizes. It requires changes to each CBFS aware mainboard config (and requires adaption on conversion), but it fixes using normal image (as the offsets are calculated correctly). I tried to get rid of ROM_IMAGE_SIZE and friends, but that'll have to wait until non-CBFS images are gone - maintaining two separate build configurations in a single build system isn't fun. If this gets accepted, I'll propose a patch for the (few) CBFS boards, and commit them together. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

11 years, 11 months

Mptable fix for M57SLI

by Harald Gutmann

Hello, I've given it another try to fix the mptable of the M57SLI. The attached patch fixes for me the following things: * Nvidia graphic device works on PCIe-16x slot (black). * Both PCI cards in the two available slots work fine. * Also the PCIe 1x slots should work fine. (untested) It would be fine if someone of you could test and verify if that patch works on hardware revision v1 too. I hope that this fixes all the problems along with interrupts for this mainboard and I'm looking forward that someone can verify/test this. Kind regards, Harald PS: Is it necessary to add PCI_INT for 00:08/07.01-03?

11 years, 11 months

MSI 7135 verbose lspci output

by David Hendricks

Attached is an lspci dump for the MSI 7135 (K8N Neo3) board. jakllsch did a v2 port for this board last year. Flashrom works, but only if you do -m msi:k8n-neo3 for erase and write operations. Uwe suggested posting the lspci contents in case someone has a few spare cycles to try and implement auto-detect for this board in flashrom.

11 years, 11 months

[PATCH] flashrom: Only probe for chips with compatible bus protocols

by Carl-Daniel Hailfinger

Only probe for chips with compatible bus protocols. It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,9 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n"); + /* Not sure if it only speaks Parallel. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,6 +63,7 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Arbeitskopie) @@ -29,6 +29,8 @@ int dummy_init(void) { printf_debug("%s\n", __func__); + /* This depends on UNKNOWN having all bits set. */ + buses_supported = CHIP_BUSTYPE_UNKNOWN; spi_controller = SPI_CONTROLLER_DUMMY; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -188,6 +188,10 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + printf_debug("skipped. Host and chip bus type are incompatible.\n"); + continue; + } size = flash->total_size * 1024; -- http://www.hailfinger.org/ Index: flashrom-chiptype_avoid_bus_mismatch/it87spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/it87spi.c (Arbeitskopie) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Index: flashrom-chiptype_avoid_bus_mismatch/nic3com.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/nic3com.c (Arbeitskopie) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/satasii.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/satasii.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/satasii.c (Arbeitskopie) @@ -67,6 +67,9 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar)) & (1 << 26))) printf("Warning: Flash seems unconnected.\n"); + /* Not sure if it only speaks Parallel. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/wbsio_spi.c (Arbeitskopie) @@ -63,6 +63,7 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/dummyflasher.c (Arbeitskopie) @@ -29,6 +29,8 @@ int dummy_init(void) { printf_debug("%s\n", __func__); + /* This depends on UNKNOWN having all bits set. */ + buses_supported = CHIP_BUSTYPE_UNKNOWN; spi_controller = SPI_CONTROLLER_DUMMY; return 0; } Index: flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/chipset_enable.c (Arbeitskopie) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Index: flashrom-chiptype_avoid_bus_mismatch/flashrom.c =================================================================== --- flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Revision 557) +++ flashrom-chiptype_avoid_bus_mismatch/flashrom.c (Arbeitskopie) @@ -188,6 +188,10 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + printf_debug("skipped. Host and chip bus type are incompatible.\n"); + continue; + } size = flash->total_size * 1024;

11 years, 11 months

[flashrom] r560 - trunk

by svn＠coreboot.org

Author: hailfinger Date: 2009-06-01 04:08:58 +0200 (Mon, 01 Jun 2009) New Revision: 560 Modified: trunk/chipset_enable.c trunk/flashrom.c trunk/it87spi.c trunk/nic3com.c trunk/satasii.c trunk/wbsio_spi.c Log: Only probe for chips with compatible bus protocols. It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested on real hardware and Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/chipset_enable.c 2009-06-01 02:08:58 UTC (rev 560) @@ -36,13 +36,12 @@ unsigned long flashbase = 0; /** - * flashrom defaults to LPC flash devices. If a known SPI controller is found - * and the SPI strappings are set, this will be overwritten by the probing code. - * - * Eventually, this will become an array when multiple flash support works. + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. */ -enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN; +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; extern int ichspi_lock; @@ -217,6 +216,8 @@ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(spibar + 0x6c)); + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_VIA; ich_init_opcodes(); @@ -262,22 +263,29 @@ */ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; /* No further SPI initialization required */ return ret; } switch (ich_generation) { case 7: + buses_supported = CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH7; spibar_offset = 0x3020; break; case 8: + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ + /* Not sure if it speaks LPC as well. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_ICH9; spibar_offset = 0x3800; break; @@ -727,8 +735,11 @@ has_spi = 0; } - if (has_spi) + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; + if (has_spi) { + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_SB600; + } /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/flashrom.c 2009-06-01 02:08:58 UTC (rev 560) @@ -174,10 +174,51 @@ return 0; } +char *strcat_realloc(char *dest, const char *src) +{ + dest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!dest) + return NULL; + strcat(dest, src); + return dest; +} + +/* Return a string corresponding to the bustype parameter. + * Memory is obtained with malloc() and can be freed with free(). + */ +char *flashbuses_to_text(enum chipbustype bustype) +{ + char *ret = calloc(1, 1); + if (bustype == CHIP_BUSTYPE_UNKNOWN) { + ret = strcat_realloc(ret, "Unknown,"); + /* FIXME: Once all chipsets and flash chips have been updated, NONSPI + * will cease to exist and should be eliminated here as well. + */ + } else if (bustype == CHIP_BUSTYPE_NONSPI) { + ret = strcat_realloc(ret, "Non-SPI,"); + } else { + if (bustype & CHIP_BUSTYPE_PARALLEL) + ret = strcat_realloc(ret, "Parallel,"); + if (bustype & CHIP_BUSTYPE_LPC) + ret = strcat_realloc(ret, "LPC,"); + if (bustype & CHIP_BUSTYPE_FWH) + ret = strcat_realloc(ret, "FWH,"); + if (bustype & CHIP_BUSTYPE_SPI) + ret = strcat_realloc(ret, "SPI,"); + if (bustype == CHIP_BUSTYPE_NONE) + ret = strcat_realloc(ret, "None,"); + } + /* Kill last comma. */ + ret[strlen(ret) - 1] = '\0'; + ret = realloc(ret, strlen(ret) + 1); + return ret; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; unsigned long base = 0, size; + char *tmp; for (flash = first_flash; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) @@ -188,6 +229,15 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } + if (!(buses_supported & flash->bustype)) { + tmp = flashbuses_to_text(buses_supported); + printf_debug("skipped. Host bus type %s ", tmp); + free(tmp); + tmp = flashbuses_to_text(flash->bustype); + printf_debug("and chip bus type %s are incompatible.\n", tmp); + free(tmp); + continue; + } size = flash->total_size * 1024; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/it87spi.c 2009-06-01 02:08:58 UTC (rev 560) @@ -109,14 +109,23 @@ int it87spi_init(void) { + int ret; + get_io_perms(); - - return it87spi_common_init(); + ret = it87spi_common_init(); + if (!ret) + buses_supported = CHIP_BUSTYPE_SPI; + return ret; } int it87xx_probe_spi_flash(const char *name) { - return it87spi_common_init(); + int ret; + + ret = it87spi_common_init(); + if (!ret) + buses_supported |= CHIP_BUSTYPE_SPI; + return ret; } /* Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/nic3com.c 2009-06-01 02:08:58 UTC (rev 560) @@ -81,6 +81,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/satasii.c 2009-06-01 02:08:58 UTC (rev 560) @@ -67,6 +67,8 @@ if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) printf("Warning: Flash seems unconnected.\n"); + buses_supported = CHIP_BUSTYPE_PARALLEL; + return 0; } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-06-01 00:02:11 UTC (rev 559) +++ trunk/wbsio_spi.c 2009-06-01 02:08:58 UTC (rev 560) @@ -63,7 +63,10 @@ return 1; printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + buses_supported |= CHIP_BUSTYPE_SPI; spi_controller = SPI_CONTROLLER_WBSIO; + return 0; }

11 years, 11 months

[v2] r4328 - trunk/coreboot-v2/src/superio/serverengines/pilot

by svn＠coreboot.org

Author: uwe Date: 2009-06-01 03:38:29 +0200 (Mon, 01 Jun 2009) New Revision: 4328 Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c Log: Cosmetics and consistency fixes in src/superio/serverengines/pilot/ (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot.h 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,15 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ -#define PILOT_SP1 0x02 -// Serial port COM1 -#define PILOT_LD1 0x01 -// logical device 1 -#define PILOT_LD4 0x04 -// logical device 4 -#define PILOT_LD5 0x05 -// logical device 5 -#define PILOT_LD7 0x07 -// logical device 7 +#define PILOT_SP1 0x02 /* Com1 */ +#define PILOT_LD1 0x01 /* Logical device 1 */ +#define PILOT_LD4 0x04 /* Logical device 4 */ +#define PILOT_LD5 0x05 /* Logical device 5 */ +#define PILOT_LD7 0x07 /* Logical device 7 */ Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_init.c 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,78 +19,79 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ #define BLUBB_DEV PNP_DEV(port, 0x04) -/* Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to - be another serial (?), it is also deactivated on the HP machine */ +/* + * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to + * be another serial (?), it is also deactivated on the HP machine. + */ static void pilot_early_init(device_t dev) { - unsigned port = dev>>8; - print_debug("Using port:");print_debug_hex16(port);print_debug("\r\n"); - pilot_disable_serial(PNP_DEV(port,0x1)); + unsigned port = dev >> 8; + + print_debug("Using port: "); + print_debug_hex16(port); + print_debug("\r\n"); + pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\r\n"); /* -pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x3)); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x3),0); + pnp_set_enable(PNP_DEV(port, 0x3), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x4)); + pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x4),0); + pnp_set_enable( PNP_DEV(port, 0x4), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x5)); + pnp_set_logical_device(PNP_DEV(port, 0x5)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x5),0); + pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); - /* +/* pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x6)); + pnp_set_logical_device(PNP_DEV(port, 0x6)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port,0x6),0); + pnp_set_enable( PNP_DEV(port, 0x6), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x7)); + pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x7), 0); + pnp_set_enable(PNP_DEV(port, 0x7), 0); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x8)); + pnp_set_logical_device(PNP_DEV(port, 0x8)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x8), 0); + pnp_set_enable(PNP_DEV(port, 0x8), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x9)); + pnp_set_logical_device(PNP_DEV(port, 0x9)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x9), 0); + pnp_set_enable(PNP_DEV(port, 0x9), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port,0x10; + pnp_set_logical_device(PNP_DEV(port, 0x10)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port,0x10 0); + pnp_set_enable(PNP_DEV(port, 0x10), 0); pnp_exit_ext_func_mode(dev); */ - } - - - Modified: trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c 2009-05-31 17:00:25 UTC (rev 4327) +++ trunk/coreboot-v2/src/superio/serverengines/pilot/pilot_early_serial.c 2009-06-01 01:38:29 UTC (rev 4328) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for Univ. Heidelberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,25 +19,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* PILOT SuperIO is only based on LPC observation done on factory system. */ +/* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/romcc_io.h> #include "pilot.h" -/* pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access */ +/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ static inline void pnp_enter_ext_func_mode(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0x5A, port); } static void pnp_exit_ext_func_mode(device_t dev) { - unsigned port = dev>>8; + unsigned port = dev >> 8; outb(0xA5, port); } -/* serial config is failry standard procedure */ +/* Serial config is a fairly standard procedure. */ static void pilot_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); @@ -55,4 +55,3 @@ pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); } -

11 years, 11 months

[flashrom] nic3com: address lines

by Mats Erik Andersson

Hello all, using a signal probe I can verify two facts: 1) 3c905B has address lines A0 -- A16 routed, but not A17. Thus 128 kB is the maximal capacity achievable. 2) 3c905 only routes the adress lines A0 -- A15, and therefore limits itself to only 64 kB. On the other hand, I have not succeeded in getting even read capabilities going in my own code (not your "flashrom"). As a side note, rtl8138C and via-rhine VT6102 are already a priory bounded by 64 kB. Both are easily usable by straight forward coding. In contrast, eepro100 seems to be usable by ctflasher only due to their repeated probing. One time probing, as in my efforts, have yet to prove successful. Best regards Mats Erik Andersson

11 years, 11 months

[PATCH] flashrom: Add bus type support to -p dummy

by Carl-Daniel Hailfinger

Add bus type support to the dummy external programmer. The syntax is explained in the man page. Example: flashrom -p dummy=lpc,fwh Tested, works perfectly. ;-) As a nice benefit, it allows easy testing of the "probe only compatible flashes" patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dummy_bustype/flashrom.8 =================================================================== --- flashrom-dummy_bustype/flashrom.8 (Revision 557) +++ flashrom-dummy_bustype/flashrom.8 (Arbeitskopie) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Index: flashrom-dummy_bustype/flash.h =================================================================== --- flashrom-dummy_bustype/flash.h (Revision 557) +++ flashrom-dummy_bustype/flash.h (Arbeitskopie) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Index: flashrom-dummy_bustype/dummyflasher.c =================================================================== --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) @@ -20,16 +20,51 @@ #include <string.h> #include <stdlib.h> +#include <ctype.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <errno.h> #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for parallel flash.\n"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for LPC flash.\n"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for FWH flash.\n"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for SPI flash.\n"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Index: flashrom-dummy_bustype/flashrom.c =================================================================== --- flashrom-dummy_bustype/flashrom.c (Revision 557) +++ flashrom-dummy_bustype/flashrom.c (Arbeitskopie) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=') -- http://www.hailfinger.org/ Index: flashrom-dummy_bustype/flashrom.8 =================================================================== --- flashrom-dummy_bustype/flashrom.8 (Revision 557) +++ flashrom-dummy_bustype/flashrom.8 (Arbeitskopie) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Index: flashrom-dummy_bustype/flash.h =================================================================== --- flashrom-dummy_bustype/flash.h (Revision 557) +++ flashrom-dummy_bustype/flash.h (Arbeitskopie) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Index: flashrom-dummy_bustype/dummyflasher.c =================================================================== --- flashrom-dummy_bustype/dummyflasher.c (Revision 557) +++ flashrom-dummy_bustype/dummyflasher.c (Arbeitskopie) @@ -20,16 +20,51 @@ #include <string.h> #include <stdlib.h> +#include <ctype.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <errno.h> #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for parallel flash.\n"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for LPC flash.\n"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for FWH flash.\n"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for SPI flash.\n"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Index: flashrom-dummy_bustype/flashrom.c =================================================================== --- flashrom-dummy_bustype/flashrom.c (Revision 557) +++ flashrom-dummy_bustype/flashrom.c (Arbeitskopie) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=')

11 years, 11 months

[flashrom] r559 - trunk

by svn＠coreboot.org

Author: hailfinger Date: 2009-06-01 02:02:11 +0200 (Mon, 01 Jun 2009) New Revision: 559 Modified: trunk/dummyflasher.c trunk/flash.h trunk/flashrom.8 trunk/flashrom.c Log: Add bus type support to the dummy external programmer. The syntax is explained in the man page. Example: flashrom -p dummy=lpc,fwh Tested, works perfectly. ;-) As a nice benefit, it allows easy testing of the "probe only compatible flashes" patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/dummyflasher.c 2009-06-01 00:02:11 UTC (rev 559) @@ -20,16 +20,52 @@ #include <string.h> #include <stdlib.h> +#include <ctype.h> #include <fcntl.h> #include <sys/types.h> #include <sys/stat.h> #include <errno.h> #include "flash.h" +char *dummytype = NULL; + int dummy_init(void) { + int i; printf_debug("%s\n", __func__); - spi_controller = SPI_CONTROLLER_DUMMY; + + /* "all" is equivalent to specifying no type. */ + if (!strcmp(dummytype, "all")) { + free(dummytype); + dummytype = NULL; + } + if (!dummytype) + dummytype = strdup("parallel,lpc,fwh,spi"); + /* Convert the parameters to lowercase. */ + for (i = 0; dummytype[i] != '\0'; i++) + dummytype[i] = (char)tolower(dummytype[i]); + + buses_supported = CHIP_BUSTYPE_NONE; + if (strstr(dummytype, "parallel")) { + buses_supported |= CHIP_BUSTYPE_PARALLEL; + printf_debug("Enabling support for %s flash.\n", "parallel"); + } + if (strstr(dummytype, "lpc")) { + buses_supported |= CHIP_BUSTYPE_LPC; + printf_debug("Enabling support for %s flash.\n", "LPC"); + } + if (strstr(dummytype, "fwh")) { + buses_supported |= CHIP_BUSTYPE_FWH; + printf_debug("Enabling support for %s flash.\n", "FWH"); + } + if (strstr(dummytype, "spi")) { + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_DUMMY; + printf_debug("Enabling support for %s flash.\n", "SPI"); + } + if (buses_supported == CHIP_BUSTYPE_NONE) + printf_debug("Support for all flash bus types disabled.\n"); + free(dummytype); return 0; } Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flash.h 2009-06-01 00:02:11 UTC (rev 559) @@ -122,6 +122,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) enum chipbustype { + CHIP_BUSTYPE_NONE = 0, CHIP_BUSTYPE_PARALLEL = 1 << 0, CHIP_BUSTYPE_LPC = 1 << 1, CHIP_BUSTYPE_FWH = 1 << 2, @@ -646,6 +647,7 @@ #endif /* dummyflasher.c */ +extern char *dummytype; int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flashrom.8 2009-06-01 00:02:11 UTC (rev 559) @@ -135,6 +135,18 @@ .sp .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)" .sp +The dummy programmer has an optional parameter specifying the bus types it +should support. For that you have to use the +.B "flashrom -p dummy=type" +syntax where +.B type +can be any comma-separated combination of +.B parallel lpc fwh spi all +in any order. +.sp +Example: +.B "flashrom -p dummy=lpc,fwh" +.sp If you have multiple supported PCI cards which can program flash chips (NICs, SATA/IDE controllers, etc.) in your system, you must use the .B "flashrom -p xxxx=bb:dd.f" Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-31 21:35:10 UTC (rev 558) +++ trunk/flashrom.c 2009-06-01 00:02:11 UTC (rev 559) @@ -537,6 +537,8 @@ programmer = PROGRAMMER_INTERNAL; } else if (strncmp(optarg, "dummy", 5) == 0) { programmer = PROGRAMMER_DUMMY; + if (optarg[5] == '=') + dummytype = strdup(optarg + 6); } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=')

11 years, 11 months

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coreboot June 2009