coreboot June 2009

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Flashrom patch
by Maciej Pijanka 02 Jun '09

02 Jun '09

Hello I tried vortex-diag on some 3com card and reading/writing flash was working, so i tried to add it to nic3com.c (patch attached) Also, i added AT29C512 Atmel flash chip to flashchips.c to get it autodetected (patch also attached). Final flashrom -p nic3com -V log is in patched-detection.log best regards Maciej Pijanka -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user

2 1

[flashrom] r566 - trunk
by svn＠coreboot.org 02 Jun '09

02 Jun '09

Author: uwe Date: 2009-06-02 18:45:59 +0200 (Tue, 02 Jun 2009) New Revision: 566 Modified: trunk/flash.h trunk/flashchips.c trunk/nic3com.c Log: Add support for the 10b7:9058 3COM NIC (3C905B: Cyclone 10/100/BNC). Also, add Atmel AT29C512 support. Both are tested on hardware by Maciej Pijanka. Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/flash.h 2009-06-02 16:45:59 UTC (rev 566) @@ -287,6 +287,7 @@ #define AT_29C040A 0xA4 #define AT_29C010A 0xD5 #define AT_29C020 0xDA +#define AT_29C512 0x5D #define AT_45BR3214B /* No ID available */ #define AT_45CS1282 0x2920 #define AT_45D011 /* No ID available */ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/flashchips.c 2009-06-02 16:45:59 UTC (rev 566) @@ -400,6 +400,22 @@ { .vendor = "Atmel", + .name = "AT29C512", + .bustype = CHIP_BUSTYPE_NONSPI, + .manufacture_id = ATMEL_ID, + .model_id = AT_29C512, + .total_size = 64, + .page_size = 128, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .erase = erase_chip_jedec, + .write = write_jedec, + .read = read_memmapped, + + }, + + { + .vendor = "Atmel", .name = "AT29C010A", .bustype = CHIP_BUSTYPE_NONSPI, .manufacture_id = ATMEL_ID, Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-06-02 13:39:42 UTC (rev 565) +++ trunk/nic3com.c 2009-06-02 16:45:59 UTC (rev 566) @@ -46,6 +46,7 @@ {0x10b7, 0x9006, PCI_NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" }, {0x10b7, 0x900a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FL" }, {0x10b7, 0x905a, PCI_NT, "3COM", "3C90xB: PCI 10BASE-FX" }, + {0x10b7, 0x9058, PCI_NT, "3COM", "3C905B: Cyclone 10/100/BNC" }, /* 3C905C */ {0x10b7, 0x9200, PCI_OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" }, @@ -65,7 +66,7 @@ /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 - || id == 0x9006 || id == 0x900a || id == 0x905a) { + || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { /* Select register window 3 and save the receiver status. */ OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); internal_conf = INL(io_base_addr + INTERNAL_CONFIG); @@ -90,7 +91,7 @@ { /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 - || id == 0x9006 || id == 0x900a || id == 0x905a) { + || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { /* Select register window 3 and restore the receiver status. */ OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);

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#127: Add support for hp dl145g3 to coreboot v2
by coreboot 02 Jun '09

02 Jun '09

#127: Add support for hp dl145g3 to coreboot v2 -------------------------------------------+-------------------------------- Reporter: samuel.verstraete@… | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- http://www.coreboot.org/pipermail/coreboot/2009-March/046076.html -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/127> coreboot <http://www.coreboot.org/>

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Re: [coreboot] [v2] r4323 - trunk/coreboot-v2/src/arch/i386/lib
by Luc Verhaegen 02 Jun '09

02 Jun '09

On Fri, May 29, 2009 at 03:08:27PM +0200, svn(a)coreboot.org wrote: > Author: stepan > Date: 2009-05-29 15:08:27 +0200 (Fri, 29 May 2009) > New Revision: 4323 > > Modified: > trunk/coreboot-v2/src/arch/i386/lib/c_start.S > Log: > drop most of the crappy vm86 code and replace it with a rewritten > version that has all assembler in a .S file and all C code in a .c > file. Also, remove requirement to move around between GDTs. > > This version includes the suggestions from Peter to clean up CR0 manipulation > and to guard critical code paths by cli/sti. Tested and working on my hardware. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Peter Stuge <peter(a)stuge.se> > > > > Modified: trunk/coreboot-v2/src/arch/i386/lib/c_start.S > =================================================================== > --- trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2009-05-29 03:44:47 UTC (rev 4322) > +++ trunk/coreboot-v2/src/arch/i386/lib/c_start.S 2009-05-29 13:08:27 UTC (rev 4323) > @@ -253,7 +253,7 @@ > > /* This is the gdt for GCC part of coreboot. > * It is different from the gdt in ROMCC/ASM part of coreboot > - * which is defined in entry32.inc */ > + * which is defined in entry32.inc */ /* BUT WHY?? */ > gdt: > /* selgdt 0, unused */ > .word 0x0000, 0x0000 /* dummy */ > @@ -275,6 +275,13 @@ > .word 0x0000, 0x0000 /* dummy */ > .byte 0x00, 0x00, 0x00, 0x00 > > + /* selgdt 0x28 16-bit 64k code at 0x00000000 */ > + .word 0xffff, 0x0000 > + .byte 0, 0x9a, 0, 0 > + > + /* selgdt 0x30 16-bit 64k data at 0x00000000 */ > + .word 0xffff, 0x0000 > + .byte 0, 0x92, 0, 0 > gdt_end: > > idtarg: Is this correct? Aren't some files supposed to be added and some supposed to be removed with this commit? At least i seem to remember something like that from the patch that was sent in a week or so ago, and the log message also points in this direction. Luc Verhaegen.

2 2

use libpayload in optionrom
by Jason Wang 02 Jun '09

02 Jun '09

Hi all, I am trying to use libpayload in our optionrom, but does not work now... The main difference between optionrom use its own ldscript and head asm code. I main things I did now is set up the stack and heap in the pci_rom.ld. and include the "libpayload.h" and "libpayload-config.h" in the main.c. it doesn't work when i am trying to print out message which use " printf("hello optionrom")". Is there any other things i should do? All my source code was in http://vps.dorilex.net/cgi-bin/gitweb.cgi?p=optionrom.git;a=summary Need some help about this, thanks everyone... -- Jason Wang Peking University

1 0

flashrom touches only 0x70000-0x80000 addresses of my bios flash
by Alexander Gordeev 02 Jun '09

02 Jun '09

Hi All! I've tried flashrom on my Gigabyte GA-K8N-SLI board but it can only write to 0x70000-0x80000. This includes both write and erase. Could you please help me to solve this? BTW, I don't yet have a backup chip so tested changes are preferred :) Here is the probe output: alex@tornado:~/bios$ sudo flashrom flashrom v0.9.0+r544 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. No operations were specified. Here is the output of lshw: *-firmware:0 description: BIOS vendor: Award Software International, Inc. physical id: 0 version: F4 (05/11/2006) size: 128KiB capacity: 448KiB capabilities: isa pci pnp apm upgrade shadowing cdboot bootselect socketedrom edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification *-firmware:1 description: BIOS physical id: 20 size: 1023KiB capabilities: apm bootselect socketedrom int13floppytoshiba int5printscreen I hope this helps. -- Alexander

4 15

[flashrom] r565 - trunk
by svn＠coreboot.org 02 Jun '09

02 Jun '09

Author: uwe Date: 2009-06-02 15:39:42 +0200 (Tue, 02 Jun 2009) New Revision: 565 Modified: trunk/board_enable.c Log: Add two more boards supported by flashrom: - ASUS A8N-SLI (reported by Ryan McLean <pvtryan100(a)googlemail.com>) - MSI/Medion MS-7255 (P4M890M) (reported by J?\195?\182rg Schirottke <master(a)kanotix.com>) Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-02 00:38:14 UTC (rev 564) +++ trunk/board_enable.c 2009-06-02 13:39:42 UTC (rev 565) @@ -704,6 +704,7 @@ { "ASI", "MB-5BLMP", }, { "ASUS", "A8N-E", }, { "ASUS", "A8NE-FM/S", }, + { "ASUS", "A8N-SLI", }, { "ASUS", "A8N-SLI Premium", }, { "ASUS", "A8V-E Deluxe", }, { "ASUS", "M2A-VM", }, @@ -733,6 +734,7 @@ { "MSI", "MS-7236 (945PL Neo3)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, { "MSI", "MS-7168 (Orion)", }, + { "MSI", "MS-7255 (P4M890M)", }, { "NEC", "PowerMate 2000", }, { "PC Engines", "Alix.1c", }, { "PC Engines", "Alix.2c2", },

1 0

Adding 740G support to RS690 code
by Carl-Daniel Hailfinger 02 Jun '09

02 Jun '09

Hi Zheng, since the AMD web site says the 740G is just a shrunk 690G with new graphics, would it be possible to add 740G support to the RS690 code easily? Can we use the RS690 code without changes? Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[FLASHROM] Add support for 3COM NICs and Atmel AT49BV512
by Uwe Hermann 02 Jun '09

02 Jun '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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flashrom: small patch
by Murawski Mateusz 02 Jun '09

02 Jun '09

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coreboot June 2009