coreboot June 2009

coreboot@coreboot.org

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500 discussions

Coreboot and ICH8M chipsets
by Lionel Broche 27 Jun '09

27 Jun '09

Hi, I have a laptop with the ICH8M chipset for intel core 2 duo microprocessors. It seems like it is not yet supported by coreboot: is there anything I can do to speed the support process? Here are some info about my system: Motherboard: Manufacturer: Intel Corporation Product Name: SANTA ROSA CRB chipsets: Manufacturer: Intel Corporation Product Name: Crestline & ICH8M Chipset processor: Intel Core 2 Duo The lspci -tvnn command gives me the following: -[0000:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-01.0-[0000:01]----00.0 nVidia Corporation GeForce 8600M GS [10de:0425] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[0000:02-03]----00.0 Atheros Communications Inc. AR242x 802.11abg Wireless PCI Express Adapter [168c:001c] +-1c.2-[0000:04-05]----00.0 Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] +-1c.3-[0000:06-07]-- +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[0000:08]-- +-1f.0 Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] +-1f.2 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA IDE Controller [8086:2828] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] I don't know what I/O chip is on the mainboard, and superiotool -dV fails to find anything, and the result of flashrom -V is attached in a file. And thanks for your hard work! Lionel

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Missing entry16.inc for vx800
by bari 27 Jun '09

27 Jun '09

Here are the two missing entry16 files for the vx800. -Bari /* This software and ancillary information (herein called SOFTWARE ) called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has been authored by an employee or employees of the University of California, operator of the Los Alamos National Laboratory under Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The U.S. Government has rights to use, reproduce, and distribute this SOFTWARE. The public may copy, distribute, prepare derivative works and publicly display this SOFTWARE without charge, provided that this Notice and any statement of authorship are reproduced on all copies. Neither the Government nor the University makes any warranty, express or implied, or assumes any liability or responsibility for the use of this SOFTWARE. If SOFTWARE is modified to produce derivative works, such modified SOFTWARE should be clearly marked, so as not to confuse it with the version available from LANL. */ /* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL * rminnich(a)lanl.gov */ /** Start code to put an i386 or later processor into 32-bit * protected mode. */ /* .section ".rom.text" */ #include <arch/rom_segs.h> .code16 .globl _start .type _start, @function _start: cli /* Save the BIST result */ movl %eax, %ebp /* 2008-12-2 added this----------*/ /*Open A20 */ /*inb $0x92, %al orb $0x2,%al outb %al, $0x92*/ /*;----------------------; ;Disable NMI and PARITY; ;----------------------; */ /*movb $0x8d,%al*/ /*; disable parity*/ /*outb %al, $0x70 movb $0xc,%al */ /*; disable NMI*/ /*outb %al, $0x61*/ /* 2008-12-2 added this---------*/ /* thanks to kmliu(a)sis.tw.com for this TBL fix ... */ /**/ /* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ /* any further code. Even though paging is disabled we could still get*/ /*false address translations due to the TLB if we didn't invalidate it.*/ /**/ xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ /* Invalidating the cache here seems to be a bad idea on * modern processors. Don't. * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. * If you cpu needs it you can write a cpu dependent version of * entry16.inc. */ /* Note: gas handles memory addresses in 16 bit code very poorly. * In particular it doesn't appear to have a directive allowing you * associate a section or even an absolute offset with a segment register. * * This means that anything except cs:ip relative offsets are * a real pain in 16 bit mode. And explains why it is almost * imposible to get gas to do lgdt correctly. * * One way to work around this is to have the linker do the * math instead of the assembler. This solves the very * pratical problem of being able to write code that can * be relocated. * * An lgdt call before we have memory enabled cannot be * position independent, as we cannot execute a call * instruction to get our current instruction pointer. * So while this code is relocateable it isn't arbitrarily * relocatable. * * The criteria for relocation have been relaxed to their * utmost, so that we can use the same code for both * our initial entry point and startup of the second cpu. * The code assumes when executing at _start that: * (((cs & 0xfff) == 0) and (ip == _start & 0xffff)) * or * ((cs == anything) and (ip == 0)). * * The restrictions in reset16.inc mean that _start initially * must be loaded at or above 0xffff0000 or below 0x100000. * * The linker scripts computs gdtptr16_offset by simply returning * the low 16 bits. This means that the intial segment used * when start is called must be 64K aligned. This should not * restrict the address as the ip address can be anything. */ movw %cs, %ax shlw $4, %ax movw $gdtptr16_offset, %bx subw %ax, %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Restore BIST to %eax */ movl %ebp, %eax /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp $ROM_CODE_SEG, $__protected_start /** * The gdt is defined in entry32.inc, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ .align 4 .globl gdtptr16 gdtptr16: .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ .globl _estart _estart: .code32 gdtptr16_offset = gdtptr16 & 0xffff; _start_offset = _start & 0xffff;

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build service results for r4376
by coreboot information 27 Jun '09

27 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4376 to the coreboot repository. This caused the following changes: Change Log: Add a target/ directory for the VIA EPIA-M700 board, so we can build it. Note that this board is nowhere near usable, further patches will follow and hopefully get this into buildable and usable shape. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4376&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4376&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4376 - in trunk/coreboot-v2/targets/via: . epia-m700
by svn＠coreboot.org 27 Jun '09

27 Jun '09

Author: uwe Date: 2009-06-27 18:06:51 +0200 (Sat, 27 Jun 2009) New Revision: 4376 Added: trunk/coreboot-v2/targets/via/epia-m700/ trunk/coreboot-v2/targets/via/epia-m700/Config.lb Log: Add a target/ directory for the VIA EPIA-M700 board, so we can build it. Note that this board is nowhere near usable, further patches will follow and hopefully get this into buildable and usable shape. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/coreboot-v2/targets/via/epia-m700/Config.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-m700/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/via/epia-m700/Config.lb 2009-06-27 16:06:51 UTC (rev 4376) @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target epia-m700 +mainboard via/epia-m700 + +romimage "image" + option COREBOOT_EXTRA_VERSION = "-epia-m700" + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "image"

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User:Hailfinger/Drafts/Women
by Joseph Smith 27 Jun '09

27 Jun '09

Carl-Daniel what does this have to do with anything? http://www.coreboot.org/User:Hailfinger/Drafts/Women -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[RFC] killing the old flashrom tree
by Carl-Daniel Hailfinger 27 Jun '09

27 Jun '09

Hi, it seems some people still try to check out the old flashrom repo. That code is not only ancient, it also lacks some fixes we have in newer code. I have the following two suggested options for deletion: 1. Remove the whole directory. 2. Remove all files in the directory and just keep the file which says the repo moved. Opinions? Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] SB600 suspend/S3 try
by Rudolf Marek 27 Jun '09

27 Jun '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I think for SB600 only very little is needed to get a chance that S3 will work. Please check the patch for AMD board dbm690t The patch is just an example and compile tested! Some (expected) problems: 1) the code which save/restore might not work - please check it! 2) the SuperIO chip might cut of the power to ram (for IT8712 check the 3vsb routine) 3) it will work on singlecore, dualcore maybe 4) it may corrupt CAR address area (it does not matter because not even ROM is there) Just a cert of origin: (not think this will go for SVN right now) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAko/6v8ACgkQ3J9wPJqZRNWBRgCfRqkrHxvTRz89n+1ya/YacPio SkQAoJGgFwguIi59ma0ro3BcaFJt0E+5 =UphE -----END PGP SIGNATURE-----

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patch tosuperiotool - add LPC47N252
by CybFr 27 Jun '09

27 Jun '09

Signed-off-by: François-Regis Vuillemin <coreboot(a)miradou.com -- FR

2 2

build service results for r4375
by coreboot information 27 Jun '09

27 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4375 to the coreboot repository. This caused the following changes: Change Log: Add dump support for SMSC LPC47N252. Signed-off-by: François-Regis Vuillemin <coreboot(a)miradou.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4375&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4375&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4375 - trunk/util/superiotool
by svn＠coreboot.org 27 Jun '09

27 Jun '09

Author: uwe Date: 2009-06-27 04:23:26 +0200 (Sat, 27 Jun 2009) New Revision: 4375 Modified: trunk/util/superiotool/smsc.c Log: Add dump support for SMSC LPC47N252. Signed-off-by: Fran?\195?\167ois-Regis Vuillemin <coreboot(a)miradou.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2009-06-26 15:53:07 UTC (rev 4374) +++ trunk/util/superiotool/smsc.c 2009-06-27 02:23:26 UTC (rev 4375) @@ -109,6 +109,45 @@ {0x00,0x00,0x00,EOT}}, {EOT}}}, {0x0e, "LPC47N252", { /* From sensors-detect */ + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x0e,NANA,0x00,0x00,0x04,0x04,NANA,NANA,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00, + 0x00,EOT}}, + {0x1, "Power management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2 / IRCC", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,0xf1, + 0xf2,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02, + 0x03,0x00,0x00,EOT}}, + {0x6, "Real-time clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x70,0x00,0x74,0x00,0x00,NANA,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox Interface", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "LPC/8051 addressable GPIO (LGPIO)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, {EOT}}}, {0x14, "LPC47M172", { {EOT}}},

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coreboot June 2009