coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

build service results for r4273
by coreboot information 13 May '09

13 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4273 to the coreboot repository. This caused the following changes: Change Log: Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Configuration of asus:m2v-mx_se has been fixed Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4273&device=s2891&vendor=t… Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4273&device=s2892&vendor=t… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] libpayload within option rom dir
by Jason Wang 13 May '09

13 May '09

Hi all, I have set up a new version usbrom[1] now. it can send out the char to serial port now. And I think there is a list of TODO which may include: 1. format the message which can send out by string(such as printf) 2. make the message can be displayed in screen. Dorileo, how do you think about that ? [1]http://vps.dorilex.net/cgi-bin/gitweb.cgi?p=usbrom.git;a=summary -- Jason Wang Peking University

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build service results for r4281
by coreboot information 13 May '09

13 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4281 to the coreboot repository. This caused the following changes: Change Log: Allow dynamic size for the {s,}elfboot bounce buffer. Use that to fix selfboot with compressed payloads. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4281&device=mew-am&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4281 - in trunk/coreboot-v2/src: arch/i386/boot arch/ppc/boot boot include/boot
by svn＠coreboot.org 13 May '09

13 May '09

Author: oxygene Date: 2009-05-13 18:27:25 +0200 (Wed, 13 May 2009) New Revision: 4281 Modified: trunk/coreboot-v2/src/arch/i386/boot/boot.c trunk/coreboot-v2/src/arch/ppc/boot/boot.c trunk/coreboot-v2/src/boot/elfboot.c trunk/coreboot-v2/src/boot/selfboot.c trunk/coreboot-v2/src/include/boot/elf.h Log: Allow dynamic size for the {s,}elfboot bounce buffer. Use that to fix selfboot with compressed payloads. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/boot.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/boot.c 2009-05-13 14:39:59 UTC (rev 4280) +++ trunk/coreboot-v2/src/arch/i386/boot/boot.c 2009-05-13 16:27:25 UTC (rev 4281) @@ -68,7 +68,7 @@ } -void jmp_to_elf_entry(void *entry, unsigned long buffer) +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long bounce_size) { extern unsigned char _ram_seg, _eram_seg; unsigned long lb_start, lb_size; @@ -79,7 +79,7 @@ lb_start = (unsigned long)&_ram_seg; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); - adjust = buffer + lb_size - lb_start; + adjust = buffer + bounce_size - lb_start; adjusted_boot_notes = (unsigned long)&elf_boot_notes; adjusted_boot_notes += adjust; Modified: trunk/coreboot-v2/src/arch/ppc/boot/boot.c =================================================================== --- trunk/coreboot-v2/src/arch/ppc/boot/boot.c 2009-05-13 14:39:59 UTC (rev 4280) +++ trunk/coreboot-v2/src/arch/ppc/boot/boot.c 2009-05-13 16:27:25 UTC (rev 4281) @@ -16,7 +16,7 @@ } -void jmp_to_elf_entry(void *entry, unsigned long buffer) +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long bounce_size) { void (*kernel_entry)(void); Modified: trunk/coreboot-v2/src/boot/elfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/elfboot.c 2009-05-13 14:39:59 UTC (rev 4280) +++ trunk/coreboot-v2/src/boot/elfboot.c 2009-05-13 16:27:25 UTC (rev 4281) @@ -122,6 +122,8 @@ * */ +static unsigned long bounce_size; + static unsigned long get_bounce_buffer(struct lb_memory *mem) { unsigned long lb_size; @@ -130,7 +132,8 @@ int i; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); /* Double coreboot size so I have somewhere to place a copy to return to */ - lb_size = lb_size + lb_size; + bounce_size = lb_size; + lb_size = bounce_size + lb_size; mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); buffer = 0; for(i = 0; i < mem_entries; i++) { @@ -610,7 +613,7 @@ post_code(0xfe); /* Jump to kernel */ - jmp_to_elf_entry(entry, bounce_buffer); + jmp_to_elf_entry(entry, bounce_buffer, bounce_size); return 1; out: Modified: trunk/coreboot-v2/src/boot/selfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/selfboot.c 2009-05-13 14:39:59 UTC (rev 4280) +++ trunk/coreboot-v2/src/boot/selfboot.c 2009-05-13 16:27:25 UTC (rev 4281) @@ -92,7 +92,9 @@ * */ -static unsigned long get_bounce_buffer(struct lb_memory *mem) +static unsigned long bounce_size, bounce_buffer; + +static void get_bounce_buffer(struct lb_memory *mem, unsigned long bounce_size) { unsigned long lb_size; unsigned long mem_entries; @@ -100,7 +102,7 @@ int i; lb_size = (unsigned long)(&_eram_seg - &_ram_seg); /* Double coreboot size so I have somewhere to place a copy to return to */ - lb_size = lb_size + lb_size; + lb_size = bounce_size + lb_size; mem_entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); buffer = 0; for(i = 0; i < mem_entries; i++) { @@ -123,7 +125,7 @@ continue; buffer = tbuffer; } - return buffer; + bounce_buffer = buffer; } static int valid_area(struct lb_memory *mem, unsigned long buffer, @@ -180,24 +182,34 @@ return 1; } +static const unsigned long lb_start = (unsigned long)&_ram_seg; +static const unsigned long lb_end = (unsigned long)&_eram_seg; + +static int overlaps_coreboot(struct segment *seg) +{ + unsigned long start, end; + start = seg->s_dstaddr; + end = start + seg->s_memsz; + return !((end <= lb_start) || (start >= lb_end)); +} + static void relocate_segment(unsigned long buffer, struct segment *seg) { /* Modify all segments that want to load onto coreboot * to load onto the bounce buffer instead. */ - unsigned long lb_start = (unsigned long)&_ram_seg; - unsigned long lb_end = (unsigned long)&_eram_seg; unsigned long start, middle, end; printk_spew("lb: [0x%016lx, 0x%016lx)\n", lb_start, lb_end); + /* I don't conflict with coreboot so get out of here */ + if (!overlaps_coreboot(seg)) + return; + start = seg->s_dstaddr; middle = start + seg->s_filesz; end = start + seg->s_memsz; - /* I don't conflict with coreboot so get out of here */ - if ((end <= lb_start) || (start >= lb_end)) - return; printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", start, middle, end); @@ -297,7 +309,7 @@ static int build_self_segment_list( struct segment *head, - unsigned long bounce_buffer, struct lb_memory *mem, + struct lb_memory *mem, struct cbfs_payload *payload, u32 *entry) { struct segment *new; @@ -369,32 +381,47 @@ new->phdr_prev = head->phdr_prev; head->phdr_prev->phdr_next = new; head->phdr_prev = new; - - /* Verify the memory addresses in the segment are valid */ - if (!valid_area(mem, bounce_buffer, new->s_dstaddr, new->s_memsz)) - goto out; - - /* Modify the segment to load onto the bounce_buffer if necessary. - */ - relocate_segment(bounce_buffer, new); } return 1; - out: - return 0; } static int load_self_segments( - struct segment *head, struct cbfs_payload *payload) + struct segment *head, + struct lb_memory *mem, + struct cbfs_payload *payload) { unsigned long offset; struct segment *ptr; offset = 0; + unsigned long required_bounce_size = lb_end - lb_start; for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (!overlaps_coreboot(ptr)) continue; + unsigned long bounce = ptr->s_dstaddr + ptr->s_memsz - lb_start; + if (bounce > required_bounce_size) required_bounce_size = bounce; + } + get_bounce_buffer(mem, required_bounce_size); + if (!bounce_buffer) { + printk_err("Could not find a bounce buffer...\n"); + return 0; + } + for(ptr = head->next; ptr != head; ptr = ptr->next) { + /* Verify the memory addresses in the segment are valid */ + if (!valid_area(mem, bounce_buffer, ptr->s_dstaddr, ptr->s_memsz)) + return 0; + } + for(ptr = head->next; ptr != head; ptr = ptr->next) { unsigned char *dest, *middle, *end, *src; printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); + /* Modify the segment to load onto the bounce_buffer if necessary. + */ + relocate_segment(bounce_buffer, ptr); + + printk_debug("Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", + ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); + /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); src = (unsigned char *)(ptr->s_srcaddr); @@ -454,21 +481,13 @@ { u32 entry=0; struct segment head; - unsigned long bounce_buffer; - /* Find a bounce buffer so I can load to coreboot's current location */ - bounce_buffer = get_bounce_buffer(mem); - if (!bounce_buffer) { - printk_err("Could not find a bounce buffer...\n"); - goto out; - } - /* Preprocess the self segments */ - if (!build_self_segment_list(&head, bounce_buffer, mem, payload, &entry)) + if (!build_self_segment_list(&head, mem, payload, &entry)) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, mem, payload)) goto out; printk_spew("Loaded segments\n"); @@ -480,7 +499,7 @@ post_code(0xfe); /* Jump to kernel */ - jmp_to_elf_entry((void*)entry, bounce_buffer); + jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); return 1; out: Modified: trunk/coreboot-v2/src/include/boot/elf.h =================================================================== --- trunk/coreboot-v2/src/include/boot/elf.h 2009-05-13 14:39:59 UTC (rev 4280) +++ trunk/coreboot-v2/src/include/boot/elf.h 2009-05-13 16:27:25 UTC (rev 4281) @@ -390,7 +390,7 @@ #endif int elf_check_arch(Elf_ehdr *ehdr); -void jmp_to_elf_entry(void *entry, unsigned long buffer); +void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long bounce_size); struct lb_memory; int elfboot(struct lb_memory *mem); /* Temporary compile fix, FILO should be dropped from coreboot */

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[flashrom] r502 - trunk
by svn＠coreboot.org 13 May '09

13 May '09

Author: uwe Date: 2009-05-13 17:57:38 +0200 (Wed, 13 May 2009) New Revision: 502 Modified: trunk/flashchips.c Log: Mark SST 39VF512 as fully tested. Tested with 3COM 3C905C: EtherLink 10/100 PCI (TX) http://www.coreboot.org/pipermail/coreboot/2009-May/048163.html Signed-off-by: Mateusz Murawski <matowy(a)tlen.pl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-13 12:01:57 UTC (rev 501) +++ trunk/flashchips.c 2009-05-13 15:57:38 UTC (rev 502) @@ -1375,7 +1375,7 @@ .model_id = SST_39VF512, .total_size = 64, .page_size = 4096, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002,

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[PATCH]Fix selfboot bounce buffer handling
by Patrick Georgi 13 May '09

13 May '09

Hi, attached patches do: * dynamic-bounce-buffer-size Eliminate the assumption that the bouncebuffer is twice the size of coreboot. * flexible-self-bounce-buffer Bouncebuffer handling with compressed segments was changed so that the entire segment ends up in the buffer and isn't split into "overlaps coreboot" and "doesn't overlap coreboot". That can lead to problems if the segment is larger than coreboot, incl. corruption of the high memory tables, or crashes in extreme cases. This patch builds on dynamic-bounce-buffer-size and allocates the bouncebuffer so that all segments that overlap coreboot fit into it entirely. * update-comments Update comments accordingly The patches have some different line numbers than upstream, but apply correctly. The remaining changes are just debug prints. Tested on Kontron. Together with the other patch by me this morning and the commited FILO change, ACPI and e820 tables are seen correctly by Linux. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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build service results for r4280
by coreboot information 13 May '09

13 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4280 to the coreboot repository. This caused the following changes: Change Log: Make ACPI with low and high tables work again. The RSDP contained a bogus RSDT pointer due to a wrong order of commands. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4280&device=mew-am&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4280 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 13 May '09

13 May '09

Author: oxygene Date: 2009-05-13 16:39:59 +0200 (Wed, 13 May 2009) New Revision: 4280 Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c Log: Make ACPI with low and high tables work again. The RSDP contained a bogus RSDT pointer due to a wrong order of commands. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-05-13 02:48:58 UTC (rev 4279) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-05-13 14:39:59 UTC (rev 4280) @@ -116,14 +116,16 @@ #if HAVE_HIGH_TABLES == 1 #if HAVE_LOW_TABLES == 1 unsigned long high_rsdp=ALIGN(high_table_end, 16); - unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address); - acpi_write_rsdp(rom_table_end, rsdt_location); - rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16); #endif if (high_tables_base) { high_table_end = write_acpi_tables(high_table_end); high_table_end = (high_table_end+1023) & ~1023; } +#if HAVE_LOW_TABLES == 1 + unsigned long rsdt_location=(unsigned long*)(((acpi_rsdp_t*)high_rsdp)->rsdt_address); + acpi_write_rsdp(rom_table_end, rsdt_location); + rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16); +#endif #else #if HAVE_LOW_TABLES == 1 rom_table_end = write_acpi_tables(rom_table_end);

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[PATCH]Fix ACPI in HIGH-and-LOW tables configuration
by Patrick Georgi 13 May '09

13 May '09

Hi, I messed up and added some "harmless" code right before pushing this change. Just that it wasn't harmless. I'm sorry. Anyway, with this patch, ACPI works again for setups with both HAVE_HIGH_TABLES and HAVE_LOW_TABLES, as the RSDP contains valid data now (without it the RSDT is bogus: it is read out before it is written) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

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[flashrom] r501 - trunk
by svn＠coreboot.org 13 May '09

13 May '09

Author: uwe Date: 2009-05-13 14:01:57 +0200 (Wed, 13 May 2009) New Revision: 501 Modified: trunk/nic3com.c Log: Fix nic3com.c build issues on *BSD (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-13 11:40:08 UTC (rev 500) +++ trunk/nic3com.c 2009-05-13 12:01:57 UTC (rev 501) @@ -20,8 +20,10 @@ #include <stdlib.h> #include <string.h> +#include <fcntl.h> +#include <sys/types.h> +#include <sys/stat.h> #include <errno.h> -#include <sys/io.h> #include <pci/pci.h> #include "flash.h" @@ -37,6 +39,10 @@ uint32_t io_base_addr; struct pci_access *pacc; +#if defined(__FreeBSD__) || defined(__DragonFly__) +int io_fd; +#endif + #define OK 0 #define NT 1 /* Not tested */

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coreboot May 2009