coreboot May 2009

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[PATCH] flashrom: Downgrade all SST25* chips to 1-byte write
by Carl-Daniel Hailfinger 14 May '09

14 May '09

SST25 chips do not support page program, only byte program. Downgrade the chips from 256-byte writes to 1-byte writes. This fixes writing to them on ICH/VIA SPI masters. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sst_1byte_write/flashchips.c =================================================================== --- flashrom-sst_1byte_write/flashchips.c (Revision 498) +++ flashrom-sst_1byte_write/flashchips.c (Arbeitskopie) @@ -1168,7 +1168,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1182,7 +1182,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1196,7 +1196,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1210,7 +1210,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_60, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1224,7 +1224,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_c7, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = spi_chip_read, }, -- http://www.hailfinger.org/ Index: flashrom-sst25_1byte_write/flashchips.c =================================================================== --- flashrom-sst25_1byte_write/flashchips.c (Revision 498) +++ flashrom-sst25_1byte_write/flashchips.c (Arbeitskopie) @@ -1168,7 +1168,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1182,7 +1182,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1196,7 +1196,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1210,7 +1210,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_60, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1224,7 +1224,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_c7, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = spi_chip_read, },

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[flashrom] r504 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: hailfinger Date: 2009-05-14 00:19:12 +0200 (Thu, 14 May 2009) New Revision: 504 Modified: trunk/flashchips.c Log: SST25 chips do not support page program, only byte program. Downgrade the chips from 256-byte writes to 1-byte writes. This fixes writing to them on ICH/VIA SPI masters. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: FENG Yu Ning <fengyuning1984(a)gmail.com> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-13 22:18:35 UTC (rev 503) +++ trunk/flashchips.c 2009-05-13 22:19:12 UTC (rev 504) @@ -1182,7 +1182,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1196,7 +1196,7 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1210,7 +1210,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .erase = spi_chip_erase_c7, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1224,7 +1224,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_60, - .write = spi_chip_write_256, + .write = spi_chip_write_1, .read = spi_chip_read, }, @@ -1238,7 +1238,7 @@ .tested = TEST_OK_PR, .probe = probe_spi_rems, .erase = spi_chip_erase_c7, - .write = spi_aai_write, + .write = spi_chip_write_1, .read = spi_chip_read, },

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flashrom: Winbond W39V040A PR tested
by Mateusz Murawski 14 May '09

14 May '09

Hi Tested on MSI MS-7191 flashrom v0.9.0-r501 No coreboot table found. Found chipset "ATI SB400", enabling flash write... OK. Calibrating delay loop... OK. Found chip "Winbond W39V040A" (512 KB) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading flash... done. Signed-off-by: Mateusz Murawski <matowy at tlen.pl> --- flashchips.c.old 2009-05-13 19:50:12.000000000 +0200 +++ flashchips.c 2009-05-13 19:49:02.000000000 +0200 @@ -2145,7 +2145,7 @@ .model_id = W_39V040A, .total_size = 512, .page_size = 64*1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002,

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[flashrom] r503 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: stuge Date: 2009-05-14 00:18:35 +0200 (Thu, 14 May 2009) New Revision: 503 Modified: trunk/flashchips.c Log: Winbond W39V040A TEST_OK_ PROBE READ Thanks to Mateusz for testing and reporting! Signed-off-by: Mateusz Murawski <matowy(a)tlen.pl> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-13 15:57:38 UTC (rev 502) +++ trunk/flashchips.c 2009-05-13 22:18:35 UTC (rev 503) @@ -2145,7 +2145,7 @@ .model_id = W_39V040A, .total_size = 512, .page_size = 64*1024, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002,

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[cbfstool] [PATCH] add string types for add command
by Ward Vandewege 13 May '09

13 May '09

See attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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build service results for r4283
by coreboot information 13 May '09

13 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ward" checked in revision 4283 to the coreboot repository. This caused the following changes: Change Log: This patch fixes a segfault when a file too large to fit is added to a rom image. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4283&device=mew-am&vendor=… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4282
by coreboot information 13 May '09

13 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4282 to the coreboot repository. This caused the following changes: Change Log: Add support for human-friendly component string types for the cbfstool add command. Make use of it in config.g (Myles) Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4282&device=mew-am&vendor=… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[cbfstool] [PATCH] fix segfault when adding file that won't fit
by Ward Vandewege 13 May '09

13 May '09

See attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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[v2] r4283 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 13 May '09

13 May '09

Author: ward Date: 2009-05-13 22:11:04 +0200 (Wed, 13 May 2009) New Revision: 4283 Modified: trunk/coreboot-v2/util/cbfstool/fs.c Log: This patch fixes a segfault when a file too large to fit is added to a rom image. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/util/cbfstool/fs.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/fs.c 2009-05-13 20:08:28 UTC (rev 4282) +++ trunk/coreboot-v2/util/cbfstool/fs.c 2009-05-13 20:11:04 UTC (rev 4283) @@ -99,7 +99,7 @@ { /* walk the rom and find an empty file with a base > base, and a large enough size */ unsigned int offset = ntohl(rom->header->offset); - unsigned int ret = -1; + int ret = -1; struct cbfs_file *c = NULL; unsigned long nextoffset, truncoffset; struct cbfs_file *newfile = NULL;

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[v2] r4282 - in trunk/coreboot-v2/util: cbfstool newconfig
by svn＠coreboot.org 13 May '09

13 May '09

Author: myles Date: 2009-05-13 22:08:28 +0200 (Wed, 13 May 2009) New Revision: 4282 Modified: trunk/coreboot-v2/util/cbfstool/add.c trunk/coreboot-v2/util/newconfig/config.g Log: Add support for human-friendly component string types for the cbfstool add command. Make use of it in config.g (Myles) Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/util/cbfstool/add.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/add.c 2009-05-13 16:27:25 UTC (rev 4281) +++ trunk/coreboot-v2/util/cbfstool/add.c 2009-05-13 20:08:28 UTC (rev 4282) @@ -219,6 +219,22 @@ ("add-payload FILE NAME [OPTIONS]\tAdd a payload to the ROM\n"); } +int select_component_type(char *s) +{ + int i = 0; + char *accepted_strings[] = { + "stage", + "payload", + "optionrom", + "deleted", + "free", + }; + for (i=0; i < 5; i++) + if (!strcmp(s, accepted_strings[i])) + return i; + return -1; +} + int add_handler(struct rom *rom, int argc, char **argv) { unsigned int type = CBFS_COMPONENT_NULL; @@ -233,13 +249,33 @@ return -1; } + int component_type; + /* There are two ways to specify the type - a string or a number */ if (isdigit(*(argv[2]))) type = strtoul(argv[2], 0, 0); else { - ERROR("String types (%s) aren't implemented yet.\n", argv[2]); - return -1; + switch( component_type = select_component_type(argv[2])) { + case 0: + type = CBFS_COMPONENT_STAGE; + break; + case 1: + type = CBFS_COMPONENT_PAYLOAD; + break; + case 2: + type = CBFS_COMPONENT_OPTIONROM; + break; + case 3: + type = CBFS_COMPONENT_DELETED; + break; + case 4: + type = CBFS_COMPONENT_NULL; + break; + default: + ERROR("Unrecognized component type %s.\nValid options are: stage, payload, optionrom, deleted, free.\n", argv[2]); + return -1; + } } return add_blob(rom, argv[0], argv[1], type); Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-05-13 16:27:25 UTC (rev 4281) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-05-13 20:08:28 UTC (rev 4282) @@ -2298,7 +2298,7 @@ file.write("\t./cbfstool %s create %s %s %s.bootblock\n" %(i.name, romsize, bootblocksize, i.name)) for j in pciroms: - file.write("\t./cbfstool %s add %s pci%04x,%04x.rom 48\n" % (i.name, j.name, j.pci_vid, j.pci_did)) + file.write("\t./cbfstool %s add %s pci%04x,%04x.rom optionrom\n" % (i.name, j.name, j.pci_vid, j.pci_did)) for j in i.roms: #failover is a hack that will go away soon. if (j != "failover") and (rommapping[j] != "/dev/null"):

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coreboot May 2009