coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

Fwd: FW: Google Alert - "cme group"
by ron minnich 12 May '09

12 May '09

Exciting!, ron From: Google Alerts [mailto:googlealerts-noreply@google.com] Google News Alert for: "cme group" CME Group Dives Into 'Coreboot' and Other Linux Open Source Projects Wall Street & Technology - New York,NY,USA By Ivy Schmerken CME Group, the world's largest derivatives exchange operator, is diving deeper into the Linux open source movement to influence the ... See all stories on this topic ________________________________ This as-it-happens Google Alert is brought to you by Google. Remove this alert. Create another alert. Manage your alerts.

2 1

qemu, v2, latest
by ron minnich 12 May '09

12 May '09

if failing for me with a seabios payload. Not a filo payload, mind you. The failure is odd. It seems to be dying at first instruction with a triple fault. Anyway, ideas welcome :-) Devices initialized Copying Interrupt Routing Table to 0x000f0000... done. Moving GDT to 0x500...ok Multiboot Information structure has been written. Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f04b8 to 0x00100000 Wrote coreboot table at: 00000530 - 00000bc0 checksum bda7 Check CBFS header at fffeffd0 magic is 4f524243 Found CBFS header at fffeffd0 Check normal/payload Got a payload Segment fff80028 data: New segment dstaddr 0xf0000 memsize 0x10000 srcaddr 0xfff80060 filesize 0x10000 (cleaned up) New segment addr 0xf0000 size 0x10000 offset 0xfff80060 filesize 0x10000 Payload is overwriting Coreboot tables. Segment fff80044 Entry 000fa684 Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000 it's not compressed! Jumping to boot code at fa684 qemu: fatal: triple fault EAX=2badb002 EBX=000f0400 ECX=00000000 EDX=00012000 ESI=03fee000 EDI=00016000 EBP=000fa684 ESP=03ffbe9c EIP=000fa684 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0 ES =0018 00000000 ffffffff 00cf9300 CS =0010 00000000 ffffffff 00cf9b00 SS =0018 00000000 ffffffff 00cf9300 DS =0018 00000000 ffffffff 00cf9300 FS =0018 00000000 ffffffff 00cf9300 GS =0018 00000000 ffffffff 00cf9300 LDT=0000 00000000 0000ffff 00008000 TR =0000 00000000 0000ffff 00008000 GDT= 00000500 00000027 IDT= 0000d100 0000009f CR0=60000011 CR2=00000000 CR3=00000000 CR4=00000000 CCS=00009000 CCD=00004800 CCO=SARL FCW=037f FSW=0000 [ST=0] FTW=00 MXCSR=00001f80 FPR0=0000000000000000 0000 FPR1=0000000000000000 0000 FPR2=0000000000000000 0000 FPR3=0000000000000000 0000 FPR4=0000000000000000 0000 FPR5=0000000000000000 0000 FPR6=0000000000000000 0000 FPR7=0000000000000000 0000 XMM00=00000000000000000000000000000000 XMM01=00000000000000000000000000000000 XMM02=00000000000000000000000000000000 XMM03=00000000000000000000000000000000 XMM04=00000000000000000000000000000000 XMM05=00000000000000000000000000000000 XMM06=00000000000000000000000000000000 XMM07=00000000000000000000000000000000 Aborted This seabios was built locally from organically harvested electrons. Thanks ron

2 5

[PATCH] flashrom: Use helper functions to access flash chips
by Carl-Daniel Hailfinger 12 May '09

12 May '09

The semantic patch I used in r418 to make the original conversion to accessor functions was missing one isomorphism: a[b] <=> *(a+b) The semantic patcher Coccinelle was used to create this patch. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + chip_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + chip_readb(b) @@ type T; T b; @@ ( chip_readb | chip_writeb ) (..., - (T) - (b) + b ) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-inband_chipaccess_helper_functions/jedec.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/jedec.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/jedec.c (Arbeitskopie) @@ -331,8 +331,8 @@ erase_chip_jedec(flash); // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != (uint8_t) 0xff) { - printf("ERASE FAILED @%d, val %02x!\n", i, bios[i]); + if (chip_readb(bios + i) != (uint8_t) 0xff) { + printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i)); return -1; } } Index: flashrom-inband_chipaccess_helper_functions/w39v040c.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v040c.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/w39v040c.c (Arbeitskopie) @@ -67,8 +67,8 @@ erase_sector_jedec(flash->virtual_memory, i); for (i = 0; i < total_size; i++) - if (0xff != bios[i]) { - printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, bios[i]); + if (0xff != chip_readb(bios + i)) { + printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, chip_readb(bios + i)); return -1; } Index: flashrom-inband_chipaccess_helper_functions/sst_fwhub.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Arbeitskopie) @@ -122,7 +122,7 @@ // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { + if (chip_readb(bios + i) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-inband_chipaccess_helper_functions/w39v080fa.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Arbeitskopie) @@ -180,8 +180,8 @@ printf("\n"); for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { - fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, bios[i]); + if (chip_readb(bios + i) != 0xff) { + fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, chip_readb(bios + i)); return -1; } } -- http://www.hailfinger.org/ Index: flashrom-inband_chipaccess_helper_functions/jedec.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/jedec.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/jedec.c (Arbeitskopie) @@ -331,8 +331,8 @@ erase_chip_jedec(flash); // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != (uint8_t) 0xff) { - printf("ERASE FAILED @%d, val %02x!\n", i, bios[i]); + if (chip_readb(bios + i) != (uint8_t) 0xff) { + printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i)); return -1; } } Index: flashrom-inband_chipaccess_helper_functions/w39v040c.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v040c.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/w39v040c.c (Arbeitskopie) @@ -67,8 +67,8 @@ erase_sector_jedec(flash->virtual_memory, i); for (i = 0; i < total_size; i++) - if (0xff != bios[i]) { - printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, bios[i]); + if (0xff != chip_readb(bios + i)) { + printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, chip_readb(bios + i)); return -1; } Index: flashrom-inband_chipaccess_helper_functions/sst_fwhub.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/sst_fwhub.c (Arbeitskopie) @@ -122,7 +122,7 @@ // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { + if (chip_readb(bios + i) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Index: flashrom-inband_chipaccess_helper_functions/w39v080fa.c =================================================================== --- flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Revision 496) +++ flashrom-inband_chipaccess_helper_functions/w39v080fa.c (Arbeitskopie) @@ -180,8 +180,8 @@ printf("\n"); for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { - fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, bios[i]); + if (chip_readb(bios + i) != 0xff) { + fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, chip_readb(bios + i)); return -1; } }

2 2

[flashrom] r498 - trunk
by svn＠coreboot.org 12 May '09

12 May '09

Author: hailfinger Date: 2009-05-12 17:38:55 +0200 (Tue, 12 May 2009) New Revision: 498 Modified: trunk/jedec.c trunk/sst_fwhub.c trunk/w39v040c.c trunk/w39v080fa.c Log: Use helper functions chip_{read,write}[bwl] to access flash chips. The semantic patch I used in r418 to make the original conversion to accessor functions was missing one isomorphism: a[b] <=> *(a+b) The semantic patcher Coccinelle was used to create this patch. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + chip_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + chip_readb(b) @@ type T; T b; @@ ( chip_readb | chip_writeb ) (..., - (T) - (b) + b ) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-05-12 14:06:04 UTC (rev 497) +++ trunk/jedec.c 2009-05-12 15:38:55 UTC (rev 498) @@ -331,8 +331,8 @@ erase_chip_jedec(flash); // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != (uint8_t) 0xff) { - printf("ERASE FAILED @%d, val %02x!\n", i, bios[i]); + if (chip_readb(bios + i) != (uint8_t) 0xff) { + printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i)); return -1; } } Modified: trunk/sst_fwhub.c =================================================================== --- trunk/sst_fwhub.c 2009-05-12 14:06:04 UTC (rev 497) +++ trunk/sst_fwhub.c 2009-05-12 15:38:55 UTC (rev 498) @@ -122,7 +122,7 @@ // dumb check if erase was successful. for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { + if (chip_readb(bios + i) != 0xff) { printf("ERASE FAILED!\n"); return -1; } Modified: trunk/w39v040c.c =================================================================== --- trunk/w39v040c.c 2009-05-12 14:06:04 UTC (rev 497) +++ trunk/w39v040c.c 2009-05-12 15:38:55 UTC (rev 498) @@ -67,8 +67,8 @@ erase_sector_jedec(flash->virtual_memory, i); for (i = 0; i < total_size; i++) - if (0xff != bios[i]) { - printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, bios[i]); + if (0xff != chip_readb(bios + i)) { + printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, chip_readb(bios + i)); return -1; } Modified: trunk/w39v080fa.c =================================================================== --- trunk/w39v080fa.c 2009-05-12 14:06:04 UTC (rev 497) +++ trunk/w39v080fa.c 2009-05-12 15:38:55 UTC (rev 498) @@ -180,8 +180,8 @@ printf("\n"); for (i = 0; i < total_size; i++) { - if (bios[i] != 0xff) { - fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, bios[i]); + if (chip_readb(bios + i) != 0xff) { + fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, chip_readb(bios + i)); return -1; } }

1 0

build service results for r4274
by coreboot information 12 May '09

12 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4274 to the coreboot repository. This caused the following changes: Change Log: I guess a couple of function calls pushed these boards over the 0x1700 edge on the build server. Add Config-abuild.lb to fix s2892 & s2891. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4277 - in trunk/coreboot-v2: src/mainboard/hp/dl145_g3 targets/hp/dl145_g3
by svn＠coreboot.org 12 May '09

12 May '09

Author: myles Date: 2009-05-12 17:15:07 +0200 (Tue, 12 May 2009) New Revision: 4277 Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb Log: This is the final patch that got everything working for me with the HP dl145g3. I would like to remind you that this firmware enables the hardware virtualization on the AMD cpu's on the machine. That feature was explicitly disabled by the factory BIOS. Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS) than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read config space of a device that is actually not present. Because SeaBIOS does not support AHCI SATA it can not start the bootable drive of the machine so i had to add filo to seabios to manage booting: ./cbfstool coreboot.rom add-payload filo.elf img/FILO Signed-off-by: Samuel Verstraete <samuel.verstraete(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb 2009-05-12 15:06:54 UTC (rev 4276) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Config.lb 2009-05-12 15:15:07 UTC (rev 4277) @@ -192,15 +192,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - chip drivers/pci/onboard - # it is in bcm5785_0 bus, but the device id can - # not be changed even unitid is changed, fake one - # to get the rom_address - # if HT_CHAIN_END_UNITID_BASE=0, it is 4, - # if HT_CHAIN_END_UNITID_BASE=1, it is 3 - device pci 4.0 on end - register "rom_address" = "0xfff00000" - end + device pci 3.0 on end # VGA + #bx_a013+ start #chip drivers/pci/onboard #SATA2 # device pci 5.0 on end Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-05-12 15:06:54 UTC (rev 4276) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-05-12 15:15:07 UTC (rev 4277) @@ -194,7 +194,7 @@ #VGA Console default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 +default CONFIG_PCI_ROM_RUN=0 #HT Unit ID offset, default is 1, the typical one default HT_CHAIN_UNITID_BASE=0x06 Modified: trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb 2009-05-12 15:06:54 UTC (rev 4276) +++ trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb 2009-05-12 15:15:07 UTC (rev 4277) @@ -13,13 +13,7 @@ option ROM_SIZE=1024*(1024-32) option FALLBACK_SIZE=1024*512 -romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION=".0-normal" - payload __PAYLOAD__ -end +option CONFIG_CBFS = 1 romimage "fallback" option USE_FALLBACK_IMAGE=1 @@ -29,5 +23,5 @@ payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" Modified: trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb =================================================================== --- trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb 2009-05-12 15:06:54 UTC (rev 4276) +++ trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb 2009-05-12 15:15:07 UTC (rev 4277) @@ -24,23 +24,18 @@ target dl145_g3 mainboard hp/dl145_g3 -# Leave 32K for VGA ROM -option ROM_SIZE= 1024*1024 - 32*1024 +option ROM_SIZE= 1024*1024 +option CONFIG_CBFS = 1 -romimage "normal" - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - payload ../payload.elf -end - romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - payload ../payload.elf + payload ./bios.bin.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback" + +pci_rom ./matrox.rom vendor_id=0x102b device_id=0x0522 +

1 0

[v2] r4276 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 12 May '09

12 May '09

Author: rminnich Date: 2009-05-12 17:06:54 +0200 (Tue, 12 May 2009) New Revision: 4276 Modified: trunk/coreboot-v2/util/cbfstool/fs.c Log: This fixes a rather silly bug in cbfs with filenames > 16 characters. Tested to booting linux with qemu. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson<mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/util/cbfstool/fs.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/fs.c 2009-05-12 14:24:25 UTC (rev 4275) +++ trunk/coreboot-v2/util/cbfstool/fs.c 2009-05-12 15:06:54 UTC (rev 4276) @@ -95,7 +95,7 @@ * @param size the size of the file needed * @returns pointer to a cbfs_file struct. */ -struct cbfs_file * rom_alloc(struct rom *rom, unsigned long size) +struct cbfs_file * rom_alloc(struct rom *rom, const char *name, unsigned long size, int type) { /* walk the rom and find an empty file with a base > base, and a large enough size */ unsigned int offset = ntohl(rom->header->offset); @@ -103,6 +103,7 @@ struct cbfs_file *c = NULL; unsigned long nextoffset, truncoffset; struct cbfs_file *newfile = NULL; + unsigned int csize; while (offset < rom->fssize) { @@ -113,7 +114,7 @@ offset += ALIGN(ntohl(c->offset) + ntohl(c->len), ntohl(rom->header->align)); continue; - } + } /* Is this file big enough for our needs? */ if (ntohl(c->len) >= size){ ret = offset; @@ -132,10 +133,10 @@ /* figure out the real end of this file, and hence the size */ /* compute where the next file is */ - nextoffset = ALIGN(ret + ntohl(c->len) + headersize((char *)CBFS_NAME(c)), + nextoffset = ALIGN(ret + ntohl(c->len) + headersize(name), ntohl(rom->header->align)); /* compute where the end of this new file might be */ - truncoffset = ALIGN(ret + size + headersize((char *)CBFS_NAME(c)), + truncoffset = ALIGN(ret + size + headersize(name), ntohl(rom->header->align)); /* If there is more than align bytes difference, create a new empty file */ /* later, we can add code to merge all empty files. */ @@ -149,6 +150,16 @@ c->len = htonl(size); + csize = headersize(name); + + strcpy(c->magic, COMPONENT_MAGIC); + + c->offset = htonl(csize); + + c->type = htonl(type); + + setname(c, name); + return ((struct cbfs_file *)ROM_PTR(rom, ret)); } @@ -264,32 +275,21 @@ */ int rom_add(struct rom *rom, const char *name, void *buffer, int size, int type) { - struct cbfs_file *c = rom_alloc(rom, size); - int offset; - int csize; + struct cbfs_file *c; if (rom_find_by_name(rom, name)) { ERROR("Component %s already exists in this rom\n", name); return -1; } + c = rom_alloc(rom, name, size, type); + if (c == NULL) { ERROR("There is no more room in this ROM\n"); return -1; } - csize = headersize(name); - - offset = ROM_OFFSET(rom, c); - - strcpy(c->magic, COMPONENT_MAGIC); - - c->offset = htonl(csize); - c->type = htonl(type); - - setname(c, name); - - memcpy(((unsigned char *)c) + csize, buffer, size); + memcpy(((unsigned char *)c) + ntohl(c->offset), buffer, size); return 0; }

1 0

build service results for r4272
by coreboot information 12 May '09

12 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4272 to the coreboot repository. This caused the following changes: Change Log: Fix pdflatex build issues (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4272&device=m2v-mx_se&vend… Compilation of tyan:s2891 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4272&device=s2891&vendor=t… Compilation of tyan:s2892 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4272&device=s2892&vendor=t… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] flashrom: Drop duplicate write_39sf020()
by Uwe Hermann 12 May '09

12 May '09

See patch. We should also rename w49f002u.c in another patch to something more generic, that code is in no way specific to the w49f002u. Maybe even put the only function in that file (byte-wise JEDEC writes of one page/sector) into jedec.c? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[v2] r4275 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 12 May '09

12 May '09

Author: uwe Date: 2009-05-12 16:24:25 +0200 (Tue, 12 May 2009) New Revision: 4275 Modified: trunk/coreboot-v2/documentation/Makefile Log: There's no 'svg2pdf' in Debian AFAICT, probably the same problem on other systems too. So, check for svg2pdf, convert, and inkscape and use the first one that is found to convert the SVG files to PDF. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/documentation/Makefile =================================================================== --- trunk/coreboot-v2/documentation/Makefile 2009-05-12 14:14:54 UTC (rev 4274) +++ trunk/coreboot-v2/documentation/Makefile 2009-05-12 14:24:25 UTC (rev 4275) @@ -9,12 +9,27 @@ all: LinuxBIOS-AMD64.pdf +SVG2PDF=$(shell which svg2pdf) +INKSCAPE=$(shell which inkscape) +CONVERT=$(shell which convert) codeflow.pdf: codeflow.svg +ifneq ($(strip $(SVG2PDF)),) svg2pdf $< $@ +else ifneq ($(strip $(INKSCAPE)),) + inkscape $< --export-pdf=$@ +else ifneq ($(strip $(CONVERT)),) + convert $< $@ +endif hypertransport.pdf: hypertransport.svg +ifneq ($(strip $(SVG2PDF)),) svg2pdf $< $@ +else ifneq ($(strip $(INKSCAPE)),) + inkscape $< --export-pdf=$@ +else ifneq ($(strip $(CONVERT)),) + convert $< $@ +endif LinuxBIOS-AMD64.toc: $(FIGS) LinuxBIOS-AMD64.tex # 2 times to make sure we have a current toc. @@ -30,4 +45,3 @@ distclean: clean rm -f LinuxBIOS-AMD64.pdf -

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coreboot May 2009