coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

[v2] r4274 - in trunk/coreboot-v2/targets/tyan: s2891 s2892
by svn＠coreboot.org 12 May '09

12 May '09

Author: myles Date: 2009-05-12 16:14:54 +0200 (Tue, 12 May 2009) New Revision: 4274 Added: trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb Log: I guess a couple of function calls pushed these boards over the 0x1700 edge on the build server. Add Config-abuild.lb to fix s2892 & s2891. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/tyan/s2891/Config-abuild.lb 2009-05-12 14:14:54 UTC (rev 4274) @@ -0,0 +1,27 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ +__LOGLEVEL__ + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Added: trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/tyan/s2892/Config-abuild.lb 2009-05-12 14:14:54 UTC (rev 4274) @@ -0,0 +1,27 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ +__LOGLEVEL__ + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

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[flashrom] r497 - trunk
by svn＠coreboot.org 12 May '09

12 May '09

Author: uwe Date: 2009-05-12 16:06:04 +0200 (Tue, 12 May 2009) New Revision: 497 Removed: trunk/sst39sf020.c Modified: trunk/Makefile trunk/flashchips.c trunk/w49f002u.c Log: The write_39sf020() and write_49f002() functions are identical except for whitespace differences, so drop one of them. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-11 20:04:30 UTC (rev 496) +++ trunk/Makefile 2009-05-12 14:06:04 UTC (rev 497) @@ -30,7 +30,7 @@ LDFLAGS += -lpci -lz OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ - sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ + sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o \ w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-11 20:04:30 UTC (rev 496) +++ trunk/flashchips.c 2009-05-12 14:06:04 UTC (rev 497) @@ -1322,7 +1322,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1336,7 +1336,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1350,7 +1350,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1364,7 +1364,7 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1378,7 +1378,7 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1392,7 +1392,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1406,7 +1406,7 @@ .tested = TEST_OK_PROBE, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -1420,7 +1420,7 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -2134,7 +2134,7 @@ .tested = TEST_UNTESTED, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -2148,7 +2148,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -2176,7 +2176,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, @@ -2190,7 +2190,7 @@ .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, - .write = write_39sf020, + .write = write_49f002, .read = read_memmapped, }, Deleted: trunk/sst39sf020.c =================================================================== --- trunk/sst39sf020.c 2009-05-11 20:04:30 UTC (rev 496) +++ trunk/sst39sf020.c 2009-05-12 14:06:04 UTC (rev 497) @@ -1,46 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2000 Silicon Integrated System Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdio.h> -#include <stdint.h> -#include "flash.h" - -int write_39sf020(struct flashchip *flash, uint8_t *buf) -{ - int i; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; - volatile uint8_t *bios = flash->virtual_memory; - - erase_chip_jedec(flash); - - printf("Programming page: "); - for (i = 0; i < total_size / page_size; i++) { - /* write to the sector */ - printf("%04d at address: 0x%08x", i, i * page_size); - write_sector_jedec(bios, buf + i * page_size, - bios + i * page_size, page_size); - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - fflush(stdout); - } - printf("\n"); - - return 0; -} Modified: trunk/w49f002u.c =================================================================== --- trunk/w49f002u.c 2009-05-11 20:04:30 UTC (rev 496) +++ trunk/w49f002u.c 2009-05-12 14:06:04 UTC (rev 497) @@ -32,8 +32,8 @@ printf("Programming page: "); for (i = 0; i < total_size / page_size; i++) { - /* write to the sector */ printf("%04d at address: 0x%08x ", i, i * page_size); + /* Byte-wise writing of 'page_size' bytes. */ write_sector_jedec(bios, buf + i * page_size, bios + i * page_size, page_size); printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");

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build service results for r4271
by coreboot information 12 May '09

12 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4271 to the coreboot repository. This caused the following changes: Change Log: Use the debugging functions to print out the tree and resources. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4271&device=m2v-mx_se&vend… Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4271&device=s2891&vendor=t… Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4271&device=s2892&vendor=t… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4273 - trunk/coreboot-v2/targets/asus/m2v-mx_se
by svn＠coreboot.org 12 May '09

12 May '09

Author: myles Date: 2009-05-12 16:03:12 +0200 (Tue, 12 May 2009) New Revision: 4273 Added: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb Log: Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-05-12 14:03:12 UTC (rev 4273) @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target asus_m2v-mx_se +mainboard asus/m2v-mx_se + +## ROM_SIZE is the total number of bytes allocated for coreboot use +## (normal AND fallback images and payloads). + +# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary +# 384KB of flash is for payload/roms. + +option ROM_SIZE = 512 * 1024 + +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## not including any payload. + +# Please note that 128KB is cached for (XIP) too + +option ROM_IMAGE_SIZE = 128 * 1024 + +## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## (including payload) will use. + +option FALLBACK_SIZE = ROM_SIZE + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "fallback"

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[v2] r4272 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 12 May '09

12 May '09

Author: uwe Date: 2009-05-12 16:01:14 +0200 (Tue, 12 May 2009) New Revision: 4272 Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex Log: Fix pdflatex build issues (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex =================================================================== --- trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-05-12 13:43:34 UTC (rev 4271) +++ trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-05-12 14:01:14 UTC (rev 4272) @@ -1711,16 +1711,16 @@ \begin{quote} ./src/mainboard/iei/nova4899r/failover.c ./src/mainboard/emulation/qemu-x86/failover.c -./src/mainboard/supermicro/x6dhr_ig/failover.c -./src/mainboard/supermicro/x6dai_g/failover.c -./src/mainboard/supermicro/x6dhe_g2/failover.c -./src/mainboard/supermicro/x6dhr_ig2/failover.c -./src/mainboard/supermicro/x6dhe_g/failover.c +./src/mainboard/supermicro/x6dhr\_ig/failover.c +./src/mainboard/supermicro/x6dai\_g/failover.c +./src/mainboard/supermicro/x6dhe\_g2/failover.c +./src/mainboard/supermicro/x6dhr\_ig2/failover.c +./src/mainboard/supermicro/x6dhe\_g/failover.c ./src/mainboard/dell/s1850/failover.c ./src/mainboard/intel/xe7501devkit/failover.c ./src/mainboard/intel/jarrell/failover.c ./src/mainboard/olpc/btest/failover.c -./src/mainboard/olpc/rev_a/failover.c +./src/mainboard/olpc/rev\_a/failover.c ./src/mainboard/via/epia-m/failover.c \end{quote} Here is one of the more complicated ones:

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Board enable for Epox 8K5A2.
by Luc Verhaegen 12 May '09

12 May '09

I didn't prepend this with [PATCH] yet, as i still need to verify this change on an epia-m with its original bios... This patch adds support for the Epox 8k5a2 motherboard as owned by Kevin Sopp (CC). His lspci is attached for future reference. Kevin still needs to try this code too. His board is properly matched by pci subsystem ids, as there is one proper epox id in there, and the other id was copied from the device id (which is already better than leaving it blank). This motherboard requires just the MEMW# on the winbond superio to be raised for it to work. 2 more boards with vt823x need this as well. There are two other functions needed by other vt823x based boards; * raising a vt823x gpio line (used 2x). * enabling memory writes to always hit lpc on vt823x (used 2x). By putting this code into separate functions, the vt823x board enables become very simple, with only the msi on still needing to poke a single pci bit on its own. Luc Verhaegen.

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debugging usage
by Myles Watson 12 May '09

12 May '09

This patch is how I like to use the debugging functions I just committed. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4271 - in trunk/coreboot-v2/src: devices include/device
by svn＠coreboot.org 12 May '09

12 May '09

Author: myles Date: 2009-05-12 15:43:34 +0200 (Tue, 12 May 2009) New Revision: 4271 Modified: trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/include/device/device.h Log: Use the debugging functions to print out the tree and resources. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-05-11 22:45:35 UTC (rev 4270) +++ trunk/coreboot-v2/src/devices/device.c 2009-05-12 13:43:34 UTC (rev 4271) @@ -618,6 +618,12 @@ unsigned subordinate; printk_info("Enumerating buses...\n"); root = &dev_root; + + show_all_devs(BIOS_DEBUG, "Before Phase 3."); + printk_debug("Compare with tree...\n"); + + show_devs_tree(root, BIOS_DEBUG, 0, 0); + if (root->chip_ops && root->chip_ops->enable_dev) { root->chip_ops->enable_dev(root); } @@ -651,6 +657,9 @@ printk_info("Allocating resources...\n"); root = &dev_root; + + print_resource_tree(root, BIOS_DEBUG, "Original."); + if (!root->ops || !root->ops->read_resources) { printk_err("dev_root missing read_resources\n"); return; @@ -664,6 +673,8 @@ root->ops->read_resources(root); printk_info("Done reading resources.\n"); + print_resource_tree(root, BIOS_DEBUG, "After reading."); + /* Get the resources */ io = &root->resource[0]; mem = &root->resource[1]; @@ -681,6 +692,7 @@ #if CONFIG_CONSOLE_VGA == 1 /* Allocate the VGA I/O resource.. */ allocate_vga_resource(); + print_resource_tree(root, BIOS_DEBUG, "After VGA."); #endif /* Store the computed resource allocations into device registers ... */ @@ -691,6 +703,7 @@ mem->flags |= IORESOURCE_STORED; report_resource_stored(root, mem, ""); #endif + print_resource_tree(root, BIOS_DEBUG, "After assigning values."); printk_info("Done allocating resources.\n"); } @@ -737,5 +750,6 @@ } } printk_info("Devices initialized\n"); + show_all_devs(BIOS_DEBUG, "After init."); } Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-05-11 22:45:35 UTC (rev 4270) +++ trunk/coreboot-v2/src/include/device/device.h 2009-05-12 13:43:34 UTC (rev 4271) @@ -126,7 +126,6 @@ device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); /* Debug functions */ -void resource_tree(struct device * root, int debug_level, int depth); void print_resource_tree(struct device * root, int debug_level, const char *msg); void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum);

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[flashrom] emit a warning if first byte of flash is 0x02?
by Frieder Ferlemann 12 May '09

12 May '09

Hi, I don't know whether this proposal really makes sense but 8051 based Embedded Controlers are very likely to have 0x02 (the opcode for LJMP) at address 0x0000 and at some of its IRQ entry points at address 0x0003 + n*8 It might be worth warning about because erasing/writing the flash while the EC is running might not be a good idea. This posting was triggered by todays publication of: "Flash Programming for Dummies", A book by Carl-Daniel Hailfinger which specifically mentions interactions with embedded controlers. And a grep for "Embedded" "Controler" "EC" within the flashrom sources did not reveal a warning message. Greetings, Frieder

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changes to cbfstool to support more efficient rom walking
by ron minnich 12 May '09

12 May '09

I realized during the discussion that there is a fundamental improvement we can make to cbfstool. This change I am detailing is compatible with existing coreboot libraries. I describe it below and attach the patch. I have made a very simple mod to cbfstool that is compatible with the src/lib/ code in coreboot. I.e. the tool changes but the coreboot code does not. Currently, as cbfstool manages the ROM, there are files and empty space. To allocate files, the code does, first, a walk of the headers and, if that fails, does a brute-force search of the rest of the space. We all agree that the brute-force search is not a good idea. What I realized is that we should actually have 'empty space' as a cbfs file. This simple change greatly simplifies everything else. But how do we get a new file? Simple: we find an empty file and use it, splitting it if necessary. Result: all cbfs operations are now on headers, and nothing else. No walking of the ROM trying to find a header. So I've made a slight change. Instead of an "empty space" area with no valid headers, I've made a header for the empty space. Now creation of a new cbfs follows these steps: - set up the boot block - create a file, of type CBFS_COMPONENT_NULL, that contains the empty space. CBFS_COMPONENT_NULL was already defined in cbfs.h Here's an example: [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs create 1048576 2048 (cbfstool) E: Unable to open (null): Bad address [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size 0x0 0xffffffff 1046456 Note that the EMPTY area (type CBFS_COMPONENT_NULL) consumes the file area of the cbfs archive. So how do we create a new cbfs file in the archive? It's easy: walk the files and find a file of type CBFS_COMPONENT_NULL, which is as large or larger than the file you are trying to create. Then you use that cbfs file. - if the cbfs file is the same size as the NULL cbfs file, then it's easy: use it - if the cbfs file is smaller than the NULL file, you split the NULL cbfs file into two parts. note that this works in the base case: the base case is that the whole storage is CBFS_COMPONENT_NULL. Here's an example of adding a file. [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed t [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size t 0x0 stage 23176 0x5ab0 0xffffffff 1023240 Note that the NULL split and got smaller. But the entire ROM is still contained by the two files. To walk this entire rom will require two FLASH accesses -- no more. Add another file: [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed tt [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size t 0x0 stage 23176 tt 0x5ab0 stage 23176 0xb560 0xffffffff 1000024 [rminnich@xcpu2 cbfstool]$ So, taking current ROMs as an example, I can reduce FLASH accesses for cbfs from (potentially) thousands to (typically) less than 10. Note that I have changed deletion. To delete a file, we just burn the type to 0. This allows us to make a file unavailabe in FLASH without a block erase, and to put a new file of same name with, it is hoped, no block erase either. Comments welcome. This change should be tested by anyone who can give it a try. ron

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coreboot May 2009