coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

[PATCH] fix the XIP size and fallback computations for M2V-MX SE
by Rudolf Marek 12 May '09

12 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, It seems I'm quite tired to formulate the description of the patch accurately I hope it is understandable somehow. Following patch fixes the XIP computation issue. I removed the normal image because it was not working anyway (it was hardcoded) and because it allows me to fix the XIP base to something sane (and use generic computation and approach) This board is bit tricky because until now it required the VGA BIOS on the flash start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be aligned too to 64KB. Third reason is that now it makes 384KB for additional ROMs and payload - plenty of space for CBFS fun ;) Now it uses generic _ROMBASE etc computation which is nice too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkn8wQgACgkQ3J9wPJqZRNUftgCfXjuQUkJwksgI4VU81mdJ78Kh PyMAoMMWXjUKmq5YVQhsWZ6iFMEdgTSu =mtSc -----END PGP SIGNATURE-----

4 6

Failed flash, flashrom emergency help needed on ICH7
by Ali Nadalizadeh 12 May '09

12 May '09

I tried the latest svn version (6 May 09) of flashrom and unlike older versions didn't get a warning on my chipset. flashrom reads my chip successfully and outputs a fine Phoenix bios. After writing a new image into the chip I found that writer is not fully functional and reading the chip again results in an image that is neither original one nor the new image. then I tried erase functionality and it resulted in some 0xFF and some unchanged bytes in the chip. Currently writing either images doesn't change the chip and it remains in mostly 0xFF bytes. Here are the flashrom detection info : ali@Velocity:~/tmp/f$ sudo ./flashrom/flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. No operations were specified. verbose output at http://coreboot.pastebin.com/m604f01b6 history of my commands : http://coreboot.pastebin.com/m5c3c2372 Original Rom : http://filebin.ca/mhtqhm/mybios.rom lspci -vv output attached. I try to keep my Lenovo 3000 up and running and waiting for helps. :) I'm also online on #coreboot as nadalizadeh Thanks Ali Nadalizadeh

5 11

[PATCH] flashrom: Fix Elan SC520 handling
by Carl-Daniel Hailfinger 12 May '09

12 May '09

Fix Elan SC520 handling. flashbase is a variable which should never be set outside chipset code. It is only used to calculate the base address of the flash space at exactly one location in the code. Setting flashbase during probe caused subsequent probes to fail unless special handling code was used. We had such code and it caused every probe except the first to fail on Elan SC520. Remove the superfluous flashbase assignment and simplify the rest of the code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-flashbase/flashrom.c =================================================================== --- flashrom-flashbase/flashrom.c (Revision 486) +++ flashrom-flashbase/flashrom.c (Arbeitskopie) @@ -113,7 +113,7 @@ size = getpagesize(); } - base = flashbase && flashchips == first_flash ? flashbase : (0xffffffff - size + 1); + base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = bios = physmap("flash chip", base, size); if (force) @@ -135,7 +135,6 @@ printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n", flash->vendor, flash->name, flash->total_size, base); - flashbase = base; return flash; } -- http://www.hailfinger.org/ Index: flashrom-flashbase/flashrom.c =================================================================== --- flashrom-flashbase/flashrom.c (Revision 486) +++ flashrom-flashbase/flashrom.c (Arbeitskopie) @@ -113,7 +113,7 @@ size = getpagesize(); } - base = flashbase && flashchips == first_flash ? flashbase : (0xffffffff - size + 1); + base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = bios = physmap("flash chip", base, size); if (force) @@ -135,7 +135,6 @@ printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n", flash->vendor, flash->name, flash->total_size, base); - flashbase = base; return flash; }

3 3

build service results for r4270
by coreboot information 11 May '09

11 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4270 to the coreboot repository. This caused the following changes: Change Log: Bring v3-style debug output to v2. Fix a minor typo. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4270&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

msrtool and inteltool available in Debian
by Uwe Hermann 11 May '09

11 May '09

Hi, I'm happy to announce that my Debian packages of msrtool and inteltool are now available in Debian unstable: apt-get install msrtool inteltool See below for build logs, builds fail for some architectures. On some those tools don't make much sense I guess, but others could need some fixing. http://packages.qa.debian.org/m/msrtool.html https://buildd.debian.org/pkg.cgi?pkg=msrtool https://buildd.debian.org/~luk/status/package.php?p=msrtool http://buildd.debian-ports.org/status/package.php?p=msrtool (yes, msrtool builds fine on Hurd ;-) http://packages.qa.debian.org/i/inteltool.html https://buildd.debian.org/pkg.cgi?pkg=inteltool https://buildd.debian.org/~luk/status/package.php?p=inteltool http://buildd.debian-ports.org/status/package.php?p=inteltool Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

build service results for r4269
by coreboot information 11 May '09

11 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4269 to the coreboot repository. This caused the following changes: Change Log: This patch adds high table support to qemu. It was already added to src/northbridge/intel/i440bx/ but not to src/cpu/emulation/qemu-x86/northbridge.c It also adds a driver for the ISA device that is found when using 0.9.1 If you look in a log without this patch you won't find the RTC init lines. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4269&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

debugging helps
by Myles Watson 11 May '09

11 May '09

I like the debugging output from v3, so I brought it to v2. I also fixed a typo roung -> round. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[v2] r4270 - in trunk/coreboot-v2/src: devices include/device
by svn＠coreboot.org 11 May '09

11 May '09

Author: myles Date: 2009-05-12 00:45:35 +0200 (Tue, 12 May 2009) New Revision: 4270 Modified: trunk/coreboot-v2/src/devices/device_util.c trunk/coreboot-v2/src/include/device/device.h Log: Bring v3-style debug output to v2. Fix a minor typo. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/devices/device_util.c =================================================================== --- trunk/coreboot-v2/src/devices/device_util.c 2009-05-11 22:44:14 UTC (rev 4269) +++ trunk/coreboot-v2/src/devices/device_util.c 2009-05-11 22:45:35 UTC (rev 4270) @@ -554,3 +554,143 @@ dev_set_enabled(child, 0); } } + +void resource_tree(struct device *root, int debug_level, int depth) +{ + int i = 0, link = 0; + struct device *child; + char indent[30]; /* If your tree has more levels, it's wrong. */ + + for (i = 0; i < depth + 1 && i < 29; i++) + indent[i] = ' '; + indent[i] = '\0'; + + do_printk(BIOS_DEBUG, "%s%s links %x child on link 0 %s\n", + indent, dev_path(root), root->links, + root->link[0].children ? dev_path(root->link[0].children) : + "NULL"); + for (i = 0; i < root->resources; i++) { + do_printk(BIOS_DEBUG, + "%s%s resource base %llx size %llx align %d gran %d limit %llx flags %lx index %lx\n", + indent, dev_path(root), root->resource[i].base, + root->resource[i].size, root->resource[i].align, + root->resource[i].gran, root->resource[i].limit, + root->resource[i].flags, root->resource[i].index); + } + + for (link = 0; link < root->links; link++) { + for (child = root->link[link].children; child; + child = child->sibling) + resource_tree(child, debug_level, depth + 1); + } +} + +void print_resource_tree(struct device * root, int debug_level, + const char *msg) +{ + /* Bail if root is null. */ + if (!root) { + do_printk(debug_level, "%s passed NULL for root!\n", __func__); + return; + } + + /* Bail if not printing to screen. */ + if (!do_printk(debug_level, "Show resources in subtree (%s)...%s\n", + dev_path(root), msg)) + return; + resource_tree(root, debug_level, 0); +} + +void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum) +{ + char depth_str[20] = ""; + int i; + struct device *sibling; + for (i = 0; i < depth; i++) + depth_str[i] = ' '; + depth_str[i] = '\0'; + do_printk(debug_level, "%s%s: enabled %d, %d resources\n", + depth_str, dev_path(dev), dev->enabled, dev->resources); + for (i = 0; i < dev->links; i++) { + for (sibling = dev->link[i].children; sibling; + sibling = sibling->sibling) + show_devs_tree(sibling, debug_level, depth + 1, i); + } +} + +void show_all_devs_tree(int debug_level, const char *msg) +{ + /* Bail if not printing to screen. */ + if (!do_printk(debug_level, "Show all devs in tree form...%s\n", msg)) + return; + show_devs_tree(all_devices, debug_level, 0, -1); +} + +void show_devs_subtree(struct device *root, int debug_level, const char *msg) +{ + /* Bail if not printing to screen. */ + if (!do_printk(debug_level, "Show all devs in subtree %s...%s\n", + dev_path(root), msg)) + return; + do_printk(debug_level, "%s\n", msg); + show_devs_tree(root, debug_level, 0, -1); +} + +void show_all_devs(int debug_level, const char *msg) +{ + struct device *dev; + + /* Bail if not printing to screen. */ + if (!do_printk(debug_level, "Show all devs...%s\n", msg)) + return; + for (dev = all_devices; dev; dev = dev->next) { + do_printk(debug_level, + "%s: enabled %d, %d resources\n", + dev_path(dev), dev->enabled, + dev->resources); + } +} + +void show_one_resource(int debug_level, struct device *dev, + struct resource *resource, const char *comment) +{ + char buf[10]; + unsigned long long base, end; + base = resource->base; + end = resource_end(resource); + buf[0] = '\0'; +/* + if (resource->flags & IORESOURCE_BRIDGE) { +#if PCI_BUS_SEGN_BITS + sprintf(buf, "bus %04x:%02x ", dev->bus->secondary >> 8, + dev->link[0].secondary & 0xff); +#else + sprintf(buf, "bus %02x ", dev->link[0].secondary); +#endif + } +*/ + do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] " + "size 0x%08Lx gran 0x%02x %s%s%s\n", + dev_path(dev), resource->index, base, end, + resource->size, resource->gran, buf, + resource_type(resource), comment); + +} + +void show_all_devs_resources(int debug_level, const char* msg) +{ + struct device *dev; + + if(!do_printk(debug_level, "Show all devs with resources...%s\n", msg)) + return; + + for (dev = all_devices; dev; dev = dev->next) { + int i; + do_printk(debug_level, + "%s: enabled %d, %d resources\n", + dev_path(dev), dev->enabled, + dev->resources); + for (i = 0; i < dev->resources; i++) + show_one_resource(debug_level, dev, &dev->resource[i], ""); + } +} Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-05-11 22:44:14 UTC (rev 4269) +++ trunk/coreboot-v2/src/include/device/device.h 2009-05-11 22:45:35 UTC (rev 4270) @@ -125,9 +125,19 @@ device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); +/* Debug functions */ +void resource_tree(struct device * root, int debug_level, int depth); +void print_resource_tree(struct device * root, int debug_level, + const char *msg); +void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); +void show_devs_subtree(struct device *root, int debug_level, const char *msg); +void show_all_devs(int debug_level, const char *msg); +void show_one_resource(int debug_level, struct device *dev, + struct resource *resource, const char *comment); +void show_all_devs_resources(int debug_level, const char* msg); /* Rounding for boundaries. - * Due to some chip bugs, go ahead and roung IO to 16 + * Due to some chip bugs, go ahead and round IO to 16 */ #define DEVICE_IO_ALIGN 16 #define DEVICE_MEM_ALIGN 4096

1 0

build service results for r4268
by coreboot information 11 May '09

11 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4268 to the coreboot repository. This caused the following changes: Change Log: Trivial white space fixes so that the next patches are easier to read. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4268&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Qemu fixes
by Myles Watson 11 May '09

11 May '09

This patch adds high table support to qemu. It was already added to src/northbridge/intel/i440bx/ but not to src/cpu/emulation/qemu-x86/northbridge.c It also adds a driver for the ISA device that is found when using 0.9.1 If you look in a log without this patch you won't find the RTC init lines. The (un)fortunate thing is that it works (boots) either way. Maybe this will fix some PIRQ problems that were really because the table was being overwritten by SeaBIOS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

← Newer
1
...
38
39
40
41
42
43
44
...
58
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2009