coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

[v2] r4267 - trunk/coreboot-v2/src/superio/ite/it8718f
by svn＠coreboot.org 11 May '09

11 May '09

Author: uwe Date: 2009-05-11 15:45:11 +0200 (Mon, 11 May 2009) New Revision: 4267 Modified: trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c Log: We should separate the it8718f_24mhz_clkin like the way IT8712 does. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by; Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c 2009-05-11 01:44:54 UTC (rev 4266) +++ trunk/coreboot-v2/src/superio/ite/it8718f/it8718f_early_serial.c 2009-05-11 13:45:11 UTC (rev 4267) @@ -45,10 +45,9 @@ outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8718F Super I/O chip. */ -static void it8718f_enable_serial(device_t dev, unsigned iobase) +static void it8718f_enter_conf(void) { - /* (1) Enter the configuration state (MB PnP mode). */ + /* Enter the configuration state (MB PnP mode). */ /* Perform MB PnP setup to put the SIO chip at 0x2e. */ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ @@ -57,7 +56,30 @@ outb(0x01, IT8718F_CONFIGURATION_PORT); outb(0x55, IT8718F_CONFIGURATION_PORT); outb(0x55, IT8718F_CONFIGURATION_PORT); +} +static void it8718f_exit_conf(void) +{ + /* Exit the configuration state (MB PnP mode). */ + it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); +} + +static void it8718f_24mhz_clkin(void) +{ + it8718f_enter_conf(); + + /* Select 24MHz CLKIN (48MHZ default)*/ + it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); + + it8718f_exit_conf(); +} + +/* Enable the peripheral devices on the IT8718F Super I/O chip. */ +static void it8718f_enable_serial(device_t dev, unsigned iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8718f_enter_conf(); + /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). @@ -65,17 +87,14 @@ If this register is not written, both chips are configured. */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ - /* Enable all devices. */ + /* Enable serial port(s). */ it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ - /* Select 24MHz CLKIN (set bit 0). */ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01); - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ /* (3) Exit the configuration state (MB PnP mode). */ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); + it8718f_exit_conf(); }

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build service results for r4266
by coreboot information 10 May '09

10 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4266 to the coreboot repository. This caused the following changes: Change Log: Fix manual build on the Kontron board (trivial). A manual build was yielding section overlaps, so increase ROM_IMAGE_SIZE to the same size the Config-abuild.lb is using. Build-tested by me using a manual build. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Configuration of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4266&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4266 - trunk/coreboot-v2/targets/kontron/986lcd-m
by svn＠coreboot.org 10 May '09

10 May '09

Author: uwe Date: 2009-05-11 03:44:54 +0200 (Mon, 11 May 2009) New Revision: 4266 Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb Log: Fix manual build on the Kontron board (trivial). A manual build was yielding section overlaps, so increase ROM_IMAGE_SIZE to the same size the Config-abuild.lb is using. Build-tested by me using a manual build. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-05-10 20:35:18 UTC (rev 4265) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-05-11 01:44:54 UTC (rev 4266) @@ -17,7 +17,8 @@ option FALLBACK_SIZE = ROM_SIZE romimage "fallback" - option USE_FALLBACK_IMAGE=1 + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 144 * 1024 payload ../payload.elf end

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Re: [coreboot] [flashrom] r486 - trunk
by Carl-Daniel Hailfinger 10 May '09

10 May '09

On 09.05.2009 04:34, svn(a)coreboot.org wrote: > Author: hailfinger > New Revision: 486 > > Log: > Convert all flashchips.c entries with SPI programing to the 256-byte > version by default. > > Change the flashchips entry for SST SST25VF080B to 1-byte writing. > A big THANK YOU goes to Peter Stuge for investing many hours and sacrificing his sleep to debug this. He had lots of cool ideas and patience which allowed us to track down the associated bug from a random nonsense write pattern to a single non-obvious line in the data sheet. Regards, Carl-Daniel

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How to flash my bios on Sony Vaio VGN FZ21M Laptop
by ahmet alper parker 10 May '09

10 May '09

Hi all, I want to replace my crappy bios with the coreboot. I looked at the site and it states that my chipset is ok. Here is the flashrom output on fedora 10. ----------------------------- flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH8M", enabling flash write... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ----------------------------- I have a Sony Vaio Laptop Vgn-Fz21m. But I don't know what is it's chip. What should I do? Any comment is wellcomed. Best Regards AAP

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[v2] r4265 - in trunk/coreboot-v2: src/mainboard/asus/m2v-mx_se targets/asus/m2v-mx_se
by svn＠coreboot.org 10 May '09

10 May '09

Author: ruik Date: 2009-05-10 22:35:18 +0200 (Sun, 10 May 2009) New Revision: 4265 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb Log: Following patch fixes the XIP computation issue. I removed the normal image because it was not working anyway (it was hardcoded) and because it allows me to fix the XIP base to something sane (and use generic computation and approach) This board is bit tricky because until now it required the VGA BIOS on the flash start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be aligned too to 64KB. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-05-09 17:14:58 UTC (rev 4264) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-05-10 20:35:18 UTC (rev 4265) @@ -20,24 +20,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end +include /config/nofailovercalculation128.lb -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default CONFIG_ROM_PAYLOAD = 1 -default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) - -##WARNING enable caching of whole ROM during CAR -##for 512KB flash -default XIP_ROM_SIZE = 0x80000 -default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE - arch i386 end driver mainboard.o Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-05-09 17:14:58 UTC (rev 4264) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-05-10 20:35:18 UTC (rev 4265) @@ -96,8 +96,6 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_USE_PRINTK_IN_CAR -default ROM_SIZE = 512 * 1024 -default FALLBACK_SIZE = 256 * 1024 default HAVE_FALLBACK_BOOT = 1 default HAVE_HARD_RESET = 1 default HAVE_PIRQ_TABLE = 0 @@ -153,7 +151,6 @@ default MAINBOARD_PART_NUMBER = "M2V-MX SE" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 # default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default ROM_IMAGE_SIZE = 64 * 1024 default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-05-09 17:14:58 UTC (rev 4264) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-05-10 20:35:18 UTC (rev 4265) @@ -162,64 +162,10 @@ } -#if USE_FALLBACK_IMAGE == 1 - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* unsigned last_boot_normal_x = last_boot_normal(); */ - /* FIXME */ - unsigned last_boot_normal_x = 1; - - sio_init(); - it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); - it8712f_kill_watchdog(); - uart_init(); - console_init(); - enable_rom_decode(); - - print_info("now booting... fallback\r\n"); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU, how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - /* print_info("JMP normal image\r\n"); */ - - __asm__ __volatile__("jmp __normal_image": - :"a" (bist), "b" (cpu_init_detectedx)); - -fallback_image: - ; -} -#endif - void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif real_main(bist, cpu_init_detectedx); } Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-05-09 17:14:58 UTC (rev 4264) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-05-10 20:35:18 UTC (rev 4265) @@ -20,19 +20,35 @@ target asus_m2v-mx_se mainboard asus/m2v-mx_se -romimage "normal" - option ROM_SIZE = 512 * 1024 - option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 128 * 1024 - option COREBOOT_EXTRA_VERSION=".0Normal" - payload ../payload.elf -end +## ROM_SIZE is the total number of bytes allocated for coreboot use +## (normal AND fallback images and payloads). +# The board comes with 512KB SPI flash (DIP8), 128KB is for coreboot binary +# 384KB of flash is for payload/roms. + +option ROM_SIZE = 512 * 1024 + +# Use following line instead if you want to use onboard VGA - +# padd the rom size to 64KB or XIP won't work, complaining about +# not good base. + +#option ROM_SIZE = (512 * 1024) - (64 * 1024) + +## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, +## not including any payload. + +# Please note that 128KB is cached for (XIP) too + +option ROM_IMAGE_SIZE = 128 * 1024 + +## FALLBACK_SIZE is the amount of the ROM the complete fallback image +## (including payload) will use. + +option FALLBACK_SIZE = ROM_SIZE + romimage "fallback" - option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 128 * 1024 - option COREBOOT_EXTRA_VERSION=".0Fallback" + option USE_FALLBACK_IMAGE=1 payload ../payload.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom ROM_SIZE "fallback"

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Local server for Coreboot
by Gregg C Levine 10 May '09

10 May '09

Hello! Any issues with my setting up a local server for my Coreboot trees? Of course this does presuppose a problem. I am familiar with doing so via the now discontinued CVS methods, but what about doing so via SVN? I would imagine that I've got the complete documentation here, but I am looking for advice on this subject as it happens. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

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[PATCH] flashrom: SB600 SPI detection heuristic
by Carl-Daniel Hailfinger 10 May '09

10 May '09

Create a SB600 SPI detection heuristic. I know that the data sheets say we can't read the ROM straps, but creative interpretation of the data sheets yielded a heuristic which should work pretty well. NOTE: If you test this, make sure you power down and _unplug_ the machine for a few minutes before you boot and run flashrom with this patch. If the machine is not unplugged for some time, the test will yield incorrect results. If you run a slightly older flashrom version than svn HEAD, the test will yield incorrect results. If you run any flashrom version (except svn HEAD plus this patch) after poweron, the test will yield incorrect results. Explanation: Older flashrom versions unconditionally stomp on registers which are used for this heuristic. These registers are in the S5 power domain, so even powering down does not clear them, you really have to unplug the machine. Please run flashrom --verbose once and post the output to this list. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sb600/chipset_enable.c =================================================================== --- flashrom-sb600/chipset_enable.c (Revision 464) +++ flashrom-sb600/chipset_enable.c (Arbeitskopie) @@ -660,6 +660,8 @@ { uint32_t tmp, prot; uint8_t reg; + struct pci_dev *smbus_dev; + int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -688,13 +690,48 @@ tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + has_spi = 0; + /* Physical memory can only be mapped at page (4k) boundaries */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); /* The low bits of the SPI base address are used as offset into the mapped page */ sb600_spibar += tmp & 0xfff; - flashbus = BUS_TYPE_SB600_SPI; + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + if (!smbus_dev) { + fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + has_spi = 0; + } else { + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) + has_spi = 0; + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + if (reg != 0x00) + has_spi = 0; + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) + has_spi = 0; + } + + if (has_spi) + flashbus = BUS_TYPE_SB600_SPI; + /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have -- http://www.hailfinger.org/ Index: flashrom-sb600/chipset_enable.c =================================================================== --- flashrom-sb600/chipset_enable.c (Revision 464) +++ flashrom-sb600/chipset_enable.c (Arbeitskopie) @@ -660,6 +660,8 @@ { uint32_t tmp, prot; uint8_t reg; + struct pci_dev *smbus_dev; + int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -688,13 +690,48 @@ tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + has_spi = 0; + /* Physical memory can only be mapped at page (4k) boundaries */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); /* The low bits of the SPI base address are used as offset into the mapped page */ sb600_spibar += tmp & 0xfff; - flashbus = BUS_TYPE_SB600_SPI; + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + if (!smbus_dev) { + fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + has_spi = 0; + } else { + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) + has_spi = 0; + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + if (reg != 0x00) + has_spi = 0; + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) + has_spi = 0; + } + + if (has_spi) + flashbus = BUS_TYPE_SB600_SPI; + /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have

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[flashrom] r491 - trunk
by svn＠coreboot.org 10 May '09

10 May '09

Author: hailfinger Date: 2009-05-10 16:11:07 +0200 (Sun, 10 May 2009) New Revision: 491 Modified: trunk/chipset_enable.c Log: Create a SB600 SPI detection heuristic. I know that the data sheets say we can't read the ROM straps, but creative interpretation of the data sheets yielded a heuristic which should work pretty well. NOTE: If you test this, make sure you power down and _unplug_ the machine for a few minutes before you boot and run flashrom with this patch. If the machine is not unplugged for some time, the test will yield incorrect results. If you run a slightly older flashrom version than svn HEAD, the test will yield incorrect results. If you run any flashrom version (except svn HEAD plus this patch) after poweron, the test will yield incorrect results. Explanation: Older flashrom versions unconditionally write to registers which are used for this heuristic. These registers are in the S5 power domain, so even powering down does not clear them, you really have to unplug the machine and remove the battery if this is a laptop. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-09 14:26:04 UTC (rev 490) +++ trunk/chipset_enable.c 2009-05-10 14:11:07 UTC (rev 491) @@ -660,6 +660,8 @@ { uint32_t tmp, prot; uint8_t reg; + struct pci_dev *smbus_dev; + int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -688,13 +690,48 @@ tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ printf_debug("SPI base address is at 0x%x\n", tmp); + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + has_spi = 0; + /* Physical memory can only be mapped at page (4k) boundaries */ sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); /* The low bits of the SPI base address are used as offset into the mapped page */ sb600_spibar += tmp & 0xfff; - flashbus = BUS_TYPE_SB600_SPI; + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + if (!smbus_dev) { + fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); + has_spi = 0; + } else { + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) + has_spi = 0; + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + if (reg != 0x00) + has_spi = 0; + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) + has_spi = 0; + } + + if (has_spi) + flashbus = BUS_TYPE_SB600_SPI; + /* Force enable SPI ROM in SB600 PM register. * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have

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[PATCH] Revert "This is an emergency fix for building for qemu. "
by Mart Raudsepp 09 May '09

09 May '09

Revert "This is an emergency fix for building for qemu. " This reverts r1162 because r1161 was a better and more universal fix. Signed-off-by: Mart Raudsepp <leio(a)gentoo.org> --- northbridge/intel/i440bxemulation/i440bx.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/northbridge/intel/i440bxemulation/i440bx.c b/northbridge/intel/i440bxemulation/i440bx.c index 345faf4..34eb4fa 100644 --- a/northbridge/intel/i440bxemulation/i440bx.c +++ b/northbridge/intel/i440bxemulation/i440bx.c @@ -60,11 +60,6 @@ static void no_op(struct device *dev) { } -int is_coldboot(void) -{ - return 1; -} - static void i440bx_read_resources(struct device *dev) { struct resource *res; -- 1.6.1.3

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coreboot May 2009