coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

[PATCH] flashrom: Fix compilation of nic3com on 64bit
by Carl-Daniel Hailfinger 14 May '09

14 May '09

Fix compilation of nic3com on 64bit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-nic3com_compilefix/flash.h =================================================================== --- flashrom-nic3com_compilefix/flash.h (Revision 511) +++ flashrom-nic3com_compilefix/flash.h (Arbeitskopie) @@ -585,6 +585,7 @@ void physunmap(void *virt_addr, size_t len); /* internal.c */ +void get_io_perms(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, volatile void *addr); Index: flashrom-nic3com_compilefix/nic3com.c =================================================================== --- flashrom-nic3com_compilefix/nic3com.c (Revision 511) +++ flashrom-nic3com_compilefix/nic3com.c (Arbeitskopie) @@ -158,7 +158,7 @@ void nic3com_chip_writeb(uint8_t val, volatile void *addr) { - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } @@ -174,7 +174,7 @@ { uint8_t val; - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); val = INB(io_base_addr + BIOS_ROM_DATA); return val; Index: flashrom-nic3com_compilefix/internal.c =================================================================== --- flashrom-nic3com_compilefix/internal.c (Revision 511) +++ flashrom-nic3com_compilefix/internal.c (Arbeitskopie) @@ -83,7 +83,7 @@ return NULL; } -void get_io_perms(void) +void get_io_perms() { #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { @@ -102,7 +102,7 @@ { int ret = 0; - get_io_perms(void); + get_io_perms(); /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ -- http://www.hailfinger.org/ Index: flashrom-nic3com_compilefix/flash.h =================================================================== --- flashrom-nic3com_compilefix/flash.h (Revision 511) +++ flashrom-nic3com_compilefix/flash.h (Arbeitskopie) @@ -585,6 +585,7 @@ void physunmap(void *virt_addr, size_t len); /* internal.c */ +void get_io_perms(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, volatile void *addr); Index: flashrom-nic3com_compilefix/nic3com.c =================================================================== --- flashrom-nic3com_compilefix/nic3com.c (Revision 511) +++ flashrom-nic3com_compilefix/nic3com.c (Arbeitskopie) @@ -158,7 +158,7 @@ void nic3com_chip_writeb(uint8_t val, volatile void *addr) { - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } @@ -174,7 +174,7 @@ { uint8_t val; - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); val = INB(io_base_addr + BIOS_ROM_DATA); return val; Index: flashrom-nic3com_compilefix/internal.c =================================================================== --- flashrom-nic3com_compilefix/internal.c (Revision 511) +++ flashrom-nic3com_compilefix/internal.c (Arbeitskopie) @@ -83,7 +83,7 @@ return NULL; } -void get_io_perms(void) +void get_io_perms() { #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { @@ -102,7 +102,7 @@ { int ret = 0; - get_io_perms(void); + get_io_perms(); /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */

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[flashrom] r512 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: hailfinger Date: 2009-05-14 23:41:10 +0200 (Thu, 14 May 2009) New Revision: 512 Modified: trunk/flash.h trunk/internal.c trunk/nic3com.c Log: Fix compilation of nic3com on 64bit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-14 20:41:57 UTC (rev 511) +++ trunk/flash.h 2009-05-14 21:41:10 UTC (rev 512) @@ -585,6 +585,7 @@ void physunmap(void *virt_addr, size_t len); /* internal.c */ +void get_io_perms(void); int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, volatile void *addr); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-05-14 20:41:57 UTC (rev 511) +++ trunk/internal.c 2009-05-14 21:41:10 UTC (rev 512) @@ -102,7 +102,7 @@ { int ret = 0; - get_io_perms(void); + get_io_perms(); /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-14 20:41:57 UTC (rev 511) +++ trunk/nic3com.c 2009-05-14 21:41:10 UTC (rev 512) @@ -158,7 +158,7 @@ void nic3com_chip_writeb(uint8_t val, volatile void *addr) { - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); OUTB(val, io_base_addr + BIOS_ROM_DATA); } @@ -174,7 +174,7 @@ { uint8_t val; - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTL((uint32_t)(intptr_t)addr, io_base_addr + BIOS_ROM_ADDR); val = INB(io_base_addr + BIOS_ROM_DATA); return val;

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serengeti_cheetah_fam10 Max CPU and Max Physical CPU
by Lim, Vincent 14 May '09

14 May '09

Hi All: >From AMD Family 10h Processor BKDG (Rev D): a platform is capable of having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores. Thus I am proposing to update the Options.lb as below: Index: src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- src/mainboard/amd/serengeti_cheetah_fam10/Options.lb (revision 4267) +++ src/mainboard/amd/serengeti_cheetah_fam10/Options.lb (working copy) @@ -184,11 +187,10 @@ ## ## Build code for SMP support -## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS +default CONFIG_MAX_PHYSICAL_CPUS=8 +default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 I need this for my Simulation platform to POST as many core as possible. With this setup, I did quick test on POSTing lower count nodes, i.e.: 1 node and 2 nodes platform OK. Signed-off-by: Vincent Lim <vincent.lim(a)amd.com> Best Regards, Vincent Lim SimNow Team Performance CoE Central Engineering T 512.602.1618 F 512.602.7745

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Multiboot table help
by Myles Watson 14 May '09

14 May '09

Robert, Is there anything specific that I need to know with respect to where the Multiboot table ends up? If you could give me memory ranges that are acceptable, that would be great. Should it be in the high tables area as well? Thanks, Myles

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[v2] r4285 - trunk/coreboot-v2/src/boot
by svn＠coreboot.org 14 May '09

14 May '09

Author: rminnich Date: 2009-05-14 23:26:28 +0200 (Thu, 14 May 2009) New Revision: 4285 Modified: trunk/coreboot-v2/src/boot/selfboot.c Log: #136: failed to boot under KVM\QEMU > -------------------------------------+-------------------------------------- > Reporter: silicium@?\226?\128?\166 | Owner: somebody > Type: defect | Status: new > Priority: major | Milestone: > Component: coreboot | Version: v2 > Keywords: | Dependencies: > Patchstatus: patch needs review | > -------------------------------------+-------------------------------------- Fix use of uninitialized pointers. To help in future, move the declaration to the same scope as the use. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/boot/selfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/selfboot.c 2009-05-14 03:00:15 UTC (rev 4284) +++ trunk/coreboot-v2/src/boot/selfboot.c 2009-05-14 21:26:28 UTC (rev 4285) @@ -411,7 +411,7 @@ return 0; } for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *middle, *end, *src; + unsigned char *dest,*src; printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -428,6 +428,7 @@ /* Copy data from the initial buffer */ if (ptr->s_filesz) { + unsigned char *middle, *end; size_t len; len = ptr->s_filesz; switch(ptr->compression) { @@ -464,14 +465,15 @@ (unsigned long)middle, (unsigned long)end, (unsigned long)src); - } - /* Zero the extra bytes between middle & end */ - if (middle < end) { - printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", - (unsigned long)middle, (unsigned long)(end - middle)); + + /* Zero the extra bytes between middle & end */ + if (middle < end) { + printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", + (unsigned long)middle, (unsigned long)(end - middle)); - /* Zero the extra bytes */ - memset(middle, 0, end - middle); + /* Zero the extra bytes */ + memset(middle, 0, end - middle); + } } } return 1;

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[flashrom] r511 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: uwe Date: 2009-05-14 22:41:57 +0200 (Thu, 14 May 2009) New Revision: 511 Modified: trunk/flash.h trunk/internal.c trunk/nic3com.c Log: Factor out portable iopl()-style code into a global function which all programmers can use, add missing close() call (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-14 18:57:26 UTC (rev 510) +++ trunk/flash.h 2009-05-14 20:41:57 UTC (rev 511) @@ -593,6 +593,9 @@ uint8_t internal_chip_readb(const volatile void *addr); uint16_t internal_chip_readw(const volatile void *addr); uint32_t internal_chip_readl(const volatile void *addr); +#if defined(__FreeBSD__) || defined(__DragonFly__) +extern int io_fd; +#endif /* dummyflasher.c */ int dummy_init(void); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-05-14 18:57:26 UTC (rev 510) +++ trunk/internal.c 2009-05-14 20:41:57 UTC (rev 511) @@ -83,11 +83,8 @@ return NULL; } -int internal_init(void) +void get_io_perms(void) { - int ret = 0; - - /* First get full io access */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { #elif defined(__FreeBSD__) || defined (__DragonFly__) @@ -95,10 +92,18 @@ #else if (iopl(3) != 0) { #endif - fprintf(stderr, "ERROR: Could not get IO privileges (%s).\nYou need to be root.\n", strerror(errno)); + fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n" + "You need to be root.\n", strerror(errno)); exit(1); } +} +int internal_init(void) +{ + int ret = 0; + + get_io_perms(void); + /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ /* Set all options you want -- here we stick with the defaults */ Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-14 18:57:26 UTC (rev 510) +++ trunk/nic3com.c 2009-05-14 20:41:57 UTC (rev 511) @@ -39,10 +39,6 @@ struct pci_access *pacc; struct pci_filter filter; -#if defined(__FreeBSD__) || defined(__DragonFly__) -int io_fd; -#endif - #define OK 0 #define NT 1 /* Not tested */ @@ -102,17 +98,7 @@ struct pci_dev *dev; char *msg = NULL; -#if defined (__sun) && (defined(__i386) || defined(__amd64)) - if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { -#elif defined(__FreeBSD__) || defined (__DragonFly__) - if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#else - if (iopl(3) != 0) { -#endif - fprintf(stderr, "ERROR: Could not get IO privileges (%s).\n" - "You need to be root.\n", strerror(errno)); - exit(1); - } + get_io_perms(); pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ @@ -155,6 +141,9 @@ { free(nic_pcidev); pci_cleanup(pacc); +#if defined(__FreeBSD__) || defined(__DragonFly__) + close(io_fd); +#endif return 0; }

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[flashrom] nic3com: support for user specified NIC via id
by Christian Ruppert 14 May '09

14 May '09

Hey, here is the first official patch to support a user specified NIC via pci id (bus:slot:func). example: flashrom -p nic3com=xx:xx.x Signed-off-by: Christian Ruppert <spooky85(a)gmail.com> Regards, Christian Ruppert

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[flashrom] r510 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: uwe Date: 2009-05-14 20:57:26 +0200 (Thu, 14 May 2009) New Revision: 510 Modified: trunk/flash.h trunk/flashrom.c trunk/internal.c trunk/nic3com.c Log: 3COM: Add support for users to specify a certain NIC via PCI bus:slot.func notation, in case there are multiple NICs in one system. Usage: flashrom -p nic3com=bb:ss.f Signed-off-by: Christian Ruppert <spooky85(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-14 14:51:14 UTC (rev 509) +++ trunk/flash.h 2009-05-14 18:57:26 UTC (rev 510) @@ -29,6 +29,7 @@ #include <unistd.h> #include <stdint.h> #include <stdio.h> +#include <pci/pci.h> /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) @@ -545,6 +546,7 @@ /* PCI handling for board/chipset_enable */ struct pci_access *pacc; +struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); @@ -623,6 +625,7 @@ #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf); +extern char *nic_pcidev; /* layout.c */ int show_id(uint8_t *bios, int size, int force); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-14 14:51:14 UTC (rev 509) +++ trunk/flashrom.c 2009-05-14 18:57:26 UTC (rev 510) @@ -35,6 +35,7 @@ int exclude_start_page, exclude_end_page; int verbose = 0; int programmer = PROGRAMMER_INTERNAL; +char *nic_pcidev = NULL; const struct programmer_entry programmer_table[] = { { @@ -454,6 +455,8 @@ programmer = PROGRAMMER_DUMMY; } else if (strncmp(optarg, "nic3com", 7) == 0) { programmer = PROGRAMMER_NIC3COM; + if (optarg[7] == '=') + nic_pcidev = strdup(optarg + 8); } else { printf("Error: Unknown programmer.\n"); exit(1); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-05-14 14:51:14 UTC (rev 509) +++ trunk/internal.c 2009-05-14 18:57:26 UTC (rev 510) @@ -34,6 +34,17 @@ struct pci_access *pacc; /* For board and chipset_enable */ +struct pci_dev *pci_dev_find_filter(struct pci_filter filter) +{ + struct pci_dev *temp; + + for (temp = pacc->devices; temp; temp = temp->next) + if (pci_filter_match(&filter, temp)) + return temp; + + return NULL; +} + struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) { struct pci_dev *temp; Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-14 14:51:14 UTC (rev 509) +++ trunk/nic3com.c 2009-05-14 18:57:26 UTC (rev 510) @@ -24,7 +24,6 @@ #include <sys/types.h> #include <sys/stat.h> #include <errno.h> -#include <pci/pci.h> #include "flash.h" #define BIOS_ROM_ADDR 0x04 @@ -38,6 +37,7 @@ uint32_t io_base_addr; struct pci_access *pacc; +struct pci_filter filter; #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; @@ -69,10 +69,38 @@ {}, }; +uint32_t nic3com_validate(struct pci_dev *dev) +{ + int i = 0; + uint32_t addr = -1; + + for (i = 0; nics[i].device_name != NULL; i++) { + if (dev->device_id != nics[i].device_id) + continue; + + addr = pci_read_long(dev, PCI_IO_BASE_ADDRESS) & ~0x03; + + printf("Found NIC \"3COM %s\" (%04x:%04x), addr = 0x%x\n", + nics[i].device_name, PCI_VENDOR_ID_3COM, + nics[i].device_id, addr); + + if (nics[i].status == NT) { + printf("===\nThis NIC is UNTESTED. Please email a " + "report including the 'flashrom -p nic3com'\n" + "output to flashrom(a)coreboot.org if it works " + "for you. Thank you for your help!\n===\n"); + } + + return addr; + } + + return addr; +} + int nic3com_init(void) { - int i, found = 0; struct pci_dev *dev; + char *msg = NULL; #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { @@ -90,29 +118,25 @@ pci_init(pacc); /* Initialize the PCI library */ pci_scan_bus(pacc); /* We want to get the list of devices */ - for (i = 0; nics[i].device_name != NULL; i++) { - dev = pci_dev_find(PCI_VENDOR_ID_3COM, nics[i].device_id); - if (!dev) - continue; - - io_base_addr = pci_read_long(dev, PCI_IO_BASE_ADDRESS) & ~0x03; - - printf("Found NIC \"3COM %s\" (%04x:%04x), addr = 0x%x\n", - nics[i].device_name, PCI_VENDOR_ID_3COM, - nics[i].device_id, io_base_addr); - - if (nics[i].status == NT) { - printf("===\nThis NIC is UNTESTED. Please email a " - "report including the 'flashrom -p nic3com'\n" - "output to flashrom(a)coreboot.org if it works " - "for you. Thank you for your help!\n===\n"); + if (nic_pcidev != NULL) { + pci_filter_init(pacc, &filter); + + if ((msg = pci_filter_parse_slot(&filter, nic_pcidev))) { + fprintf(stderr, "Error: %s\n", msg); + exit(1); } + } - found = 1; - break; + if (!filter.vendor && !filter.device) { + pci_filter_init(pacc, &filter); + filter.vendor = PCI_VENDOR_ID_3COM; } - if (!found) { + dev = pci_dev_find_filter(filter); + + if (dev && (dev->vendor_id == PCI_VENDOR_ID_3COM)) + io_base_addr = nic3com_validate(dev); + else { fprintf(stderr, "Error: No supported 3COM NIC found.\n"); exit(1); } @@ -129,6 +153,8 @@ int nic3com_shutdown(void) { + free(nic_pcidev); + pci_cleanup(pacc); return 0; }

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build service results for r4278
by coreboot information 14 May '09

14 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "linux_junkie" checked in revision 4278 to the coreboot repository. This caused the following changes: Change Log: Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4278&device=mew-am&vendor=… If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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SGABIOS checksum [kevin@koconnor.net: Re: SeaBIOS, serial output, and grub]
by Peter Stuge 14 May '09

14 May '09

Hi Nathan, there was some discussion on the coreboot mailing list, and it seems that the SGABIOS binary doesn't have a checksum calculated for it, which means that some BIOSes refuse to initialize it. The SeaBIOS project maintained by Kevin has a utility for calculating checksums, available at: http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=tools/checksum.py;h=… Kevin, I can't find that buildrom.py script in seabios.git? //Peter ----- Forwarded message from Kevin O'Connor <kevin(a)koconnor.net> ----- From: Kevin O'Connor <kevin(a)koconnor.net> To: coreboot(a)coreboot.org Subject: Re: [coreboot] SeaBIOS, serial output, and grub Date: Thu, 14 May 2009 09:19:33 -0400 On Wed, May 13, 2009 at 11:23:52PM -0400, Ward Vandewege wrote: > > which is correct (the last two digits are 00). > > Huh: > > $ v ../payloads/sgabios.bin > -rwxr-xr-x 1 root src 3169 2009-04-29 13:56 ../payloads/sgabios.bin* > $ tools/checksum.py <../payloads/sgabios.bin > sum=50b76 Heh - sgabios isn't properly checksumming. It was just dumb luck that my binary summed to zero. This is a hack, but you can use seabios' rom building tool to make it work: tools/buildrom.py ../payloads/sgabios.bin sgabios-cksum.bin Someone should follow up with google on this.. -Kevin -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot ----- End forwarded message -----

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coreboot May 2009