coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

Re: [coreboot] [flashrom] report error on flashrom read
by Carl-Daniel Hailfinger 15 May '09

15 May '09

[moving to coreboot@] On 15.05.2009 00:58, Ward Vandewege wrote: > On Thu, May 14, 2009 at 11:13:45PM +0200, Carl-Daniel Hailfinger wrote: > >> Can you please run >> flashrom -V >> and mail the output to us? This will help us to add support for your chip. >> >> On 14.05.2009 23:00, wangji wrote: >> >>> ./flashrom -r YellowPc.rom >>> flashrom v0.9.0-r510 >>> No coreboot table found. >>> Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. >>> Calibrating delay loop... OK. >>> Found chip "EON unknown EON SPI chip" (0 KB) at physical address 0x0. >>> >>> >> Great. First time that the unknown chip logic triggered and it was >> immediately useful. >> >> >>> === >>> This flash part has status NOT WORKING for operations: PROBE READ ERASE >>> WRITE >>> Please email a report to flashrom(a)coreboot.org if any of the above >>> operations >>> work correctly for you with this flash part. Please include the full >>> output >>> from the program, including chipset found. Thank you for your help! >>> === >>> > > -> would it make sense to suggest to the user to write to us with flashrom -V > output, since we want that output to debug almost all problems? > Indeed. We should also tell the user not to reboot and mail us or join IRC if any modifying operation fails. My medium-term plan is to have flashrom read the flash before any erase or write (with opt-out possibility) and if erase fails halfway through, try to restore. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 15

#118: Flashrom Makefile improvements
by coreboot 15 May '09

15 May '09

#118: Flashrom Makefile improvements ----------------------------------+----------------------------------------- Reporter: spooky85@… | Owner: somebody Type: task | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- hi guys, i wrote a small Makefile patch for flashrom. a few improvements and i corrected LD/C-FLAGS usage and link order e.g. for --as-needed. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/118> coreboot <http://www.coreboot.org/>

1 3

#136: failed to boot under KVM\QEMU
by coreboot 15 May '09

15 May '09

#136: failed to boot under KVM\QEMU -------------------------------------+-------------------------------------- Reporter: silicium@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------+-------------------------------------- I try to boot kvm with coreboot and kernel payload, but boot hangup. Last massage from it is: Loading Segment: addr: 0x0000000000020000 memsz: 0x0000000000001070 filesz: 0x0000000000000000 Post relocation: addr: 0x0000000000020000 memsz: 0x0000000000001070 filesz: 0x0000000000000000 Clearing Segment: addr: 0x00000000000090ae memsz: 0x0000000000008f0e coreboot-2.0.0-r4281-GRUB2 Срд Май 13 22:50:59 MSD 2009 starting... Uncompressing coreboot to RAM. Uncompressing image to RAM. I investigate and solve problem. Patch applied. Please review it. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/136> coreboot <http://www.coreboot.org/>

3 4

Trac reminder: list of new ticket(s)
by coreboot tracker 15 May '09

15 May '09

1 0

[flashrom] BIOS lock enable patch fixed
by Daniel McLellan 15 May '09

15 May '09

Author : Javeed Shaikh : Daniel McLellan Date: Fri May 15 10:11:40 EDT 2009 Modified: trunk/flashrom/chipset_enable.c Log: warning for BIOS lock enable --- flashrom/chipset_enable.c 2009-05-15 10:07:38.888122441 -0400 +++ chipset_enable.c.new 2009-05-15 10:03:45.686122396 -0400 @@ -178,8 +178,11 @@ printf_debug("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); printf_debug("BIOS_CNTL is 0x%x\n", old); + if ( (old & (1 << 1)) && !(old & (1 << 0) )) { + printf("\nBIOS Lock enabled. Please refer to your manual to disable.\n"); + } new = old | 1; if (new == old) return 0;

1 0

chipset_enable BIOS Lock enabled patch
by psibyrion 15 May '09

15 May '09

Author : Javeed Shaikh : Daniel McLellan Date: Fri May 15 08:09:07 EDT 2009 Modified: trunk/flashrom/chipset_enable.c Log: warning for BIOS lock enable Signed-off-by: Daniel McLellan (raijin) <daniel.mclellan(a)gmail.com> --- chipset_enable.c~ 2009-05-14 11:47:02.254392318 -0400 +++ chipset_enable.c 09-05-14 11:47:02.351382159 -0400 @@ -178,8 +178,11 @@ printf_debug("BIOS Write Enable: %sabled, ", (old & (1 << 0)) ? "en" : "dis"); printf_debug("BIOS_CNTL is 0x%x\n", old); + if ( (old & (1 << 1)) && !(old & (1 << 0) ) + printf("\nBIOS Lock enabled. Please refer to your manual to disable.\n"); + new = old | 1; if (new == old) return 0;

1 0

Winbond W39V040A Testresults
by Thomas Schneider 15 May '09

15 May '09

I have a "VIA VT8237" chipset with a "Winbond W39V040A" chip on it. I tested probe and read. Output: FuckUP ~ # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "Winbond W39V040A" (512 KB) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === No operations were specified. FuckUP ~ # flashrom -r bios-backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "Winbond W39V040A" (512 KB) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading flash... done.

2 1

Trac Spam
by Gregg Levine 15 May '09

15 May '09

Hello! Just for the sake of argument, is everyone aware of this annoying tendency of Trac to attract spam? This guy is getting to be more annoying then a certain series of advertisments on the telly for something even more useless then a certain brand of soft drink. And no I am not going to quote any of that ***** here. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature was once found posting rude messages in English in the Moscow subway."

1 0

[PATCH] flashrom: Handle WREN and EWSR failure gracefully on ICH/VIA SPI
by Carl-Daniel Hailfinger 14 May '09

14 May '09

Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes status register writes on almost all ICH+VIA SPI masters. The fix is almost identical to r484, but this time it affects the EWSR (Enable Write Status Register) opcode instead of the WREN (Write Enable) opcode. With the differentiated return codes introduced in r500, the workaround is more precise this time. The old WREN workaround was updated as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c =================================================================== --- flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c (Revision 505) +++ flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c (Arbeitskopie) @@ -116,8 +116,10 @@ /* Send WREN (Write Enable) */ result = spi_command(sizeof(cmd), 0, cmd, NULL); - if (result) { - printf_debug("spi_write_enable failed"); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { switch (flashbus) { case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: @@ -126,9 +128,12 @@ " and hoping it will be run as PREOP\n"); return 0; default: - printf_debug("\n"); + break; } } + if (result) + printf_debug("\n"); + return result; } @@ -555,9 +560,29 @@ int spi_write_status_enable(void) { const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; + int result; /* Send EWSR (Enable Write Status Register). */ - return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: + case BUS_TYPE_VIA_SPI: + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + return 0; + default: + break; + } + } + if (result) + printf_debug("\n"); + + return result; } /* -- http://www.hailfinger.org/ Index: flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c =================================================================== --- flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c (Revision 505) +++ flashrom-spi_wren_ewsr_error_checking_ichspi_workaround/spi.c (Arbeitskopie) @@ -116,8 +116,10 @@ /* Send WREN (Write Enable) */ result = spi_command(sizeof(cmd), 0, cmd, NULL); - if (result) { - printf_debug("spi_write_enable failed"); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { switch (flashbus) { case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: @@ -126,9 +128,12 @@ " and hoping it will be run as PREOP\n"); return 0; default: - printf_debug("\n"); + break; } } + if (result) + printf_debug("\n"); + return result; } @@ -555,9 +560,29 @@ int spi_write_status_enable(void) { const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; + int result; /* Send EWSR (Enable Write Status Register). */ - return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: + case BUS_TYPE_VIA_SPI: + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + return 0; + default: + break; + } + } + if (result) + printf_debug("\n"); + + return result; } /*

3 3

[flashrom] r514 - trunk
by svn＠coreboot.org 14 May '09

14 May '09

Author: hailfinger Date: 2009-05-15 02:56:22 +0200 (Fri, 15 May 2009) New Revision: 514 Modified: trunk/spi.c Log: Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes status register writes on almost all ICH+VIA SPI masters. The fix is almost identical to r484, but this time it affects the EWSR (Enable Write Status Register) opcode instead of the WREN (Write Enable) opcode. With the differentiated return codes introduced in r500, the workaround is more precise this time. The old WREN workaround was updated as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: FENG Yu Ning <fengyuning1984(a)gmail.com> Acked-by: Cristi Magherusan <cristi.magherusan(a)net.utcluj.ro> Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-05-14 22:58:21 UTC (rev 513) +++ trunk/spi.c 2009-05-15 00:56:22 UTC (rev 514) @@ -121,8 +121,10 @@ /* Send WREN (Write Enable) */ result = spi_command(sizeof(cmd), 0, cmd, NULL); - if (result) { - printf_debug("spi_write_enable failed"); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { switch (flashbus) { case BUS_TYPE_ICH7_SPI: case BUS_TYPE_ICH9_SPI: @@ -131,9 +133,12 @@ " and hoping it will be run as PREOP\n"); return 0; default: - printf_debug("\n"); + break; } } + if (result) + printf_debug("\n"); + return result; } @@ -561,9 +566,29 @@ int spi_write_status_enable(void) { const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR }; + int result; /* Send EWSR (Enable Write Status Register). */ - return spi_command(JEDEC_EWSR_OUTSIZE, JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + + if (result) + printf_debug("%s failed", __func__); + if (result == SPI_INVALID_OPCODE) { + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: + case BUS_TYPE_VIA_SPI: + printf_debug(" due to SPI master limitation, ignoring" + " and hoping it will be run as PREOP\n"); + return 0; + default: + break; + } + } + if (result) + printf_debug("\n"); + + return result; } /*

1 0

← Newer
1
...
28
29
30
31
32
33
34
...
58
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2009