coreboot May 2009

coreboot@coreboot.org

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571 discussions

[flashrom] Write support doesn't work on A7M266-D
by Pierre Bogossian 18 May '09

18 May '09

Hi, in january, I sent a mail to report that I could not flash a Pm49FL002 chip on my A7M266-D motherboard using flashrom. Since then, I tried to figure out what was going wrong. I discovered that the problem comes from the TBL# and WP# pins of the flash chip that have to be set high to disable write protection respectively on the boot block and on the rest of the memory (I guess all of you already knew that, but I'm a noob, so it's new for me). Flashing the chip using AFLASH, I checked with a voltmeter that the voltage at the WP# pin is jumping from 0V to 3.3V and then 0V again, every time a block is written. Doing the same test while flashing with flashrom, the voltmeter reads 0V all the time. So it seems clear that flashrom is not doing what is needed to set the TBL# and WP# pins high when a write is done. Now, I have no idea how to set these pins high. Are these pins controlled by the AMD-768 chipset ? I searched the documentation provided by AMD but found no mention about these pins. All I found is that a bit in a register (0x40) has to be set to enable LPC ROM write, but flashrom is already doing that, so I suppose it's unrelated to the TBL#/WP# write protection. Can someone tell me how the voltage of pins TBL#/WP# is controlled ? Pierre -- Be Yourself @ mail.com! Choose From 200+ Email Addresses Get a Free Account at www.mail.com

3 2

[PATCH] flashrom add PMC 39F010
by Rudolf Marek 18 May '09

18 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkoQQLIACgkQ3J9wPJqZRNUkrQCfYNGfDd9j+C5w6LHaCfSpOJ1e YpEAoJbDc9H7g6GjqS+anB3odMb0LhLY =ax1K -----END PGP SIGNATURE-----

2 1

[PATCH] tested SST39VF010
by Rudolf Marek 18 May '09

18 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkoQQGIACgkQ3J9wPJqZRNURVACgj1700wKrsx9ld4iaEsS558s6 OEEAnjbhIgazOEEjXLvKwva7MS4lGAzB =yq2h -----END PGP SIGNATURE-----

2 1

[PATCH] flashrom: Use accessor functions for MMIO
by Carl-Daniel Hailfinger 18 May '09

18 May '09

Use accessor functions for MMIO. Some MMIO accesses used volatile, others didn't (and risked non-execution of side effects) and even with volatile, some accesses looked dubious. Since the MMIO accessor functions and the onboard flash accessor functions are functionally identical (but have different signatures), make the flash accessors wrappers for the MMIO accessors. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Compile tested only. Index: flashrom-mmio_accessors/flash.h =================================================================== --- flashrom-mmio_accessors/flash.h (Revision 523) +++ flashrom-mmio_accessors/flash.h (Arbeitskopie) @@ -621,6 +621,12 @@ uint8_t internal_chip_readb(const chipaddr addr); uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); +void mmio_writeb(uint8_t val, void * addr); +void mmio_writew(uint16_t val, void * addr); +void mmio_writel(uint32_t val, void * addr); +uint8_t mmio_readb(void * addr); +uint16_t mmio_readw(void * addr); +uint32_t mmio_readl(void * addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); uint16_t fallback_chip_readw(const chipaddr addr); @@ -731,7 +737,7 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); uint8_t sb600_read_status_register(void); -extern uint8_t volatile *sb600_spibar; +extern uint8_t *sb600_spibar; /* jedec.c */ uint8_t oddparity(uint8_t val); Index: flashrom-mmio_accessors/chipset_enable.c =================================================================== --- flashrom-mmio_accessors/chipset_enable.c (Revision 523) +++ flashrom-mmio_accessors/chipset_enable.c (Arbeitskopie) @@ -215,7 +215,7 @@ spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", - *(uint16_t *) (spibar + 0x6c)); + mmio_readw(spibar + 0x6c)); flashbus = BUS_TYPE_VIA_SPI; ich_init_opcodes(); @@ -245,14 +245,14 @@ /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); - gcs = *(volatile uint32_t *)(rcrb + 0x3410); + gcs = mmio_readl(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - buc = *(volatile uint8_t *)(rcrb + 0x3414); + buc = mmio_readb(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); @@ -292,44 +292,44 @@ switch (flashbus) { case BUS_TYPE_ICH7_SPI: printf_debug("0x00: 0x%04x (SPIS)\n", - *(uint16_t *) (spibar + 0)); + mmio_readw(spibar + 0)); printf_debug("0x02: 0x%04x (SPIC)\n", - *(uint16_t *) (spibar + 2)); + mmio_readw(spibar + 2)); printf_debug("0x04: 0x%08x (SPIA)\n", - *(uint32_t *) (spibar + 4)); + mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - *(uint32_t *) (spibar + offs + 4), i); + mmio_readl(spibar + offs + 4), i); } printf_debug("0x50: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0x50)); + mmio_readl(spibar + 0x50)); printf_debug("0x54: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x54)); + mmio_readw(spibar + 0x54)); printf_debug("0x56: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x56)); + mmio_readw(spibar + 0x56)); printf_debug("0x58: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5c: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x5c)); + mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); } printf_debug("\n"); - if ((*(uint16_t *) spibar) & (1 << 15)) { + if (mmio_readw(spibar) & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case BUS_TYPE_ICH9_SPI: - tmp2 = *(uint16_t *) (spibar + 4); + tmp2 = mmio_readw(spibar + 4); printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); printf_debug("FDV %i, ", (tmp2 >> 14) & 1); @@ -340,7 +340,7 @@ printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = *(uint32_t *) (spibar + 0x50); + tmp = mmio_readl(spibar + 0x50); printf_debug("0x50: 0x%08x (FRAP)\n", tmp); printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); @@ -348,39 +348,39 @@ printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); printf_debug("0x54: 0x%08x (FREG0)\n", - *(uint32_t *) (spibar + 0x54)); + mmio_readl(spibar + 0x54)); printf_debug("0x58: 0x%08x (FREG1)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5C: 0x%08x (FREG2)\n", - *(uint32_t *) (spibar + 0x5C)); + mmio_readl(spibar + 0x5C)); printf_debug("0x60: 0x%08x (FREG3)\n", - *(uint32_t *) (spibar + 0x60)); + mmio_readl(spibar + 0x60)); printf_debug("0x64: 0x%08x (FREG4)\n", - *(uint32_t *) (spibar + 0x64)); + mmio_readl(spibar + 0x64)); printf_debug("0x74: 0x%08x (PR0)\n", - *(uint32_t *) (spibar + 0x74)); + mmio_readl(spibar + 0x74)); printf_debug("0x78: 0x%08x (PR1)\n", - *(uint32_t *) (spibar + 0x78)); + mmio_readl(spibar + 0x78)); printf_debug("0x7C: 0x%08x (PR2)\n", - *(uint32_t *) (spibar + 0x7C)); + mmio_readl(spibar + 0x7C)); printf_debug("0x80: 0x%08x (PR3)\n", - *(uint32_t *) (spibar + 0x80)); + mmio_readl(spibar + 0x80)); printf_debug("0x84: 0x%08x (PR4)\n", - *(uint32_t *) (spibar + 0x84)); + mmio_readl(spibar + 0x84)); printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", - *(uint32_t *) (spibar + 0x90)); + mmio_readl(spibar + 0x90)); printf_debug("0x94: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x94)); + mmio_readw(spibar + 0x94)); printf_debug("0x96: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x96)); + mmio_readw(spibar + 0x96)); printf_debug("0x98: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x98)); + mmio_readl(spibar + 0x98)); printf_debug("0x9C: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x9C)); + mmio_readl(spibar + 0x9C)); printf_debug("0xA0: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0xA0)); + mmio_readl(spibar + 0xA0)); printf_debug("0xB0: 0x%08x (FDOC)\n", - *(uint32_t *) (spibar + 0xB0)); + mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; @@ -897,7 +897,7 @@ * BOOTCS region (PARx[31:29] = 100b)e */ for (i = 0x88; i <= 0xc4; i += 4) { - parx = *(volatile uint32_t *)(mmcr + i); + parx = mmio_readl(mmcr + i); if ((parx >> 29) == 4) { bootcs_found = 1; break; /* BOOTCS found */ Index: flashrom-mmio_accessors/sb600spi.c =================================================================== --- flashrom-mmio_accessors/sb600spi.c (Revision 523) +++ flashrom-mmio_accessors/sb600spi.c (Arbeitskopie) @@ -37,7 +37,7 @@ } sb600_spi_controller; sb600_spi_controller *spi_bar = NULL; -uint8_t volatile *sb600_spibar; +uint8_t *sb600_spibar; int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { @@ -91,17 +91,17 @@ void reset_internal_fifo_pointer(void) { - sb600_spibar[2] |= 0x10; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); - while (sb600_spibar[0xD] & 0x7) + while (mmio_readb(sb600_spibar + 0xD) & 0x7) printf("reset\n"); } void execute_command(void) { - sb600_spibar[2] |= 1; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (sb600_spibar[2] & 1) + while (mmio_readb(sb600_spibar + 2) & 1) ; } @@ -131,8 +131,8 @@ return 1; } - sb600_spibar[0] = cmd; - sb600_spibar[1] = readcnt << 4 | (writecnt); + mmio_writeb(cmd, sb600_spibar + 0); + mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1); /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); @@ -140,7 +140,7 @@ /* Send the write byte to FIFO. */ for (count = 0; count < writecnt; count++, writearr++) { printf_debug(" [%x]", *writearr); - sb600_spibar[0xC] = *writearr; + mmio_writeb(*writearr, sb600_spibar + 0xC); } printf_debug("\n"); @@ -160,13 +160,13 @@ reset_internal_fifo_pointer(); for (count = 0; count < writecnt; count++) { - cmd = sb600_spibar[0xC]; /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", sb600_spibar[0xd] & 0x07); + printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { - *readarr = sb600_spibar[0xC]; + *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); } printf_debug("\n"); Index: flashrom-mmio_accessors/internal.c =================================================================== --- flashrom-mmio_accessors/internal.c (Revision 523) +++ flashrom-mmio_accessors/internal.c (Arbeitskopie) @@ -137,31 +137,61 @@ void internal_chip_writeb(uint8_t val, chipaddr addr) { - *(volatile uint8_t *) addr = val; + mmio_writeb(val, (void *)addr); } void internal_chip_writew(uint16_t val, chipaddr addr) { - *(volatile uint16_t *) addr = val; + mmio_writew(val, (void *)addr); } void internal_chip_writel(uint32_t val, chipaddr addr) { - *(volatile uint32_t *) addr = val; + mmio_writel(val, (void *)addr); } uint8_t internal_chip_readb(const chipaddr addr) { - return *(volatile uint8_t *) addr; + return mmio_readb((void *)addr); } uint16_t internal_chip_readw(const chipaddr addr) { - return *(volatile uint16_t *) addr; + return mmio_readw((void *)addr); } uint32_t internal_chip_readl(const chipaddr addr) { + return mmio_readl((void *)addr); +} + +void mmio_writeb(uint8_t val, void * addr) +{ + *(volatile uint8_t *) addr = val; +} + +void mmio_writew(uint16_t val, void * addr) +{ + *(volatile uint16_t *) addr = val; +} + +void mmio_writel(uint32_t val, void * addr) +{ + *(volatile uint32_t *) addr = val; +} + +uint8_t mmio_readb(void * addr) +{ + return *(volatile uint8_t *) addr; +} + +uint16_t mmio_readw(void * addr) +{ + return *(volatile uint16_t *) addr; +} + +uint32_t mmio_readl(void * addr) +{ return *(volatile uint32_t *) addr; } Index: flashrom-mmio_accessors/ichspi.c =================================================================== --- flashrom-mmio_accessors/ichspi.c (Revision 523) +++ flashrom-mmio_accessors/ichspi.c (Arbeitskopie) @@ -129,21 +129,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - volatile uint32_t regval; - regval = *(volatile uint32_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readl(spibar + X); } static uint16_t REGREAD16(int X) { - volatile uint16_t regval; - regval = *(volatile uint16_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readw(spibar + X); } -#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y) +#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); -- http://www.hailfinger.org/ Index: flashrom-mmio_accessors/flash.h =================================================================== --- flashrom-mmio_accessors/flash.h (Revision 523) +++ flashrom-mmio_accessors/flash.h (Arbeitskopie) @@ -621,6 +621,12 @@ uint8_t internal_chip_readb(const chipaddr addr); uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); +void mmio_writeb(uint8_t val, void * addr); +void mmio_writew(uint16_t val, void * addr); +void mmio_writel(uint32_t val, void * addr); +uint8_t mmio_readb(void * addr); +uint16_t mmio_readw(void * addr); +uint32_t mmio_readl(void * addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); uint16_t fallback_chip_readw(const chipaddr addr); @@ -731,7 +737,7 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); uint8_t sb600_read_status_register(void); -extern uint8_t volatile *sb600_spibar; +extern uint8_t *sb600_spibar; /* jedec.c */ uint8_t oddparity(uint8_t val); Index: flashrom-mmio_accessors/chipset_enable.c =================================================================== --- flashrom-mmio_accessors/chipset_enable.c (Revision 523) +++ flashrom-mmio_accessors/chipset_enable.c (Arbeitskopie) @@ -215,7 +215,7 @@ spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", - *(uint16_t *) (spibar + 0x6c)); + mmio_readw(spibar + 0x6c)); flashbus = BUS_TYPE_VIA_SPI; ich_init_opcodes(); @@ -245,14 +245,14 @@ /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); - gcs = *(volatile uint32_t *)(rcrb + 0x3410); + gcs = mmio_readl(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - buc = *(volatile uint8_t *)(rcrb + 0x3414); + buc = mmio_readb(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); @@ -292,44 +292,44 @@ switch (flashbus) { case BUS_TYPE_ICH7_SPI: printf_debug("0x00: 0x%04x (SPIS)\n", - *(uint16_t *) (spibar + 0)); + mmio_readw(spibar + 0)); printf_debug("0x02: 0x%04x (SPIC)\n", - *(uint16_t *) (spibar + 2)); + mmio_readw(spibar + 2)); printf_debug("0x04: 0x%08x (SPIA)\n", - *(uint32_t *) (spibar + 4)); + mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - *(uint32_t *) (spibar + offs + 4), i); + mmio_readl(spibar + offs + 4), i); } printf_debug("0x50: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0x50)); + mmio_readl(spibar + 0x50)); printf_debug("0x54: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x54)); + mmio_readw(spibar + 0x54)); printf_debug("0x56: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x56)); + mmio_readw(spibar + 0x56)); printf_debug("0x58: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5c: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x5c)); + mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); } printf_debug("\n"); - if ((*(uint16_t *) spibar) & (1 << 15)) { + if (mmio_readw(spibar) & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case BUS_TYPE_ICH9_SPI: - tmp2 = *(uint16_t *) (spibar + 4); + tmp2 = mmio_readw(spibar + 4); printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); printf_debug("FDV %i, ", (tmp2 >> 14) & 1); @@ -340,7 +340,7 @@ printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = *(uint32_t *) (spibar + 0x50); + tmp = mmio_readl(spibar + 0x50); printf_debug("0x50: 0x%08x (FRAP)\n", tmp); printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); @@ -348,39 +348,39 @@ printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); printf_debug("0x54: 0x%08x (FREG0)\n", - *(uint32_t *) (spibar + 0x54)); + mmio_readl(spibar + 0x54)); printf_debug("0x58: 0x%08x (FREG1)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5C: 0x%08x (FREG2)\n", - *(uint32_t *) (spibar + 0x5C)); + mmio_readl(spibar + 0x5C)); printf_debug("0x60: 0x%08x (FREG3)\n", - *(uint32_t *) (spibar + 0x60)); + mmio_readl(spibar + 0x60)); printf_debug("0x64: 0x%08x (FREG4)\n", - *(uint32_t *) (spibar + 0x64)); + mmio_readl(spibar + 0x64)); printf_debug("0x74: 0x%08x (PR0)\n", - *(uint32_t *) (spibar + 0x74)); + mmio_readl(spibar + 0x74)); printf_debug("0x78: 0x%08x (PR1)\n", - *(uint32_t *) (spibar + 0x78)); + mmio_readl(spibar + 0x78)); printf_debug("0x7C: 0x%08x (PR2)\n", - *(uint32_t *) (spibar + 0x7C)); + mmio_readl(spibar + 0x7C)); printf_debug("0x80: 0x%08x (PR3)\n", - *(uint32_t *) (spibar + 0x80)); + mmio_readl(spibar + 0x80)); printf_debug("0x84: 0x%08x (PR4)\n", - *(uint32_t *) (spibar + 0x84)); + mmio_readl(spibar + 0x84)); printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", - *(uint32_t *) (spibar + 0x90)); + mmio_readl(spibar + 0x90)); printf_debug("0x94: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x94)); + mmio_readw(spibar + 0x94)); printf_debug("0x96: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x96)); + mmio_readw(spibar + 0x96)); printf_debug("0x98: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x98)); + mmio_readl(spibar + 0x98)); printf_debug("0x9C: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x9C)); + mmio_readl(spibar + 0x9C)); printf_debug("0xA0: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0xA0)); + mmio_readl(spibar + 0xA0)); printf_debug("0xB0: 0x%08x (FDOC)\n", - *(uint32_t *) (spibar + 0xB0)); + mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; @@ -897,7 +897,7 @@ * BOOTCS region (PARx[31:29] = 100b)e */ for (i = 0x88; i <= 0xc4; i += 4) { - parx = *(volatile uint32_t *)(mmcr + i); + parx = mmio_readl(mmcr + i); if ((parx >> 29) == 4) { bootcs_found = 1; break; /* BOOTCS found */ Index: flashrom-mmio_accessors/sb600spi.c =================================================================== --- flashrom-mmio_accessors/sb600spi.c (Revision 523) +++ flashrom-mmio_accessors/sb600spi.c (Arbeitskopie) @@ -37,7 +37,7 @@ } sb600_spi_controller; sb600_spi_controller *spi_bar = NULL; -uint8_t volatile *sb600_spibar; +uint8_t *sb600_spibar; int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { @@ -91,17 +91,17 @@ void reset_internal_fifo_pointer(void) { - sb600_spibar[2] |= 0x10; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); - while (sb600_spibar[0xD] & 0x7) + while (mmio_readb(sb600_spibar + 0xD) & 0x7) printf("reset\n"); } void execute_command(void) { - sb600_spibar[2] |= 1; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (sb600_spibar[2] & 1) + while (mmio_readb(sb600_spibar + 2) & 1) ; } @@ -131,8 +131,8 @@ return 1; } - sb600_spibar[0] = cmd; - sb600_spibar[1] = readcnt << 4 | (writecnt); + mmio_writeb(cmd, sb600_spibar + 0); + mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1); /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); @@ -140,7 +140,7 @@ /* Send the write byte to FIFO. */ for (count = 0; count < writecnt; count++, writearr++) { printf_debug(" [%x]", *writearr); - sb600_spibar[0xC] = *writearr; + mmio_writeb(*writearr, sb600_spibar + 0xC); } printf_debug("\n"); @@ -160,13 +160,13 @@ reset_internal_fifo_pointer(); for (count = 0; count < writecnt; count++) { - cmd = sb600_spibar[0xC]; /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", sb600_spibar[0xd] & 0x07); + printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { - *readarr = sb600_spibar[0xC]; + *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); } printf_debug("\n"); Index: flashrom-mmio_accessors/internal.c =================================================================== --- flashrom-mmio_accessors/internal.c (Revision 523) +++ flashrom-mmio_accessors/internal.c (Arbeitskopie) @@ -137,31 +137,61 @@ void internal_chip_writeb(uint8_t val, chipaddr addr) { - *(volatile uint8_t *) addr = val; + mmio_writeb(val, (void *)addr); } void internal_chip_writew(uint16_t val, chipaddr addr) { - *(volatile uint16_t *) addr = val; + mmio_writew(val, (void *)addr); } void internal_chip_writel(uint32_t val, chipaddr addr) { - *(volatile uint32_t *) addr = val; + mmio_writel(val, (void *)addr); } uint8_t internal_chip_readb(const chipaddr addr) { - return *(volatile uint8_t *) addr; + return mmio_readb((void *)addr); } uint16_t internal_chip_readw(const chipaddr addr) { - return *(volatile uint16_t *) addr; + return mmio_readw((void *)addr); } uint32_t internal_chip_readl(const chipaddr addr) { + return mmio_readl((void *)addr); +} + +void mmio_writeb(uint8_t val, void * addr) +{ + *(volatile uint8_t *) addr = val; +} + +void mmio_writew(uint16_t val, void * addr) +{ + *(volatile uint16_t *) addr = val; +} + +void mmio_writel(uint32_t val, void * addr) +{ + *(volatile uint32_t *) addr = val; +} + +uint8_t mmio_readb(void * addr) +{ + return *(volatile uint8_t *) addr; +} + +uint16_t mmio_readw(void * addr) +{ + return *(volatile uint16_t *) addr; +} + +uint32_t mmio_readl(void * addr) +{ return *(volatile uint32_t *) addr; } Index: flashrom-mmio_accessors/ichspi.c =================================================================== --- flashrom-mmio_accessors/ichspi.c (Revision 523) +++ flashrom-mmio_accessors/ichspi.c (Arbeitskopie) @@ -129,21 +129,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - volatile uint32_t regval; - regval = *(volatile uint32_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readl(spibar + X); } static uint16_t REGREAD16(int X) { - volatile uint16_t regval; - regval = *(volatile uint16_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readw(spibar + X); } -#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y) +#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode);

2 2

[flashrom] r524 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: hailfinger Date: 2009-05-17 17:49:24 +0200 (Sun, 17 May 2009) New Revision: 524 Modified: trunk/chipset_enable.c trunk/flash.h trunk/ichspi.c trunk/internal.c trunk/sb600spi.c Log: Use accessor functions for MMIO. Some MMIO accesses used volatile, others didn't (and risked non-execution of side effects) and even with volatile, some accesses looked dubious. Since the MMIO accessor functions and the onboard flash accessor functions are functionally identical (but have different signatures), make the flash accessors wrappers for the MMIO accessors. For some of the conversions, I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b ) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Uwe tested read, write, erase with this patch on a random board to make sure nothing breaks. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-16 23:42:17 UTC (rev 523) +++ trunk/chipset_enable.c 2009-05-17 15:49:24 UTC (rev 524) @@ -215,7 +215,7 @@ spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", - *(uint16_t *) (spibar + 0x6c)); + mmio_readw(spibar + 0x6c)); flashbus = BUS_TYPE_VIA_SPI; ich_init_opcodes(); @@ -245,14 +245,14 @@ /* Map RCBA to virtual memory */ rcrb = physmap("ICH RCRB", tmp, 0x4000); - gcs = *(volatile uint32_t *)(rcrb + 0x3410); + gcs = mmio_readl(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); - buc = *(volatile uint8_t *)(rcrb + 0x3414); + buc = mmio_readb(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); @@ -292,44 +292,44 @@ switch (flashbus) { case BUS_TYPE_ICH7_SPI: printf_debug("0x00: 0x%04x (SPIS)\n", - *(uint16_t *) (spibar + 0)); + mmio_readw(spibar + 0)); printf_debug("0x02: 0x%04x (SPIC)\n", - *(uint16_t *) (spibar + 2)); + mmio_readw(spibar + 2)); printf_debug("0x04: 0x%08x (SPIA)\n", - *(uint32_t *) (spibar + 4)); + mmio_readl(spibar + 4)); for (i = 0; i < 8; i++) { int offs; offs = 8 + (i * 8); printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - *(uint32_t *) (spibar + offs + 4), i); + mmio_readl(spibar + offs + 4), i); } printf_debug("0x50: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0x50)); + mmio_readl(spibar + 0x50)); printf_debug("0x54: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x54)); + mmio_readw(spibar + 0x54)); printf_debug("0x56: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x56)); + mmio_readw(spibar + 0x56)); printf_debug("0x58: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5c: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x5c)); + mmio_readl(spibar + 0x5c)); for (i = 0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, - *(uint32_t *) (spibar + offs), i); + mmio_readl(spibar + offs), i); } printf_debug("\n"); - if ((*(uint16_t *) spibar) & (1 << 15)) { + if (mmio_readw(spibar) & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); break; case BUS_TYPE_ICH9_SPI: - tmp2 = *(uint16_t *) (spibar + 4); + tmp2 = mmio_readw(spibar + 4); printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); printf_debug("FDV %i, ", (tmp2 >> 14) & 1); @@ -340,7 +340,7 @@ printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); - tmp = *(uint32_t *) (spibar + 0x50); + tmp = mmio_readl(spibar + 0x50); printf_debug("0x50: 0x%08x (FRAP)\n", tmp); printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); @@ -348,39 +348,39 @@ printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); printf_debug("0x54: 0x%08x (FREG0)\n", - *(uint32_t *) (spibar + 0x54)); + mmio_readl(spibar + 0x54)); printf_debug("0x58: 0x%08x (FREG1)\n", - *(uint32_t *) (spibar + 0x58)); + mmio_readl(spibar + 0x58)); printf_debug("0x5C: 0x%08x (FREG2)\n", - *(uint32_t *) (spibar + 0x5C)); + mmio_readl(spibar + 0x5C)); printf_debug("0x60: 0x%08x (FREG3)\n", - *(uint32_t *) (spibar + 0x60)); + mmio_readl(spibar + 0x60)); printf_debug("0x64: 0x%08x (FREG4)\n", - *(uint32_t *) (spibar + 0x64)); + mmio_readl(spibar + 0x64)); printf_debug("0x74: 0x%08x (PR0)\n", - *(uint32_t *) (spibar + 0x74)); + mmio_readl(spibar + 0x74)); printf_debug("0x78: 0x%08x (PR1)\n", - *(uint32_t *) (spibar + 0x78)); + mmio_readl(spibar + 0x78)); printf_debug("0x7C: 0x%08x (PR2)\n", - *(uint32_t *) (spibar + 0x7C)); + mmio_readl(spibar + 0x7C)); printf_debug("0x80: 0x%08x (PR3)\n", - *(uint32_t *) (spibar + 0x80)); + mmio_readl(spibar + 0x80)); printf_debug("0x84: 0x%08x (PR4)\n", - *(uint32_t *) (spibar + 0x84)); + mmio_readl(spibar + 0x84)); printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", - *(uint32_t *) (spibar + 0x90)); + mmio_readl(spibar + 0x90)); printf_debug("0x94: 0x%04x (PREOP)\n", - *(uint16_t *) (spibar + 0x94)); + mmio_readw(spibar + 0x94)); printf_debug("0x96: 0x%04x (OPTYPE)\n", - *(uint16_t *) (spibar + 0x96)); + mmio_readw(spibar + 0x96)); printf_debug("0x98: 0x%08x (OPMENU)\n", - *(uint32_t *) (spibar + 0x98)); + mmio_readl(spibar + 0x98)); printf_debug("0x9C: 0x%08x (OPMENU+4)\n", - *(uint32_t *) (spibar + 0x9C)); + mmio_readl(spibar + 0x9C)); printf_debug("0xA0: 0x%08x (BBAR)\n", - *(uint32_t *) (spibar + 0xA0)); + mmio_readl(spibar + 0xA0)); printf_debug("0xB0: 0x%08x (FDOC)\n", - *(uint32_t *) (spibar + 0xB0)); + mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; @@ -897,7 +897,7 @@ * BOOTCS region (PARx[31:29] = 100b)e */ for (i = 0x88; i <= 0xc4; i += 4) { - parx = *(volatile uint32_t *)(mmcr + i); + parx = mmio_readl(mmcr + i); if ((parx >> 29) == 4) { bootcs_found = 1; break; /* BOOTCS found */ Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-16 23:42:17 UTC (rev 523) +++ trunk/flash.h 2009-05-17 15:49:24 UTC (rev 524) @@ -621,6 +621,12 @@ uint8_t internal_chip_readb(const chipaddr addr); uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); +void mmio_writeb(uint8_t val, void *addr); +void mmio_writew(uint16_t val, void *addr); +void mmio_writel(uint32_t val, void *addr); +uint8_t mmio_readb(void *addr); +uint16_t mmio_readw(void *addr); +uint32_t mmio_readl(void *addr); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); uint16_t fallback_chip_readw(const chipaddr addr); @@ -731,7 +737,7 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); uint8_t sb600_read_status_register(void); -extern uint8_t volatile *sb600_spibar; +extern uint8_t *sb600_spibar; /* jedec.c */ uint8_t oddparity(uint8_t val); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-05-16 23:42:17 UTC (rev 523) +++ trunk/ichspi.c 2009-05-17 15:49:24 UTC (rev 524) @@ -129,21 +129,17 @@ /* HW access functions */ static uint32_t REGREAD32(int X) { - volatile uint32_t regval; - regval = *(volatile uint32_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readl(spibar + X); } static uint16_t REGREAD16(int X) { - volatile uint16_t regval; - regval = *(volatile uint16_t *)((uint8_t *) spibar + X); - return regval; + return mmio_readw(spibar + X); } -#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y) -#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y) +#define REGWRITE32(X,Y) mmio_writel(Y, spibar+X) +#define REGWRITE16(X,Y) mmio_writew(Y, spibar+X) +#define REGWRITE8(X,Y) mmio_writeb(Y, spibar+X) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-05-16 23:42:17 UTC (rev 523) +++ trunk/internal.c 2009-05-17 15:49:24 UTC (rev 524) @@ -137,31 +137,61 @@ void internal_chip_writeb(uint8_t val, chipaddr addr) { - *(volatile uint8_t *) addr = val; + mmio_writeb(val, (void *) addr); } void internal_chip_writew(uint16_t val, chipaddr addr) { - *(volatile uint16_t *) addr = val; + mmio_writew(val, (void *) addr); } void internal_chip_writel(uint32_t val, chipaddr addr) { - *(volatile uint32_t *) addr = val; + mmio_writel(val, (void *) addr); } uint8_t internal_chip_readb(const chipaddr addr) { - return *(volatile uint8_t *) addr; + return mmio_readb((void *) addr); } uint16_t internal_chip_readw(const chipaddr addr) { - return *(volatile uint16_t *) addr; + return mmio_readw((void *) addr); } uint32_t internal_chip_readl(const chipaddr addr) { + return mmio_readl((void *) addr); +} + +void mmio_writeb(uint8_t val, void *addr) +{ + *(volatile uint8_t *) addr = val; +} + +void mmio_writew(uint16_t val, void *addr) +{ + *(volatile uint16_t *) addr = val; +} + +void mmio_writel(uint32_t val, void *addr) +{ + *(volatile uint32_t *) addr = val; +} + +uint8_t mmio_readb(void *addr) +{ + return *(volatile uint8_t *) addr; +} + +uint16_t mmio_readw(void *addr) +{ + return *(volatile uint16_t *) addr; +} + +uint32_t mmio_readl(void *addr) +{ return *(volatile uint32_t *) addr; } Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-05-16 23:42:17 UTC (rev 523) +++ trunk/sb600spi.c 2009-05-17 15:49:24 UTC (rev 524) @@ -37,7 +37,7 @@ } sb600_spi_controller; sb600_spi_controller *spi_bar = NULL; -uint8_t volatile *sb600_spibar; +uint8_t *sb600_spibar; int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { @@ -91,17 +91,17 @@ void reset_internal_fifo_pointer(void) { - sb600_spibar[2] |= 0x10; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); - while (sb600_spibar[0xD] & 0x7) + while (mmio_readb(sb600_spibar + 0xD) & 0x7) printf("reset\n"); } void execute_command(void) { - sb600_spibar[2] |= 1; + mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (sb600_spibar[2] & 1) + while (mmio_readb(sb600_spibar + 2) & 1) ; } @@ -131,8 +131,8 @@ return 1; } - sb600_spibar[0] = cmd; - sb600_spibar[1] = readcnt << 4 | (writecnt); + mmio_writeb(cmd, sb600_spibar + 0); + mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1); /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); @@ -140,7 +140,7 @@ /* Send the write byte to FIFO. */ for (count = 0; count < writecnt; count++, writearr++) { printf_debug(" [%x]", *writearr); - sb600_spibar[0xC] = *writearr; + mmio_writeb(*writearr, sb600_spibar + 0xC); } printf_debug("\n"); @@ -160,13 +160,13 @@ reset_internal_fifo_pointer(); for (count = 0; count < writecnt; count++) { - cmd = sb600_spibar[0xC]; /* Skip the byte we send. */ + cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */ printf_debug("[ %2x]", cmd); } - printf_debug("The FIFO pointer 6 is %d.\n", sb600_spibar[0xd] & 0x07); + printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07); for (count = 0; count < readcnt; count++, readarr++) { - *readarr = sb600_spibar[0xC]; + *readarr = mmio_readb(sb600_spibar + 0xC); printf_debug("[%02x]", *readarr); } printf_debug("\n");

1 0

FILO Compilation failure
by bifferos 17 May '09

17 May '09

I've tried to build FILO following instructions at http://www.coreboot.org/FILO, but it doesn't seem to work. Can anyone give any hints? 0.5 compiles fine. Here's what I typed (snipped the uninteresting info): wrt@cent:~/coreboot/filo$ svn co svn://coreboot.org/filo/trunk/filo Checked out external at revision 4289. Checked out revision 95. wrt@cent:~/coreboot/filo$ cd filo/ wrt@cent:~/coreboot/filo/filo$ cd libpayload/ wrt@cent:~/coreboot/filo/filo/libpayload$ make defconfig wrt@cent:~/coreboot/filo/filo/libpayload$ make wrt@cent:~/coreboot/filo/filo/libpayload$ make DESTDIR=../build install wrt@cent:~/coreboot/filo/filo/libpayload$ cd .. wrt@cent:~/coreboot/filo/filo$ make menuconfig wrt@cent:~/coreboot/filo/filo$ make .... CC build/i386/context.o AS build/i386/switch.S.o CC build/i386/segment.o /home/wrt/coreboot/filo/filo/i386/segment.c: In function 'relocate': /home/wrt/coreboot/filo/filo/i386/segment.c:77: error: 'struct memrange' has no member named 'type' make: *** [/home/wrt/coreboot/filo/filo/build/i386/segment.o] Error 1 thanks, Biff.

2 1

[flashrom] r523 - trunk
by svn＠coreboot.org 17 May '09

17 May '09

Author: uwe Date: 2009-05-17 01:42:17 +0200 (Sun, 17 May 2009) New Revision: 523 Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c Log: List all boards which are: - Supported out of the box (no flash enables required) - Verifiably not yet working (unknown flash enable) Also, move some structs to flash.h in preparation for later wiki output support. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-16 22:36:00 UTC (rev 522) +++ trunk/board_enable.c 2009-05-16 23:42:17 UTC (rev 523) @@ -661,31 +661,7 @@ * When a board is identified through its coreboot ids (in both cases), the * main pci ids are still required to match, as a safeguard. */ -struct board_pciid_enable { - /* Any device, but make it sensible, like the ISA bridge. */ - uint16_t first_vendor; - uint16_t first_device; - uint16_t first_card_vendor; - uint16_t first_card_device; - /* Any device, but make it sensible, like - * the host bridge. May be NULL. - */ - uint16_t second_vendor; - uint16_t second_device; - uint16_t second_card_vendor; - uint16_t second_card_device; - - /* The vendor / part name from the coreboot table. */ - const char *lb_vendor; - const char *lb_part; - - const char *vendor_name; - const char *board_name; - - int (*enable) (const char *name); -}; - /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ @@ -725,27 +701,132 @@ { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ }; +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info boards_ok[] = { + /* Verified working boards that don't need write-enables. */ + { "Abit", "AX8", }, + { "Advantech", "PCM-5820", }, + { "ASI", "MB-5BLMP", }, + { "ASUS", "A8N-E", }, + { "ASUS", "A8NE-FM/S", }, + { "ASUS", "A8N-SLI Premium", }, + { "ASUS", "A8V-E Deluxe", }, + { "ASUS", "M2A-VM", }, + { "ASUS", "M2N-E", }, + { "ASUS", "P2B", }, + { "ASUS", "P2B-F", }, + { "ASUS", "P2B-D", }, + { "ASUS", "P2B-DS", }, + { "ASUS", "A7V400-MX", }, + { "ASUS", "A7V8X-MX", }, + { "ASUS", "P4B266", }, + { "ASUS", "A8V-E SE", }, + { "ASUS", "P2L97-S", }, + { "ASUS", "M2A-MX", }, + { "A-Trend", "ATC-6220", }, + { "BCOM", "WinNET100", }, + { "GIGABYTE", "GA-6BXC", }, + { "GIGABYTE", "GA-6BXDU", }, + { "MSI", "KT4V", }, + { "MSI", "MS-7046", }, + { "MSI", "MS-7065", }, + { "MSI", "MS-7236 (945PL Neo3)", }, + { "NEC", "PowerMate 2000", }, + { "PC Engines", "Alix.1c", }, + { "PC Engines", "Alix.2c2", }, + { "PC Engines", "Alix.2c3", }, + { "PC Engines", "Alix.3c3", }, + { "RCA", "RM4100", }, + { "Sun", "Blade x6250", }, + { "Thomson", "IP1000", }, + { "T-Online", "S-100", }, + { "Tyan", "S1846", }, + { "Tyan", "S2498 (Tomcat K7M)", }, + { "Tyan", "S2881", }, + { "Tyan", "S2882", }, + { "Tyan", "S2882-D", }, + { "Tyan", "S3095", }, + { "Tyan", "S5180", }, + { "Tyan", "S5191", }, + { "Tyan", "S5197", }, + { "Tyan", "S5211", }, + { "Tyan", "S5211-1U", }, + { "Tyan", "S5220", }, + { "Tyan", "S5375", }, + { "Tyan", "iS5375-1U", }, + { "Tyan", "S5376G2NR/S5376}WAG2NR", }, + { "Tyan", "S5377", }, + { "Tyan", "S5397", }, + { "VIA", "EPIA-M", }, + { "VIA", "EPIA-MII", }, + { "VIA", "EPIA-CN", }, + { "VIA", "EPIA-LN", }, + { "VIA", "VB700X", }, + { "VIA", "NAB74X0", }, + { "VIA", "pc2500e", }, + + {}, +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const struct board_info boards_bad[] = { + /* Verified non-working boards (for now). */ + { "ASUS", "A7N8X-E Deluxe", }, + { "ASUS", "MEW-AM", }, + { "ASUS", "MEW-VM", }, + { "ASUS", "P3B-F", }, + { "Biostar", "M6TBA", }, + { "FIC", "VA-502", }, + { "MSI", "MS-7260 (K9N Neo)", }, + { "PCCHIPS", "M537DMA33", }, + { "Soyo", "SY-5VD", }, + { "Sun", "Fire x4540", }, + { "Sun", "Fire x4150", }, + { "Sun", "Fire x4200", }, + { "Sun", "Fire x4600", }, + + {}, +}; + +void print_supported_boards_helper(const struct board_info *b) +{ + int i, j; + + for (i = 0; b[i].vendor != NULL; i++) { + printf("%s", b[i].vendor); + for (j = 0; j < 25 - strlen(b[i].vendor); j++) + printf(" "); + printf("%s", b[i].name); + for (j = 0; j < 23 - strlen(b[i].name); j++) + printf(" "); + printf("\n"); + } +} + void print_supported_boards(void) { - int i; + int i, j; + struct board_pciid_enable *b = board_pciid_enables; - printf("\nSupported mainboards (this list is not exhaustive!):\n\n"); - - for (i = 0; board_pciid_enables[i].vendor_name != NULL; i++) { - if (board_pciid_enables[i].lb_vendor != NULL) { - printf("%s %s (-m %s:%s)\n", - board_pciid_enables[i].vendor_name, - board_pciid_enables[i].board_name, - board_pciid_enables[i].lb_vendor, - board_pciid_enables[i].lb_part); - } else { - printf("%s %s (autodetected)\n", - board_pciid_enables[i].vendor_name, - board_pciid_enables[i].board_name); - } + printf("\nSupported boards which need write-enable code:\n\n"); + for (i = 0; b[i].vendor_name != NULL; i++) { + printf("%s", b[i].vendor_name); + for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) + printf(" "); + printf("%s", b[i].board_name); + for (j = 0; j < 25 - strlen(b[i].board_name); j++) + printf(" "); + if (b[i].lb_vendor != NULL) + printf("(-m %s:%s)\n", b[i].lb_vendor, b[i].lb_part); + else + printf("(autodetected)\n"); } - printf("\nSee also: http://coreboot.org/Flashrom\n"); + printf("\nSupported boards which don't need write-enable code:\n\n"); + print_supported_boards_helper(boards_ok); + + printf("\nBoards which have been verified to NOT work (yet):\n\n"); + print_supported_boards_helper(boards_bad); } /** Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-16 22:36:00 UTC (rev 522) +++ trunk/chipset_enable.c 2009-05-16 23:42:17 UTC (rev 523) @@ -924,20 +924,11 @@ return 0; } -typedef struct penable { - uint16_t vendor_id; - uint16_t device_id; - int status; - const char *vendor_name; - const char *device_name; - int (*doit) (struct pci_dev *dev, const char *name); -} FLASH_ENABLE; - #define OK 0 #define NT 1 /* Not tested */ /* Please keep this list alphabetically sorted by vendor/device. */ -static const FLASH_ENABLE enables[] = { +const struct penable chipset_enables[] = { {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1014,6 +1005,8 @@ {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + + {}, }; void print_supported_chipsets(void) @@ -1022,11 +1015,13 @@ printf("\nSupported chipsets:\n\n"); - for (i = 0; i < ARRAY_SIZE(enables); i++) - printf("%s %s [%04x:%04x]%s\n", enables[i].vendor_name, - enables[i].device_name, enables[i].vendor_id, - enables[i].device_id, - (enables[i].status == OK) ? "" : " (untested)"); + for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { + printf("%s %s [%04x:%04x]%s\n", chipset_enables[i].vendor_name, + chipset_enables[i].device_name, + chipset_enables[i].vendor_id, + chipset_enables[i].device_id, + (chipset_enables[i].status == OK) ? "" : " (untested)"); + } } int chipset_flash_enable(void) @@ -1036,17 +1031,20 @@ int i; /* Now let's try to find the chipset we have... */ - for (i = 0; i < ARRAY_SIZE(enables); i++) { - dev = pci_dev_find(enables[i].vendor_id, enables[i].device_id); + for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { + dev = pci_dev_find(chipset_enables[i].vendor_id, + chipset_enables[i].device_id); if (dev) break; } if (dev) { printf("Found chipset \"%s %s\", enabling flash write... ", - enables[i].vendor_name, enables[i].device_name); + chipset_enables[i].vendor_name, + chipset_enables[i].device_name); - ret = enables[i].doit(dev, enables[i].device_name); + ret = chipset_enables[i].doit(dev, + chipset_enables[i].device_name); if (ret) printf("FAILED!\n"); else Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-16 22:36:00 UTC (rev 522) +++ trunk/flash.h 2009-05-16 23:42:17 UTC (rev 523) @@ -168,6 +168,52 @@ extern struct flashchip flashchips[]; +struct penable { + uint16_t vendor_id; + uint16_t device_id; + int status; + const char *vendor_name; + const char *device_name; + int (*doit) (struct pci_dev *dev, const char *name); +}; + +extern const struct penable chipset_enables[]; + +struct board_pciid_enable { + /* Any device, but make it sensible, like the ISA bridge. */ + uint16_t first_vendor; + uint16_t first_device; + uint16_t first_card_vendor; + uint16_t first_card_device; + + /* Any device, but make it sensible, like + * the host bridge. May be NULL. + */ + uint16_t second_vendor; + uint16_t second_device; + uint16_t second_card_vendor; + uint16_t second_card_device; + + /* The vendor / part name from the coreboot table. */ + const char *lb_vendor; + const char *lb_part; + + const char *vendor_name; + const char *board_name; + + int (*enable) (const char *name); +}; + +extern struct board_pciid_enable board_pciid_enables[]; + +struct board_info { + const char *vendor; + const char *name; +}; + +extern const struct board_info boards_ok[]; +extern const struct board_info boards_bad[]; + /* * Please keep this list sorted alphabetically by manufacturer. The first * entry of each section should be the manufacturer ID, followed by the Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-16 22:36:00 UTC (rev 522) +++ trunk/flashrom.c 2009-05-16 23:42:17 UTC (rev 523) @@ -399,6 +399,7 @@ int option_index = 0; int force = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int list_supported = 0; int ret = 0, i; static struct option long_options[] = { @@ -491,13 +492,7 @@ find_romentry(tempstr); break; case 'L': - print_supported_chips(); - print_supported_chipsets(); - print_supported_boards(); - printf("\nSupported PCI devices flashrom can use " - "as programmer:\n\n"); - print_supported_pcidevs(nics_3com); - exit(0); + list_supported = 1; break; case 'p': if (strncmp(optarg, "internal", 8) == 0) { @@ -524,6 +519,16 @@ } } + if (list_supported) { + print_supported_chips(); + print_supported_chipsets(); + print_supported_boards(); + printf("\nSupported PCI devices flashrom can use " + "as programmer:\n\n"); + print_supported_pcidevs(nics_3com); + exit(0); + } + if (read_it && write_it) { printf("Error: -r and -w are mutually exclusive.\n"); usage(argv[0]);

1 0

build service results for r4290
by coreboot information 17 May '09

17 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4290 to the coreboot repository. This caused the following changes: Change Log: This patch implements a "flash friendly" value for initialized areas of flash. It makes the write part of flashrom dramatically faster with small payloads like filo; and it also eliminates unnecessary wear on flash by not writing zeros (it's unlikely this really matters; let me know next time you flash a BIOS flash 100,000 times!). More importantly, it allows for future partial flash upgrades with cbfs. Note that uninitialized_flash_value is a global that can, if we ever need it, be set by an argument in main. Assuming we ever see a flash where the "erased" value is 0, not 0xff. At the same time, "erased" value has been "1" on every EEPROM or FLASH I've used for some time now. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4290&device=mew-am&vendor=… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

proposed cbfs change for 'unitialized' flash
by ron minnich 17 May '09

17 May '09

attached. ron

2 4

[v2] r4290 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 17 May '09

17 May '09

Author: rminnich Date: 2009-05-17 01:05:20 +0200 (Sun, 17 May 2009) New Revision: 4290 Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.h trunk/coreboot-v2/util/cbfstool/util.c Log: This patch implements a "flash friendly" value for initialized areas of flash. It makes the write part of flashrom dramatically faster with small payloads like filo; and it also eliminates unnecessary wear on flash by not writing zeros (it's unlikely this really matters; let me know next time you flash a BIOS flash 100,000 times!). More importantly, it allows for future partial flash upgrades with cbfs. Note that uninitialized_flash_value is a global that can, if we ever need it, be set by an argument in main. Assuming we ever see a flash where the "erased" value is 0, not 0xff. At the same time, "erased" value has been "1" on every EEPROM or FLASH I've used for some time now. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.h =================================================================== --- trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-05-15 18:02:25 UTC (rev 4289) +++ trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-05-16 23:05:20 UTC (rev 4290) @@ -56,6 +56,7 @@ /* Function prototypes */ /* util.c */ +void flashinit(void *ptr, size_t len); int open_rom(struct rom *rom, const char *filename); int create_rom(struct rom *rom, const unsigned char *filename, int size, const char *bootblockname, int bootblocksize, Modified: trunk/coreboot-v2/util/cbfstool/util.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/util.c 2009-05-15 18:02:25 UTC (rev 4289) +++ trunk/coreboot-v2/util/cbfstool/util.c 2009-05-16 23:05:20 UTC (rev 4290) @@ -25,6 +25,13 @@ #include <sys/mman.h> #include "cbfstool.h" +int uninitialized_flash_value = 0xff; + +void flashinit(void *ptr, size_t len) +{ + memset(ptr, uninitialized_flash_value, len); +} + int get_size(const char *size) { char *next; @@ -203,6 +210,9 @@ return -1; } + /* mmap'ed pages are by default zero-filled. Fix that. */ + flashinit(rom->ptr, romsize); + /* This is a pointer to the header for easy access */ rom->header = (struct cbfs_header *) ROM_PTR(rom, rom->size - 16 - bootblocksize - sizeof(struct cbfs_header));

1 0

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coreboot May 2009