coreboot May 2009

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[flashrom] r533 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: uwe Date: 2009-05-18 23:56:16 +0200 (Mon, 18 May 2009) New Revision: 533 Modified: trunk/board_enable.c Log: Drop duplicate Tyan S2498 (Tomcat K7M) entry in the board list (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-18 15:31:10 UTC (rev 532) +++ trunk/board_enable.c 2009-05-18 21:56:16 UTC (rev 533) @@ -231,7 +231,7 @@ /** * Suited for: * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan Tomcat K7M: AMD Geode NX + VIA KM400 + VT8237. + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. */ static int board_asus_a7v8x_mx(const char *name) { @@ -666,39 +666,39 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, - {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, - {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, - {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "BioStar", "P4M80-M4", board_biostar_p4m80_m4}, - {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, - {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, - {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, - {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, - {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, - {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4385, 0x1458, 0x4385, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, - {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, "gigabyte", "ma790fx-dq6", "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, - {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable}, - {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM", "x3455", board_ibm_x3455}, - {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi}, - {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e}, - /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ - {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, - {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, - {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "K8N Neo3", w83627thf_gpio4_4_raise_4e}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "K8T Neo2", w83627thf_gpio4_4_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "KT4V", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8-MX SE", board_asus_a7v8x_mx}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, + {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, + {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "BioStar", "P4M80-M4", board_biostar_p4m80_m4}, + {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, + {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, + {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, + {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", board_biostar_p4m80_m4}, + {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, + {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, + {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4385, 0x1458, 0x4385, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, /* SB600 LPC, RD790 North. Neither are specific to the GA-MA790FX-DQ6. The coreboot ID is here to be able to trigger the board enable more easily. */ - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "Tomcat K7M", board_asus_a7v8x_mx}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, - {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash}, - { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ + {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, "gigabyte", "ma790fx-dq6", "GIGABYTE", "GA-MA790FX-DQ6", it87xx_probe_spi_flash}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP", "DL145 G3", board_hp_dl145_g3_enable}, + {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM", "x3455", board_ibm_x3455}, + {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel", "D201GLY", wbsio_check_for_spi}, + {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL", "DK8-HTX", w83627hf_gpio24_raise_2e}, + /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ + {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, + {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, + {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "K8N Neo3", w83627thf_gpio4_4_raise_4e}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "K8T Neo2", w83627thf_gpio4_4_raise_2e}, + {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "KT4V", board_msi_kt4v}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, + {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, + {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, + {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash}, + { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ }; /* Please keep this list alphabetically ordered by vendor/board. */ @@ -741,7 +741,6 @@ { "Thomson", "IP1000", }, { "T-Online", "S-100", }, { "Tyan", "S1846", }, - { "Tyan", "S2498 (Tomcat K7M)", }, { "Tyan", "S2881", }, { "Tyan", "S2882", }, { "Tyan", "S2882-D", },

1 0

[PATCH] Table code cleanup
by Myles Watson 18 May '09

18 May '09

I didn't understand what was going on in tables.c, and it seemed a little fragile. These three patches try to help that out. I would only recommend the first two, but all three is closer to maintaining the functionality we had. When you're reviewing, it will be helpful to note that rom_tables_* == LOW_TABLES, high_tables_* == HIGH_TABLES, and low_tables== coreboot-specific very low tables. These patches are abuild tested and boot tested on Tyan s2892, qemu, and SimNOW. tables.diff: Add comments. Remove ACPI-specific code. Align low_table_end after gdt (so it matches high_table_end). Correct "New low_table_end..." line in coreboot_table.c. high_low.diff: Factor out common code for writing tables. both.diff: If we need to have the tables written both times we can do something like this. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Re: [coreboot] Minimum RAM requirements for coreboot (under Qemu)
by bifferos 18 May '09

18 May '09

Hi Ron, I appreciate that this is perhaps not a use you expect Coreboot to be put to, however the following devices all use RDC x86-compatible SoCs and so are theoretically capable of running coreboot + various payloads: Airlink 101 AR525W (router) Edimax BR-6216Mg (router) Gemtek WRTR-137G (router) Longshine LCS-WR-2114M (router) Sitecom WL-153 (router) Sitecom WL-176 (router) Linksys WRT54GR (router) MGB100 (wireless NAS) Bifferboard (NAS) <--- My main interest There are many more. They use either R8610, R3211, or S3282 CPUs and have 486SX instruction set, clocked around 133MHz and generally come with 32MB RAM + 1-4MB flash. The chips have OHCI/EHCI controllers and 10/100 ethernet built-in. I think it makes sense to use the Coreboot payload system (if not Coreboot itself) to extend the bootloaders with extra functionality. One example is USB boot, another is PXE. We might be able to use the payloads as-is for many of these devices. Kind regards, Biff. --- On Sun, 17/5/09, ron minnich <rminnich(a)gmail.com> wrote: > From: ron minnich <rminnich(a)gmail.com> > Subject: Re: [coreboot] Minimum RAM requirements for coreboot (under Qemu) > To: "bifferos" <bifferos(a)yahoo.co.uk> > Cc: coreboot(a)coreboot.org > Date: Sunday, 17 May, 2009, 6:42 PM > On Sun, May 17, 2009 at 8:04 AM, > bifferos <bifferos(a)yahoo.co.uk> > wrote: > > > So no surprise that it doesn't work, but how/where do > I change > > these values? > > > > It's hard to get a machine with that little memory any > more. I think > that's the reason for the high number. > > I'll take a look today or tomorrow unless someone beats me > to it. > Sorry for the inconvenience! > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

3 8

[flashrom] r532 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: uwe Date: 2009-05-18 17:31:10 +0200 (Mon, 18 May 2009) New Revision: 532 Modified: trunk/board_enable.c Log: Add Tyan S2891/S2892/S2895 as supported without special write-enables being required. Thanks Myles Watson <mylesgw(a)gmail.com> for the report. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-17 23:12:17 UTC (rev 531) +++ trunk/board_enable.c 2009-05-18 15:31:10 UTC (rev 532) @@ -745,6 +745,9 @@ { "Tyan", "S2881", }, { "Tyan", "S2882", }, { "Tyan", "S2882-D", }, + { "Tyan", "S2891", }, + { "Tyan", "S2892", }, + { "Tyan", "S2895", }, { "Tyan", "S3095", }, { "Tyan", "S5180", }, { "Tyan", "S5191", },

1 0

Corruption issue in build_lb_mem()?
by David Hendricks 18 May '09

18 May '09

I am having some difficulty booting a FILO (r95) payload using coreboot-v2 (r4291). My target is a via vb7001g, but I'm using the epia-cn target since the boards are practically identical afaict. The only hardware change I've made is using a 2MB flash chip. I was able to boot some simple payloads using coreboot-v2 r4121, too. So anyway, after doing some tracing using printk's, it seems the problem occurs in build_lb_mem() in arch/i386/boot/coreboot_tables.c when it attempts to record where memory ranges live. Added print output in build_lb_mem(): printk_debug("%s: entered\n", __func__); /* Record where the lb memory ranges will live */ mem = lb_memory(head); printk_debug("%s: mem: 0x%p, mem->size = 0x%x\n", __func__, mem, mem->size); printk_debug("\tmem->size: 0x%x\n", mem->size); mem_ranges = mem; printk_debug("\tmem_ranges->size: 0x%x\n", mem_ranges->size); lb_memory() is short, so I'll print the full thing (I only added the two printk's, the rest is unmodified): struct lb_memory *lb_memory(struct lb_header *header) { struct lb_record *rec; struct lb_memory *mem; printk_debug("%s: entered, header: 0x%p", __func__, header); rec = lb_new_record(header); mem = (struct lb_memory *)rec; mem->tag = LB_TAG_MEMORY; mem->size = sizeof(*mem); printk_debug("%s: exiting, mem: 0x%p, mem->size = 0x%x\n", __func__, mem, mem->size); return mem; } ...and finally, a snippet from serial output: build_lb_mem: entered, head: 0x3fff0800 lb_memory: entered, header: 0x3fff0800 lb_memory: exiting, mem: 0x3fff0817, mem->size = 0x8 build_lb_mem: mem: 0x3fff0817, mem->size = 0xffffffff mem->size: 0xffffffff mem_ranges->size: 0xffffffff So that's pretty weird. But what's also weird is that if I set mem->size manually after it returns from lb_memory() and then set mem_ranges, it somehow gets set back to 0xffffffff. Here's build_lb_mem() with even more printk's added to show that: printk_debug("%s: entered, head: 0x%p\n", __func__); /* Record where the lb memory ranges will live */ mem = lb_memory(head); printk_debug("%s: mem: 0x%p, mem->size = 0x%x\n", __func__, mem, mem->size); mem->size = 8; /* FIXME: stupid idea */ printk_debug("\tmem->size (after being manually set): 0x%x\n", mem->size); mem_ranges = mem; printk_debug("\tmem->size after setting mem_ranges: 0x%x\n", mem->size); printk_debug("\tmem_ranges->size: 0x%x\n", mem_ranges->size); ...and the serial console output: build_lb_mem: entered, head: 0x3fff0800 lb_memory: entered, header: 0x3fff0800 lb_memory: exiting, mem: 0x3fff0817, mem->size = 0x8 build_lb_mem: mem: 0x3fff0817, mem->size = 0xffffffff mem->size (after being manually set): 0x8 mem->size after setting mem_ranges: 0xffffffff mem_ranges->size: 0xffffffff Any ideas on what could be happening or where to go next for debugging?

2 1

HP DL145G3 - BuildBot
by samuel 18 May '09

18 May '09

Dear list(s), This is the final patch that got everything working for me with the HP dl145g3. I would like to remind you that this firmware enables the hardware virtualization on the AMD cpu's on the machine. That feature was explicitly disabled by the factory BIOS. Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS) than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read config space of a device that is actually not present. Because SeaBIOS does not support AHCI SATA it can not start the bootable drive of the machine so i had to add filo to seabios to manage booting: ./cbfstool coreboot.rom add-payload filo.elf img/FILO Signed-off-by: Samuel Verstraete (samuel.verstraete(a)gmail.com) As the machine is working wonderfull now I would say that the goal of the "contest [1]" was achieved. Hereby I would like to thank everyone that helped me with this, especially Mondrian Nuessle (for the initial patches), Myles Watson (for the many hours in chat to help me with loading the vga rom, cleaning up the patches and fiddling with the payloads) and Anton Borisov (for extracting the vga rom for me). In the name of the Xfce development team I would like to award the 3 of you with each 33 euro for all the work you have done. Can you guys please contact me so we can transfer the money to you? In general I would like to thank all of the Coreboot developers and users. You were all very responsive to help me out with this machine. The machine will ship on friday to sweden where it will find it's final destination in the datacenter of http://www.su.se . From then on it will be building snapshots for Xfce. [1] http://www.coreboot.org/pipermail/coreboot/2009-March/045954.html Cheers, Samuel aka ElAngelo

10 15

[patch] flashrom: resending my patch about SPI/LPC conflicts
by Bao, Zheng 18 May '09

18 May '09

Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> This patch is about flashrom running on dbm690t. It was sent several months ago and hasn't got any response yet. Now it deals with 3 problems. 1. Fix the bug that the flashrom would hang if there is not SPI chip. A timeout detection was added. 2. We only access LPC ROM if we boot via LPC ROM. And only SPI ROM if we boot via SPI ROM. Doing crossly is not allowed. Anybody has better idea? 3. When we read/write SPI, we use memory read/write instead of sending SPI command. Joe

4 19

Re: [coreboot] [v2] r4238 - in trunk/coreboot-v2/src/northbridge: amd/amdfam10 amd/gx1 amd/gx2 amd/lx intel/e7501 intel/e7520 intel/e7525 intel/i3100 intel/i440bx intel/i82810 intel/i82830 intel/i855gme intel/i855pm via/cn700 via/cx700 via/vt8601 via/vt8623
by Kevin O'Connor 18 May '09

18 May '09

On Thu, Apr 30, 2009 at 03:58:42PM +0200, svn(a)coreboot.org wrote: > Author: stepan > Date: 2009-04-30 15:58:42 +0200 (Thu, 30 Apr 2009) > New Revision: 4238 [...] > Modified: trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c > =================================================================== > --- trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 12:53:00 UTC (rev 4237) > +++ trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c 2009-04-30 13:58:42 UTC (rev 4238) > @@ -163,6 +163,12 @@ > return tolm; > } > > +#if HAVE_HIGH_TABLES==1 > +/* maximum size of high tables in KB */ > +#define HIGH_TABLES_SIZE 64 > +extern uint64_t high_tables_base, high_tables_size; > +#endif > + > static void pci_domain_set_resources(device_t dev) > { > /* The order is important to find the correct RAM size. */ > @@ -199,6 +205,13 @@ > /* The PCI hole does does not overlap the memory. */ > tolmk = tomk; > } > + > +#if HAVE_HIGH_TABLES == 1 > + high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; > + high_tables_size = HIGH_TABLES_SIZE* 1024; > + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); > +#endif > + The above is not correct. It places the high tables over the vga memory. -Kevin

4 5

[flashrom] r531 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: uwe Date: 2009-05-18 01:12:17 +0200 (Mon, 18 May 2009) New Revision: 531 Modified: trunk/flash.h trunk/flashrom.c trunk/internal.c trunk/nic3com.c trunk/satasii.c Log: Factor out fallback_map/unmap, most external programmers don't need and special handling here (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-17 22:58:41 UTC (rev 530) +++ trunk/flash.h 2009-05-17 23:12:17 UTC (rev 531) @@ -629,6 +629,8 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void *fallback_map(const char *descr, unsigned long phys_addr, size_t len); +void fallback_unmap(void *virt_addr, size_t len); void fallback_chip_writew(uint16_t val, chipaddr addr); void fallback_chip_writel(uint32_t val, chipaddr addr); uint16_t fallback_chip_readw(const chipaddr addr); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-17 22:58:41 UTC (rev 530) +++ trunk/flashrom.c 2009-05-17 23:12:17 UTC (rev 531) @@ -64,8 +64,8 @@ { .init = nic3com_init, .shutdown = nic3com_shutdown, - .map_flash_region = nic3com_map, - .unmap_flash_region = nic3com_unmap, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -77,8 +77,8 @@ { .init = satasii_init, .shutdown = satasii_shutdown, - .map_flash_region = satasii_map, - .unmap_flash_region = satasii_unmap, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, Modified: trunk/internal.c =================================================================== --- trunk/internal.c 2009-05-17 22:58:41 UTC (rev 530) +++ trunk/internal.c 2009-05-17 23:12:17 UTC (rev 531) @@ -195,6 +195,17 @@ return *(volatile uint32_t *) addr; } +/* Fallback map() for programmers which don't need special handling */ +void *fallback_map(const char *descr, unsigned long phys_addr, size_t len) +{ + return 0; +} + +/* Fallback unmap() for programmers which don't need special handling */ +void fallback_unmap(void *virt_addr, size_t len) +{ +} + /* Little-endian fallback for drivers not supporting 16 bit accesses */ void fallback_chip_writew(uint16_t val, chipaddr addr) { Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-17 22:58:41 UTC (rev 530) +++ trunk/nic3com.c 2009-05-17 23:12:17 UTC (rev 531) @@ -102,15 +102,6 @@ return 0; } -void *nic3com_map(const char *descr, unsigned long phys_addr, size_t len) -{ - return 0; -} - -void nic3com_unmap(void *virt_addr, size_t len) -{ -} - void nic3com_chip_writeb(uint8_t val, chipaddr addr) { OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-05-17 22:58:41 UTC (rev 530) +++ trunk/satasii.c 2009-05-17 23:12:17 UTC (rev 531) @@ -80,15 +80,6 @@ return 0; } -void *satasii_map(const char *descr, unsigned long phys_addr, size_t len) -{ - return 0; -} - -void satasii_unmap(void *virt_addr, size_t len) -{ -} - void satasii_chip_writeb(uint8_t val, chipaddr addr) { uint32_t ctrl_reg, data_reg;

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[flashrom] r530 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: uwe Date: 2009-05-18 00:58:41 +0200 (Mon, 18 May 2009) New Revision: 530 Added: trunk/satasii.c Removed: trunk/sata_sii.c Modified: trunk/Makefile Log: Rename sata_sii.c to satasii.c for consistency (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-17 22:57:34 UTC (rev 529) +++ trunk/Makefile 2009-05-17 22:58:41 UTC (rev 530) @@ -33,7 +33,7 @@ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - dummyflasher.o pcidev.o nic3com.o sata_sii.o + dummyflasher.o pcidev.o nic3com.o satasii.o all: pciutils dep $(PROGRAM) Deleted: trunk/sata_sii.c =================================================================== --- trunk/sata_sii.c 2009-05-17 22:57:34 UTC (rev 529) +++ trunk/sata_sii.c 2009-05-17 22:58:41 UTC (rev 530) @@ -1,124 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ - -#include <stdlib.h> -#include <string.h> -#include <fcntl.h> -#include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> -#include "flash.h" - -#define PCI_VENDOR_ID_SII 0x1095 - -uint8_t *sii_bar; -uint16_t id; - -struct pcidev_status satas_sii[] = { - {0x1095, 0x0680, PCI_NT, "Silicon Image", "PCI0680 Ultra ATA-133 Host Controller"}, - {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"}, - {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, - {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, - {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, - - {}, -}; - -int satasii_init(void) -{ - uint32_t addr; - uint16_t reg_offset; - - get_io_perms(); - - pcidev_init(PCI_VENDOR_ID_SII, satas_sii); - id = pcidev_dev->device_id; - - if ((id == 0x3132) || (id == 0x3124)) { - addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07; - reg_offset = 0x70; - } else { - addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07; - reg_offset = 0x50; - } - - sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; - - /* Check if ROM cycle are OK. */ - if (!(mmio_readl(sii_bar)) & (1 << 26)) - printf("Warning: Flash seems unconnected\n"); - - return 0; -} - -int satasii_shutdown(void) -{ - free(pcidev_bdf); - pci_cleanup(pacc); -#if defined(__FreeBSD__) || defined(__DragonFly__) - close(io_fd); -#endif - return 0; -} - -void *satasii_map(const char *descr, unsigned long phys_addr, size_t len) -{ - return 0; -} - -void satasii_unmap(void *virt_addr, size_t len) -{ -} - -void satasii_chip_writeb(uint8_t val, chipaddr addr) -{ - uint32_t ctrl_reg, data_reg; - - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; - - /* Mask out unused/reserved bits, set writes and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); - - while (mmio_readl(sii_bar) & (1 << 25)) ; -} - -uint8_t satasii_chip_readb(const chipaddr addr) -{ - uint32_t ctrl_reg; - - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; - - /* Mask out unused/reserved bits, set reads and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - - mmio_writel(ctrl_reg, sii_bar); - - while (mmio_readl(sii_bar) & (1 << 25)) ; - - return (mmio_readl(sii_bar + 4)) & 0xff; -} Copied: trunk/satasii.c (from rev 529, trunk/sata_sii.c) =================================================================== --- trunk/satasii.c (rev 0) +++ trunk/satasii.c 2009-05-17 22:58:41 UTC (rev 530) @@ -0,0 +1,124 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ + +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <errno.h> +#include "flash.h" + +#define PCI_VENDOR_ID_SII 0x1095 + +uint8_t *sii_bar; +uint16_t id; + +struct pcidev_status satas_sii[] = { + {0x1095, 0x0680, PCI_NT, "Silicon Image", "PCI0680 Ultra ATA-133 Host Controller"}, + {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"}, + {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, + {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, + {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, + + {}, +}; + +int satasii_init(void) +{ + uint32_t addr; + uint16_t reg_offset; + + get_io_perms(); + + pcidev_init(PCI_VENDOR_ID_SII, satas_sii); + id = pcidev_dev->device_id; + + if ((id == 0x3132) || (id == 0x3124)) { + addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07; + reg_offset = 0x70; + } else { + addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07; + reg_offset = 0x50; + } + + sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; + + /* Check if ROM cycle are OK. */ + if (!(mmio_readl(sii_bar)) & (1 << 26)) + printf("Warning: Flash seems unconnected\n"); + + return 0; +} + +int satasii_shutdown(void) +{ + free(pcidev_bdf); + pci_cleanup(pacc); +#if defined(__FreeBSD__) || defined(__DragonFly__) + close(io_fd); +#endif + return 0; +} + +void *satasii_map(const char *descr, unsigned long phys_addr, size_t len) +{ + return 0; +} + +void satasii_unmap(void *virt_addr, size_t len) +{ +} + +void satasii_chip_writeb(uint8_t val, chipaddr addr) +{ + uint32_t ctrl_reg, data_reg; + + while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + + /* Mask out unused/reserved bits, set writes and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); + + data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; + mmio_writel(data_reg, (sii_bar + 4)); + mmio_writel(ctrl_reg, sii_bar); + + while (mmio_readl(sii_bar) & (1 << 25)) ; +} + +uint8_t satasii_chip_readb(const chipaddr addr) +{ + uint32_t ctrl_reg; + + while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + + /* Mask out unused/reserved bits, set reads and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); + + mmio_writel(ctrl_reg, sii_bar); + + while (mmio_readl(sii_bar) & (1 << 25)) ; + + return (mmio_readl(sii_bar + 4)) & 0xff; +} Property changes on: trunk/satasii.c ___________________________________________________________________ Added: svn:mergeinfo +

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coreboot May 2009