coreboot May 2009

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[flashrom] r529 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: uwe Date: 2009-05-18 00:57:34 +0200 (Mon, 18 May 2009) New Revision: 529 Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/pcidev.c trunk/physmap.c trunk/sata_sii.c Log: Various smaller flashrom improvements: - Document new 'satasii' programmer in -L output and manpage. - Drop PCI_IO_BASE_ADDRESS, pci.h has such #defines already. - Beautify flashrom output and make it more consistent. - Same for the 'make' output (reordered some $CC parameters). Build-tested on i386, shouldn't break any builds, I think. - Some variable renaming and other cosmetic fixes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/Makefile 2009-05-17 22:57:34 UTC (rev 529) @@ -46,7 +46,7 @@ $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) flashrom.o: flashrom.c - $(CC) -c $(CFLAGS) $(SVNDEF) $(CPPFLAGS) $< -o $@ + $(CC) $(CFLAGS) $(CPPFLAGS) -c -o $@ $< $(SVNDEF) clean: rm -f $(PROGRAM) *.o Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/flash.h 2009-05-17 22:57:34 UTC (rev 529) @@ -560,7 +560,6 @@ /* pcidev.c */ #define PCI_OK 0 #define PCI_NT 1 /* Not tested */ -#define PCI_IO_BASE_ADDRESS 0x10 extern uint32_t io_base_addr; extern struct pci_access *pacc; @@ -670,7 +669,6 @@ uint8_t satasii_chip_readb(const chipaddr addr); extern struct pcidev_status satas_sii[]; - /* flashrom.c */ extern int verbose; #define printf_debug(x...) { if (verbose) printf(x); } Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/flashrom.8 2009-05-17 22:57:34 UTC (rev 529) @@ -147,6 +147,8 @@ Example: .B "flashrom -p nic3com=05:04.0" .sp +.BR "* satasii" " (for flash ROMs on Silicon Image SATA/IDE controller cards)" +.sp .BR "* dummy" " (just prints all operations and accesses)" .TP .B "\-h, \-\-help" Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/flashrom.c 2009-05-17 22:57:34 UTC (rev 529) @@ -543,6 +543,7 @@ printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); print_supported_pcidevs(nics_3com); + print_supported_pcidevs(satas_sii); exit(0); } Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/pcidev.c 2009-05-17 22:57:34 UTC (rev 529) @@ -42,16 +42,16 @@ continue; /* Don't use dev->base_addr[0], won't work on older libpci. */ - addr = pci_read_long(dev, PCI_IO_BASE_ADDRESS) & ~0x03; + addr = pci_read_long(dev, PCI_BASE_ADDRESS_0) & ~0x03; - printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x)\n", + printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, dev->func); if (devs[i].status == PCI_NT) { - printf("===\nThis PCI device is UNTESTED. Please email " - "a report including the 'flashrom -p xxxxxx'\n" - "output to flashrom(a)coreboot.org if it works " + printf("===\nThis PCI device is UNTESTED. Please " + "report the 'flashrom -p xxxx' output \n" + "to flashrom(a)coreboot.org if it works " "for you. Thank you for your help!\n===\n"); } @@ -98,7 +98,7 @@ exit(1); } else if (found > 1) { fprintf(stderr, "Error: Multiple supported PCI devices found. " - "Please use 'flashrom -p xxxxxx=bb:dd.f' \n" + "Use 'flashrom -p xxxx=bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1); Modified: trunk/physmap.c =================================================================== --- trunk/physmap.c 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/physmap.c 2009-05-17 22:57:34 UTC (rev 529) @@ -81,18 +81,18 @@ void *physmap(const char *descr, unsigned long phys_addr, size_t len) { if (len == 0) { - printf_debug("Not mapping %s, zero size at 0x%08lx\n", - descr, phys_addr); + printf_debug("Not mapping %s, zero size at 0x%08lx.\n", + descr, phys_addr); return NULL; } if ((getpagesize() - 1) & len) { - fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx\n", + fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n", descr, phys_addr, (unsigned long)len); } if ((getpagesize() - 1) & phys_addr) { - fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx\n", + fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n", descr, (unsigned long)len, phys_addr); } Modified: trunk/sata_sii.c =================================================================== --- trunk/sata_sii.c 2009-05-17 19:46:43 UTC (rev 528) +++ trunk/sata_sii.c 2009-05-17 22:57:34 UTC (rev 529) @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, , 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ @@ -39,6 +39,7 @@ {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, + {}, }; @@ -50,33 +51,27 @@ get_io_perms(); pcidev_init(PCI_VENDOR_ID_SII, satas_sii); - id = pcidev_dev->device_id; if ((id == 0x3132) || (id == 0x3124)) { - /* BAR 0, offset 0x70 */ - addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS) & ~0x07; + addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07; reg_offset = 0x70; } else { - /* BAR 5, offset 0x50 */ - addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS + (5 * 4)) & ~0x07; + addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07; reg_offset = 0x50; } - sii_bar = physmap("SATA SIL registers", addr, 0x100); - sii_bar += reg_offset; + sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; - /* check if rom cycle are OK */ - if (!(mmio_readl(sii_bar)) & (1 << 26)) { + /* Check if ROM cycle are OK. */ + if (!(mmio_readl(sii_bar)) & (1 << 26)) printf("Warning: Flash seems unconnected\n"); - } return 0; } int satasii_shutdown(void) { - free(pcidev_bdf); pci_cleanup(pacc); #if defined(__FreeBSD__) || defined(__DragonFly__) @@ -96,21 +91,19 @@ void satasii_chip_writeb(uint8_t val, chipaddr addr) { + uint32_t ctrl_reg, data_reg; - uint32_t ctrl_reg, addr_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; - /* Mask out unused/reserved bits, set writes and start transaction */ + /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - addr_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(addr_reg, (sii_bar + 4)); + data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; + mmio_writel(data_reg, (sii_bar + 4)); mmio_writel(ctrl_reg, sii_bar); while (mmio_readl(sii_bar) & (1 << 25)) ; - } uint8_t satasii_chip_readb(const chipaddr addr) @@ -119,13 +112,13 @@ while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; - /* Mask out unused/reserved bits, set reads and start transaction */ + /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); mmio_writel(ctrl_reg, sii_bar); - while ((mmio_readl(sii_bar)) & (1 << 25)) ; + while (mmio_readl(sii_bar) & (1 << 25)) ; return (mmio_readl(sii_bar + 4)) & 0xff; }

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build service results for r4291
by coreboot information 18 May '09

18 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4291 to the coreboot repository. This caused the following changes: Change Log: Add type field to memranges, and fill it from the source data. type field contains e820 type ids, which are used by coreboot and multiboot (the two source formats), so they can be used as-is. The MEMMAP_RAM_ONLY define is a way to allow a payload to opt for only having CB_MEM_RAM type fields, which might be helpful to support older payloads easily (just add the define, and it won't encounter "weird" fields) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4291&device=mew-am&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4291 - in trunk/payloads/libpayload: i386 include
by svn＠coreboot.org 18 May '09

18 May '09

Author: oxygene Date: 2009-05-17 22:36:45 +0200 (Sun, 17 May 2009) New Revision: 4291 Modified: trunk/payloads/libpayload/i386/coreboot.c trunk/payloads/libpayload/i386/multiboot.c trunk/payloads/libpayload/i386/sysinfo.c trunk/payloads/libpayload/include/sysinfo.h Log: Add type field to memranges, and fill it from the source data. type field contains e820 type ids, which are used by coreboot and multiboot (the two source formats), so they can be used as-is. The MEMMAP_RAM_ONLY define is a way to allow a payload to opt for only having CB_MEM_RAM type fields, which might be helpful to support older payloads easily (just add the define, and it won't encounter "weird" fields) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/libpayload/i386/coreboot.c =================================================================== --- trunk/payloads/libpayload/i386/coreboot.c 2009-05-16 23:05:20 UTC (rev 4290) +++ trunk/payloads/libpayload/i386/coreboot.c 2009-05-17 20:36:45 UTC (rev 4291) @@ -57,8 +57,10 @@ struct cb_memory_range *range = (struct cb_memory_range *)MEM_RANGE_PTR(mem, i); +#if MEMMAP_RAM_ONLY if (range->type != CB_MEM_RAM) continue; +#endif info->memrange[info->n_memranges].base = UNPACK_CB64(range->start); @@ -66,6 +68,8 @@ info->memrange[info->n_memranges].size = UNPACK_CB64(range->size); + info->memrange[info->n_memranges].type = range->type; + info->n_memranges++; } } Modified: trunk/payloads/libpayload/i386/multiboot.c =================================================================== --- trunk/payloads/libpayload/i386/multiboot.c 2009-05-16 23:05:20 UTC (rev 4290) +++ trunk/payloads/libpayload/i386/multiboot.c 2009-05-17 20:36:45 UTC (rev 4291) @@ -45,15 +45,20 @@ while(ptr < (start + table->mmap_length)) { struct multiboot_mmap *mmap = (struct multiboot_mmap *) ptr; +#if MEMMAP_RAM_ONLY /* 1 == normal RAM. Ignore everything else for now */ if (mmap->type == 1) { +#endif info->memrange[info->n_memranges].base = mmap->addr; info->memrange[info->n_memranges].size = mmap->length; + info->memrange[info->n_memranges].type = mmap->type; if (++info->n_memranges == SYSINFO_MAX_MEM_RANGES) return; +#if MEMMAP_RAM_ONLY } +#endif ptr += (mmap->size + sizeof(mmap->size)); } Modified: trunk/payloads/libpayload/i386/sysinfo.c =================================================================== --- trunk/payloads/libpayload/i386/sysinfo.c 2009-05-16 23:05:20 UTC (rev 4290) +++ trunk/payloads/libpayload/i386/sysinfo.c 2009-05-17 20:36:45 UTC (rev 4291) @@ -29,6 +29,7 @@ #include <libpayload-config.h> #include <libpayload.h> +#include <coreboot_tables.h> #include <multiboot_tables.h> /** @@ -63,9 +64,13 @@ if (!lib_sysinfo.n_memranges) { /* If we can't get a good memory range, use the default. */ lib_sysinfo.n_memranges = 2; + lib_sysinfo.memrange[0].base = 0; lib_sysinfo.memrange[0].size = 640 * 1024; + lib_sysinfo.memrange[0].type = CB_MEM_RAM; + lib_sysinfo.memrange[1].base = 1024 * 1024; lib_sysinfo.memrange[1].size = 31 * 1024 * 1024; + lib_sysinfo.memrange[1].type = CB_MEM_RAM; } } Modified: trunk/payloads/libpayload/include/sysinfo.h =================================================================== --- trunk/payloads/libpayload/include/sysinfo.h 2009-05-16 23:05:20 UTC (rev 4290) +++ trunk/payloads/libpayload/include/sysinfo.h 2009-05-17 20:36:45 UTC (rev 4291) @@ -42,6 +42,7 @@ struct memrange { unsigned long long base; unsigned long long size; + unsigned int type; } memrange[SYSINFO_MAX_MEM_RANGES]; struct cb_cmos_option_table *option_table;

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Re: [coreboot] FILO Compilation failure
by bifferos 18 May '09

18 May '09

S***, I have the worst luck - broken just 4 days ago, and I started looking at this 2 days later. Of course I assumed it was somehow my idiocy... Somebody's getting their memory ranges muddled up. Many thanks Jouni. Biff. --- On Sun, 17/5/09, Jouni Mettälä <jtmettala(a)gmail.com> wrote: > From: Jouni Mettälä <jtmettala(a)gmail.com> > Subject: Re: [coreboot] FILO Compilation failure > To: "bifferos" <bifferos(a)yahoo.co.uk> > Cc: coreboot(a)coreboot.org > Date: Sunday, 17 May, 2009, 12:26 PM > > > 2009/5/16 bifferos <bifferos(a)yahoo.co.uk> > > > > I've tried to build FILO following instructions at > > http://www.coreboot.org/FILO, > but it doesn't seem to work. Can anyone > > give any hints? 0.5 compiles fine. > > > > Here's what I typed (snipped the uninteresting info): > > > > wrt@cent:~/coreboot/filo$ svn co svn://coreboot.org/filo/trunk/filo > > Checked out external at revision 4289. > > Checked out revision 95. > > wrt@cent:~/coreboot/filo$ cd filo/ > > wrt@cent:~/coreboot/filo/filo$ cd libpayload/ > > wrt@cent:~/coreboot/filo/filo/libpayload$ make defconfig > > wrt@cent:~/coreboot/filo/filo/libpayload$ make > > wrt@cent:~/coreboot/filo/filo/libpayload$ make > DESTDIR=../build install > > wrt@cent:~/coreboot/filo/filo/libpayload$ cd .. > > wrt@cent:~/coreboot/filo/filo$ make menuconfig > > wrt@cent:~/coreboot/filo/filo$ make > > .... > > CC build/i386/context.o > > AS build/i386/switch.S.o > > CC build/i386/segment.o > > /home/wrt/coreboot/filo/filo/i386/segment.c: In function > 'relocate': > > /home/wrt/coreboot/filo/filo/i386/segment.c:77: error: > 'struct memrange' has no member named > 'type' > > make: *** > [/home/wrt/coreboot/filo/filo/build/i386/segment.o] Error 1 > > > > > > thanks, > > Biff. > Does revision 94 work? I am getting same error but > revision 94 works for me. > svn co svn://coreboot.org/filo/trunk/filo > -r 94 > > > > > -----Inline Attachment Follows----- > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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[flashrom] r528 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: ruik Date: 2009-05-17 21:46:43 +0200 (Sun, 17 May 2009) New Revision: 528 Added: trunk/sata_sii.c Log: This patch adds support for BIOS flashing on the all SiliconImage SATA controllers. It was easy because 1) flashrom has now nice API 2) documentation is public on the web site Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Don't forget to add a files. Because I do. Added: trunk/sata_sii.c =================================================================== --- trunk/sata_sii.c (rev 0) +++ trunk/sata_sii.c 2009-05-17 19:46:43 UTC (rev 528) @@ -0,0 +1,131 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, , 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ + +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <errno.h> +#include "flash.h" + +#define PCI_VENDOR_ID_SII 0x1095 + +uint8_t *sii_bar; +uint16_t id; + +struct pcidev_status satas_sii[] = { + {0x1095, 0x0680, PCI_NT, "Silicon Image", "PCI0680 Ultra ATA-133 Host Controller"}, + {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"}, + {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, + {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, + {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, + {}, +}; + +int satasii_init(void) +{ + uint32_t addr; + uint16_t reg_offset; + + get_io_perms(); + + pcidev_init(PCI_VENDOR_ID_SII, satas_sii); + + id = pcidev_dev->device_id; + + if ((id == 0x3132) || (id == 0x3124)) { + /* BAR 0, offset 0x70 */ + addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS) & ~0x07; + reg_offset = 0x70; + } else { + /* BAR 5, offset 0x50 */ + addr = pci_read_long(pcidev_dev, PCI_IO_BASE_ADDRESS + (5 * 4)) & ~0x07; + reg_offset = 0x50; + } + + sii_bar = physmap("SATA SIL registers", addr, 0x100); + sii_bar += reg_offset; + + /* check if rom cycle are OK */ + if (!(mmio_readl(sii_bar)) & (1 << 26)) { + printf("Warning: Flash seems unconnected\n"); + } + + return 0; +} + +int satasii_shutdown(void) +{ + + free(pcidev_bdf); + pci_cleanup(pacc); +#if defined(__FreeBSD__) || defined(__DragonFly__) + close(io_fd); +#endif + return 0; +} + +void *satasii_map(const char *descr, unsigned long phys_addr, size_t len) +{ + return 0; +} + +void satasii_unmap(void *virt_addr, size_t len) +{ +} + +void satasii_chip_writeb(uint8_t val, chipaddr addr) +{ + + uint32_t ctrl_reg, addr_reg; + + while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + + /* Mask out unused/reserved bits, set writes and start transaction */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); + + addr_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; + mmio_writel(addr_reg, (sii_bar + 4)); + mmio_writel(ctrl_reg, sii_bar); + + while (mmio_readl(sii_bar) & (1 << 25)) ; + +} + +uint8_t satasii_chip_readb(const chipaddr addr) +{ + uint32_t ctrl_reg; + + while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + + /* Mask out unused/reserved bits, set reads and start transaction */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); + + mmio_writel(ctrl_reg, sii_bar); + + while ((mmio_readl(sii_bar)) & (1 << 25)) ; + + return (mmio_readl(sii_bar + 4)) & 0xff; +}

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[PATCH] flashrom support for SiliconImage SATA controllers
by Rudolf Marek 18 May '09

18 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, This patch adds support for BIOS flashing on the all SiliconImage SATA controllers. It was easy because 1) flashrom has now nice API 2) documentation is public on the web site Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> PS: maybe we could write to that company and tell them. For Windows/Linux they force the customer to download freedos from sourceforge ;) There is also a file with a list of roms: AMD’s Am29F010B/Am29LV010B (1 Megabit) and Am29F040B (4 Megabit) AMD’s Am29LV400B (4 Megabit) variable sectors Atmel’s AT49BV512 (64KB), AT29LV010A (1 Megabit), and AT49LV040 (4 Megabit) SST’s 39SF010 (1 Megabit), 39VF010 (1 Megabit), 39VF020 (2 Megabit), 39SF020 (2 Megabit), and 39VF040 (4 Megabit). SANYO’s LE28C1001D (1 Megabit) WinBound’s 29EE011 (1 Megabit) and 29EE512 (64KB) STMicroelectronics M29F010B/ M29W010B (1 Megabit) STMicroelectronics M29W040B (4 Megabit) STMicroelectronics M29W400B (4 Megabit) variable sectors MXIC MX29LV040 (4 Megabit) PMC Pm39LV010(1Megabit) and PMC Pm39LV040 (4Megabit) Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkoQQC0ACgkQ3J9wPJqZRNXUOwCgruIU+Uk2s0YCYvrcEWqScfvO MyoAnRhIPohNEmz7SyIpkeq9d4n77NB2 =qk7V -----END PGP SIGNATURE-----

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[flashrom] r527 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: ruik Date: 2009-05-17 21:39:27 +0200 (Sun, 17 May 2009) New Revision: 527 Modified: trunk/Makefile trunk/flash.h trunk/flashrom.c trunk/pcidev.c Log: This patch adds support for BIOS flashing on the all SiliconImage SATA controllers. It was easy because 1) flashrom has now nice API 2) documentation is public on the web site Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-17 18:24:24 UTC (rev 526) +++ trunk/Makefile 2009-05-17 19:39:27 UTC (rev 527) @@ -33,7 +33,7 @@ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - dummyflasher.o pcidev.o nic3com.o + dummyflasher.o pcidev.o nic3com.o sata_sii.o all: pciutils dep $(PROGRAM) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-17 18:24:24 UTC (rev 526) +++ trunk/flash.h 2009-05-17 19:39:27 UTC (rev 527) @@ -83,6 +83,7 @@ #define PROGRAMMER_INTERNAL 0x00 #define PROGRAMMER_DUMMY 0x01 #define PROGRAMMER_NIC3COM 0x02 +#define PROGRAMMER_SATASII 0x03 struct programmer_entry { const char *vendor; @@ -559,6 +560,8 @@ /* pcidev.c */ #define PCI_OK 0 #define PCI_NT 1 /* Not tested */ +#define PCI_IO_BASE_ADDRESS 0x10 + extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_filter filter; @@ -658,6 +661,16 @@ uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +/* satasii.c */ +int satasii_init(void); +int satasii_shutdown(void); +void *satasii_map(const char *descr, unsigned long phys_addr, size_t len); +void satasii_unmap(void *virt_addr, size_t len); +void satasii_chip_writeb(uint8_t val, chipaddr addr); +uint8_t satasii_chip_readb(const chipaddr addr); +extern struct pcidev_status satas_sii[]; + + /* flashrom.c */ extern int verbose; #define printf_debug(x...) { if (verbose) printf(x); } Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-17 18:24:24 UTC (rev 526) +++ trunk/flashrom.c 2009-05-17 19:39:27 UTC (rev 527) @@ -74,6 +74,19 @@ .chip_writel = fallback_chip_writel, }, + { + .init = satasii_init, + .shutdown = satasii_shutdown, + .map_flash_region = satasii_map, + .unmap_flash_region = satasii_unmap, + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + }, + {}, }; @@ -503,6 +516,10 @@ programmer = PROGRAMMER_NIC3COM; if (optarg[7] == '=') pcidev_bdf = strdup(optarg + 8); + } else if (strncmp(optarg, "satasii", 7) == 0) { + programmer = PROGRAMMER_SATASII; + if (optarg[7] == '=') + pcidev_bdf = strdup(optarg + 8); } else { printf("Error: Unknown programmer.\n"); exit(1); Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-05-17 18:24:24 UTC (rev 526) +++ trunk/pcidev.c 2009-05-17 19:39:27 UTC (rev 527) @@ -26,8 +26,6 @@ #include <errno.h> #include "flash.h" -#define PCI_IO_BASE_ADDRESS 0x10 - uint32_t io_base_addr; struct pci_access *pacc; struct pci_filter filter;

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[flashrom] r526 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: ruik Date: 2009-05-17 20:24:24 +0200 (Sun, 17 May 2009) New Revision: 526 Modified: trunk/flashchips.c Log: Fix a quilt introduced bug in patch. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Self-acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-17 17:02:07 UTC (rev 525) +++ trunk/flashchips.c 2009-05-17 18:24:24 UTC (rev 526) @@ -1403,7 +1403,7 @@ .model_id = SST_39VF512, .total_size = 64, .page_size = 4096, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002,

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Minimum RAM requirements for coreboot (under Qemu)
by bifferos 18 May '09

18 May '09

Coreboot seems to require a minimum of 64MB to run, but I would like to port it to a platform with only 32MB. I noticed in: targets/emulation/qemu-x86/qemu-x86/normal/crt0.S there is the line: movl $0x4000000, %esp which I have changed to movl $0x2000000, %esp The boot now gets a lot further, but my payload (FILO) still doesn't appear to run. Is there some fundamental reason why platforms with <64MB are not supported? The last thing I see is: Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x03ff0000... done. Moving GDT to 0x3ff0400...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum f3df New low_table_end: 0x00000500 Now going to write high coreboot table at 0x03ff0800 rom_table_end = 0x03ff0800 Adjust low_table_end from 0x00000500 to 0x00001000 Adjust rom_table_end from 0x03ff0800 to 0x04000000 So no surprise that it doesn't work, but how/where do I change these values? thanks Biff.

3 2

[flashrom] r525 - trunk
by svn＠coreboot.org 18 May '09

18 May '09

Author: ruik Date: 2009-05-17 19:02:07 +0200 (Sun, 17 May 2009) New Revision: 525 Modified: trunk/flashchips.c Log: [PATCH] flashrom add PMC 39F010 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> [PATCH] tested SST39VF010 Self-ack is fine for test reports. Rudolf Marek wrote: > > Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-17 15:49:24 UTC (rev 524) +++ trunk/flashchips.c 2009-05-17 17:02:07 UTC (rev 525) @@ -1132,6 +1132,20 @@ { .vendor = "PMC", + .name = "Pm39LV010", + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_39F010, + .total_size = 128, + .page_size = 4096, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .erase = erase_chip_jedec, + .write = write_49f002, + .read = read_memmapped, + }, + + { + .vendor = "PMC", .name = "Pm49FL002", .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_49FL002, @@ -1389,7 +1403,7 @@ .model_id = SST_39VF512, .total_size = 64, .page_size = 4096, - .tested = TEST_OK_PREW, + .tested = TEST_UNTESTED, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002, @@ -1403,7 +1417,7 @@ .model_id = SST_39VF010, .total_size = 128, .page_size = 4096, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .erase = erase_chip_jedec, .write = write_49f002,

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coreboot May 2009