coreboot May 2009

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build service results for r4288
by coreboot information 15 May '09

15 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "mjones" checked in revision 4288 to the coreboot repository. This caused the following changes: Change Log: Update equivalent processor revision ID to load latest microcode patches and register setting for all FAM10 processors. This does not include new errata for FAM10 C2. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Vincent Lim (vincent.lim(a)amd.com) Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4288&device=mew-am&vendor=… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2][patch] use updated microcode patches from AMD
by Marc Jones 15 May '09

15 May '09

I no longer have a Fam10 test setup but it should just work. If someone can test it I would appreciate it. Update equivalent processor revision ID to load latest microcode patches. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Thanks, Marc -- http://marcjonesconsulting.com

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[v2] r4288 - in trunk/coreboot-v2/src: cpu/amd/model_10xxx mainboard/amd/serengeti_cheetah_fam10 mainboard/tyan/s2912_fam10 northbridge/amd/amdfam10 northbridge/amd/amdmct
by svn＠coreboot.org 15 May '09

15 May '09

Author: mjones Date: 2009-05-15 01:42:41 +0200 (Fri, 15 May 2009) New Revision: 4288 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h Log: Update equivalent processor revision ID to load latest microcode patches and register setting for all FAM10 processors. This does not include new errata for FAM10 C2. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Vincent Lim (vincent.lim(a)amd.com) Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2009-05-14 23:42:41 UTC (rev 4288) @@ -30,23 +30,23 @@ u32 mask_lo; u32 mask_hi; } fam10_msr_default[] = { - { TOP_MEM2, AMD_DR_ALL, AMD_PTYPE_ALL, + { TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF }, - { SYSCFG, AMD_DR_ALL, AMD_PTYPE_ALL, + { SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, 3 << 21, 0x00000000, 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/ - { HWCR, AMD_DR_ALL, AMD_PTYPE_ALL, + { HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL, 1 << 4, 0x00000000, 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */ - { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, + { MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xF << 19, 0x00000000, 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, + { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR, 0x00000000, 0x00000004, 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ @@ -54,7 +54,7 @@ 0x00000000, 0x00000000, 0x00000000, 0x00000C00 }, /* Errata 326 */ - { NB_CFG, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 0x00000000, 1 << 22, 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */ @@ -62,15 +62,15 @@ 1 << 29, 0x00000000, 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, + { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL, 1 << 24, 0x00000000, 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ - { BU_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, + { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL, 1 << 21, 0x00000000, 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */ @@ -79,11 +79,11 @@ 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */ /* CPUID_EXT_FEATURES */ - { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, + { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC, 1 << 28, 0x00000000, 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */ - { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC, + { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC, 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ }; @@ -103,7 +103,7 @@ /* Function 0 - HT Config */ - { 0, 0x68, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config, [14:13] BufPriRel = 2h [11] RspPassPW set, [22:21] DsNpReqLmt = 10b */ @@ -112,20 +112,20 @@ { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */ - { 0, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xC4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ - { 0, 0xE4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */ /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x0000C000, 0x0000E000 }, /* [15:13] ForceFullT0 = 110b */ /* Function 1 - Map Init */ @@ -137,25 +137,25 @@ * Array MCA errors. BKDG Doc #3116 Rev 1.07 */ - { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0xFFFFFFFF }, /* Clear map */ - { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */ - { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL, + { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0xFFFFFFFF }, /* Clear map */ /* Function 2 - DRAM Controller */ /* Function 3 - Misc. Control */ - { 3, 0x40, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ - { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, [27] NbMcaToMstCpuEn = 1, [25] DisPciCfgCpuErrRsp = 1, @@ -167,42 +167,42 @@ [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ - { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00018052, 0x700780F7 }, /* Errata 281 Workaround */ { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00010094, 0x700780F7 }, - { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x60018051, 0x700780F7 }, - { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00041153, 0x777777F7 }, - { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x61221151, 0x777777F7 }, - { 3, 0x74, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00080101, 0x000F7777 }, - { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00090914, 0x707FFF1F }, /* Errata 281 Workaround */ { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1), AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F }, - { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00070814, 0x007FFF1F }, - { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00800756, 0x00F3FFFF }, - { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00C37756, 0x00F3FFFF }, - { 3, 0x144, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x00000036, 0x000000FF }, /* Errata 281 Workaround */ @@ -210,45 +210,45 @@ AMD_PTYPE_SVR, 0x00000001, 0x0000000F }, /* [3:0] RspTok = 0001b */ - { 3, 0x148, AMD_DR_ALL, AMD_PTYPE_UMA, + { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA, 0x8000052A, 0xD5FFFFFF }, /* ACPI Power State Control Reg1 */ - { 3, 0x80, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xE6002200, 0xFFFFFFFF }, /* ACPI Power State Control Reg2 */ - { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xA0E641E6, 0xFFFFFFFF }, - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, + { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ /* Reported Temp Control Register */ - { 3, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */ /* Clock Power/Timing Control 0 Register */ - { 3, 0xD4, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1, [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */ /* Clock Power/Timing Control 1 Register */ - { 3, 0xD8, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1, [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */ /* Clock Power/Timing Control 2 Register */ - { 3, 0xDC, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */ /* Extended NB MCA Config Register */ - { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, [9] SyncOnUncNbAryEn = 1 , [8] SyncOnProtEn = 1, @@ -258,11 +258,11 @@ [1] SyncFloodOnUsPwDataErr = 1 */ /* L3 Control Register */ - { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ /* IBS Control Register */ - { 3, 0x1CC, AMD_DR_ALL, AMD_PTYPE_ALL, + { 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ }; @@ -279,40 +279,40 @@ u32 mask; } fam10_htphy_default[] = { - { 0x520A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */ - { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000000, 0x000000FF }, /* Provide clear setting for logical completeness */ - { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ - { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ /* Link Phy Receiver Loop Filter Registers */ - { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, [21:14] LfcMin = 10h */ - { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ - { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, + { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, [21:14] LfcMin = 08h */ }; Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2009-05-14 23:42:41 UTC (rev 4288) @@ -39,11 +39,12 @@ * 00100F00h 1000h 01000020h * 00100F01h 1000h 01000020h * 00100F02h 1000h 01000020h - * 00100F20h 1020h 01000084h - * 00100F21h 1020h 01000084h - * 00100F2Ah 1020h 01000084h - * 00100F22h 1022h 01000083h - * 00100F23h 1022h 01000083h + * 00100F20h 1020h 01000096h + * 00100F21h (DR-B1) 1020h 01000096h + * 00100F2Ah (DR-BA) 1020h 01000096h + * 00100F22h (DR-B2) 1022h 01000095h + * 00100F23h (DR-B3) 1022h 01000095h + * 00100F62h (DA-C2) 1062h 0100009Fh */ #include AMD_UCODE_PATCH_FILE @@ -66,6 +67,7 @@ 0x100f2A, 0x1020, 0x100f22, 0x1022, 0x100f23, 0x1022, + 0x100f62, 0x1062, }; u32 new_id; Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 23:42:41 UTC (rev 4288) @@ -261,11 +261,12 @@ ## ## Set microcode patch file name ## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" +## Barcelona rev DR-Ax: "mc_patch_01000020.h" +## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" +## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" +## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" +default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-05-14 23:42:41 UTC (rev 4288) @@ -258,11 +258,12 @@ ## ## Set microcode patch file name ## -## Barcelona rev Ax: "mc_patch_01000020.h" -## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" -## Barcelona rev B2, B3: "mc_patch_01000083.h" +## Barcelona rev DR-Ax: "mc_patch_01000020.h" +## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h" +## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" +## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" +default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/raminit_amdmct.c 2009-05-14 23:42:41 UTC (rev 4288) @@ -149,6 +149,9 @@ case 0x10023: ret = AMD_DR_B3; break; + case 0x10062: + ret = AMD_RB_C2; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2009-05-14 22:11:08 UTC (rev 4287) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2009-05-14 23:42:41 UTC (rev 4288) @@ -40,6 +40,7 @@ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ #define AMD_DR_B3 0x00800000 /* Barcelona B3 */ +#define AMD_RB_C2 0x01000000 /* Shanghai C2 */ /* * Groups - Create as many as you wish, from the above public values @@ -57,6 +58,8 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2) +#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE

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[PATCH] flashrom: Force -p nic3com=bb:dd.f if multiple cards found
by Uwe Hermann 15 May '09

15 May '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[flashrom] r513 - trunk
by svn＠coreboot.org 15 May '09

15 May '09

Author: uwe Date: 2009-05-15 00:58:21 +0200 (Fri, 15 May 2009) New Revision: 513 Modified: trunk/flashrom.8 trunk/nic3com.c Log: Make the nic3com code check how many supported NICs are found. If we find multiple ones, abort with a message to the user, suggesting to use the flashrom -p nic3com=bb:dd.f syntax. If exactly one supported NIC is found, use it. If none is found, abort with an error. Print the bb:dd.f numbers for all supported NICs we find, so the user doesn't have to poke around in lspci output to find the desired bb:dd.f. Also, drop one pci_read_long() in favor of using the already existing base_addr[0] struct field. Drop the BAR in user messages, it's not really useful for us. Instead, explain the BDF syntax a bit more verbosely. While I'm at it, update the manpage some more to mention and fully document the external programmer support we have (or will have soon). The patch is tested on hardware: $ flashrom -p nic3com flashrom v0.9.0-r512 Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0) Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:03.0) Error: Multiple supported NICs found. Please use 'flashrom -p nic3com=bb:dd.f' to explicitly select the card with the given BDF (PCI bus, device, function). $ flashrom -p nic3com=05:04.0 flashrom v0.9.0-r512 Found NIC "3COM 3C905C: EtherLink 10/100 PCI (TX)" (10b7:9200, BDF 05:04.0) Calibrating delay loop... OK. Found chip "Atmel AT49BV512" (64 KB) at physical address 0xffff0000. No operations were specified. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-14 21:41:10 UTC (rev 512) +++ trunk/flashrom.8 2009-05-14 22:58:21 UTC (rev 513) @@ -1,13 +1,17 @@ -.TH FLASHROM 8 "April 11, 2009" +.TH FLASHROM 8 "May 14, 2009" .SH NAME -flashrom \- read, write, verify and erase BIOS/ROM/flash chips +flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS -.B flashrom \fR[\fB\-rwvEVfLhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end] - [\fB-m\fR [vendor:]part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file] +.B flashrom \fR[\fB\-EVfLhR\fR] [\fB\-r\fR file] [\fB\-w\fR file] [\fB\-v\fR file] + [\fB\-c\fR chipname] [\fB\-s\fR addr] [\fB\-e\fR addr] [\fB\-m\fR [vendor:]part] + [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] [file] .SH DESCRIPTION .B flashrom -is a utility for reading, writing, verifying and erasing flash ROM chips. -It's often used to flash BIOS/coreboot/firmware images. +is a utility for detecting, reading, writing, verifying and erasing flash ROM +chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system +using a supported mainboard, but it also supports flashing of network cards +(NICs), SATA controller cards, and other external devices which can program +flash chips. .PP It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash, @@ -126,11 +130,24 @@ .B "\-p, \-\-programmer <name>" Specify the programmer device. Currently supported are: .sp -.BR " internal" " (default, for in-system flashing in the mainboard)" -.br -.BR " nic3com" " (for flash ROMs on 3COM network cards)" -.br -.BR " dummy" " (just prints all operations and accesses)" +.BR "* internal" " (default, for in-system flashing in the mainboard)" +.sp +.BR "* nic3com" " (for flash ROMs on 3COM network cards)" +.sp +If you have multiple supported NICs in your system, you must use +.B "flashrom -p nic3com=bb:dd.f" +to explicitly select one of them, where +.B bb +is the PCI bus number, +.B dd +is the PCI device number, and +.B f +is the PCI function number of the desired NIC. +.sp +Example: +.B "flashrom -p nic3com=05:04.0" +.sp +.BR "* dummy" " (just prints all operations and accesses)" .TP .B "\-h, \-\-help" Show a help text and exit. Modified: trunk/nic3com.c =================================================================== --- trunk/nic3com.c 2009-05-14 21:41:10 UTC (rev 512) +++ trunk/nic3com.c 2009-05-14 22:58:21 UTC (rev 513) @@ -67,18 +67,18 @@ uint32_t nic3com_validate(struct pci_dev *dev) { - int i = 0; - uint32_t addr = -1; + int i; + uint32_t addr; for (i = 0; nics[i].device_name != NULL; i++) { if (dev->device_id != nics[i].device_id) continue; - addr = pci_read_long(dev, PCI_IO_BASE_ADDRESS) & ~0x03; + addr = (uint32_t)(dev->base_addr[0] & ~0x03); - printf("Found NIC \"3COM %s\" (%04x:%04x), addr = 0x%x\n", - nics[i].device_name, PCI_VENDOR_ID_3COM, - nics[i].device_id, addr); + printf("Found NIC \"3COM %s\" (%04x:%04x, BDF %02x:%02x.%x)\n", + nics[i].device_name, dev->vendor_id, + dev->device_id, dev->bus, dev->dev, dev->func); if (nics[i].status == NT) { printf("===\nThis NIC is UNTESTED. Please email a " @@ -90,41 +90,48 @@ return addr; } - return addr; + return 0; } int nic3com_init(void) { struct pci_dev *dev; char *msg = NULL; + int found = 0; get_io_perms(); pacc = pci_alloc(); /* Get the pci_access structure */ pci_init(pacc); /* Initialize the PCI library */ pci_scan_bus(pacc); /* We want to get the list of devices */ + pci_filter_init(pacc, &filter); + /* Filter by vendor and also bb:dd.f (if supplied by the user). */ + filter.vendor = PCI_VENDOR_ID_3COM; if (nic_pcidev != NULL) { - pci_filter_init(pacc, &filter); - if ((msg = pci_filter_parse_slot(&filter, nic_pcidev))) { fprintf(stderr, "Error: %s\n", msg); exit(1); } } - if (!filter.vendor && !filter.device) { - pci_filter_init(pacc, &filter); - filter.vendor = PCI_VENDOR_ID_3COM; + for (dev = pacc->devices; dev; dev = dev->next) { + if (pci_filter_match(&filter, dev)) { + if ((io_base_addr = nic3com_validate(dev)) != 0) + found++; + } } - dev = pci_dev_find_filter(filter); - - if (dev && (dev->vendor_id == PCI_VENDOR_ID_3COM)) - io_base_addr = nic3com_validate(dev); - else { + /* Only continue if exactly one supported NIC has been found. */ + if (found == 0) { fprintf(stderr, "Error: No supported 3COM NIC found.\n"); exit(1); + } else if (found > 1) { + fprintf(stderr, "Error: Multiple supported NICs found. " + "Please use 'flashrom -p nic3com=bb:dd.f' \n" + "to explicitly select the card with the given BDF " + "(PCI bus, device, function).\n"); + exit(1); } /*

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build service results for r4287
by coreboot information 15 May '09

15 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "vlim" checked in revision 4287 to the coreboot repository. This caused the following changes: Change Log: Trivia: remove comment Signed-off-by: Vincent Lim <vincent.lim(a)amd.com> Acked-by: Vincent Lim <vincent.lim(a)amd.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4287&device=mew-am&vendor=… If something broke during this checkin please be a pain in vlim's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4286
by coreboot information 15 May '09

15 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "vlim" checked in revision 4286 to the coreboot repository. This caused the following changes: Change Log: >From AMD family 10h Processor BKDG (rev. D): a platform is capable of having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores. Signed-off-by: Vincent Lim <vincent.lim(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4286&device=mew-am&vendor=… If something broke during this checkin please be a pain in vlim's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4287 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10
by svn＠coreboot.org 15 May '09

15 May '09

Author: vlim Date: 2009-05-15 00:11:08 +0200 (Fri, 15 May 2009) New Revision: 4287 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: Trivia: remove comment Signed-off-by: Vincent Lim <vincent.lim(a)amd.com> Acked-by: Vincent Lim <vincent.lim(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 22:00:28 UTC (rev 4286) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 22:11:08 UTC (rev 4287) @@ -184,7 +184,6 @@ ## ## Build code for SMP support -## Only worry about 2 micro processors ## default CONFIG_SMP=1 default CONFIG_MAX_PHYSICAL_CPUS=8

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[v2] r4286 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10
by svn＠coreboot.org 15 May '09

15 May '09

Author: vlim Date: 2009-05-15 00:00:28 +0200 (Fri, 15 May 2009) New Revision: 4286 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: >From AMD family 10h Processor BKDG (rev. D): a platform is capable of having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores. Signed-off-by: Vincent Lim <vincent.lim(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 21:26:28 UTC (rev 4285) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-05-14 22:00:28 UTC (rev 4286) @@ -187,8 +187,8 @@ ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS +default CONFIG_MAX_PHYSICAL_CPUS=8 +default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 #default SERIAL_CPU_INIT=0

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build service results for r4285
by coreboot information 14 May '09

14 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4285 to the coreboot repository. This caused the following changes: Change Log: #136: failed to boot under KVM\QEMU > -------------------------------------+-------------------------------------- > Reporter: silicium@… | Owner: somebody > Type: defect | Status: new > Priority: major | Milestone: > Component: coreboot | Version: v2 > Keywords: | Dependencies: > Patchstatus: patch needs review | > -------------------------------------+-------------------------------------- Fix use of uninitialized pointers. To help in future, move the declaration to the same scope as the use. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4285&device=mew-am&vendor=… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot May 2009