coreboot March 2009

coreboot@coreboot.org

64 participants
316 discussions

[PATCH] v1: Add license headers to AMD AMD-768 code
by Uwe Hermann 16 Apr '09

16 Apr '09

Yay, my first v1 patch :) Eric, any other code chunks which were mostly/entirely written by you where we can slap a GPLv2 header on? AMD-766, others? Btw, was this code from 2003 (C) Eric W. Biederman or rather (C) LNXI? Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[PATCH] v2: abuild: Add -r|--remove option to abuild
by Uwe Hermann 15 Apr '09

15 Apr '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Seabios configuration
by Wang, Qingpei 14 Apr '09

14 Apr '09

Hi all, I just followed the instruction of http://www.coreboot.org/SeaBIOS concern about #define CONFIG_OPTIONROMS_DEPLOYED 0 , But It can not show the video output correct. Maybe something wrong with it. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

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[PATCH] [v3] Fix ROM caching on Via C7
by Corey Osgood 14 Apr '09

14 Apr '09

Tested and working on hardware :D -Corey

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Fix some PCI issues on M57SLI v2
by Harald Gutmann 08 Apr '09

08 Apr '09

Hello, a few hours ago i started to address the PCI/PCI-E problems on the M57SLI-S4 (rev. 2) and here is the result of the moment. PCI-E grapic adapter works fine with the proprietary nvidia driver! (And the GPIO configuration in cache_as_ram_auto.c should be fully corrected.) The patch for that solution(s) is attached. (I don't know if this will work on v1 too, but i assume it will. I also don't know right now if there are more problems cleaned out with that patch.) Please be so kindly, and don't ask why the value has changed from "68" (which is the same in original bios) to "A8", but recently it's necessary to do it, because otherwise the value is wrong when you read it out from a running system. Kind Regards, Harald

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#124: Latest AMD Fam. 10 microcode patch
by coreboot 08 Apr '09

08 Apr '09

#124: Latest AMD Fam. 10 microcode patch ---------------------------------+------------------------------------------ Reporter: MarcoS | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ >Timestamp: >03/25/09 16:47:58 (5 days ago) >Author:mjones >Message:The latest ucode patches for Family 10h: >9fh for RB/BL/DA Rev C; According to the "Revision guide for fam. 10 processors" this patch is only for DA Rev C, not for RB -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/124> coreboot <http://www.coreboot.org/>

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[PATCH] wip - suspend/resume for AMD famF revF CPUs (socket AM2)
by Rudolf Marek 08 Apr '09

08 Apr '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, This patch is a WIP patch to get working S3 on AM2 boards. Currently it works on M2V-MX SE. The resume code does only the ram init right. No code which saves/restores mem is there. It is not yet usable. I needed to implement DQS timming save restore. I use NVRAM in K8M890 for this. The SB600 has also such NVRAM. There is quite strange errata for mine CPU, so the exit self refresh code is strange. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm0OO4ACgkQ3J9wPJqZRNX+6wCg1SMFCEW8IDccBBJWcRV9KtaL jU4An2rIGM5/nU6j/0AErME5oVSdPtSO =SoLP -----END PGP SIGNATURE-----

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Net and virtio problem with QEMU 0.10.0 and coreboot v2
by rukhsana ansari 07 Apr '09

07 Apr '09

Hi, Software used : qemu-0.10.0, coreboot-v2, filo(latest svn version), fedora9 image Problem encountered: qemu boots Fedora9 image successfully. However, the ethernet interface isn't up and dmesg shows an irq problem. Thhings tried out: I've tried pci=biosirq and problems still remains. I've also patched with the qemu bios patch (0.9.1) available at: http://www.mail-archive.com/coreboot@coreboot.org/msg01771.html However, I haven't applied the other patches that are meant for 0.9 and available at ttp://www.coreboot.org/QEMU_Build_Tutorial#Building_Qemu <http://www.coreboot.org/QEMU_Build_Tutorial#Building_Qemu> because the code difference with 0.10.0 Any suggestions from coreboot experts on howto proceed to resolve this issue? === The following is an edited version of dmesg that shows an irq problem: ne2k-pci.c:v1.03 9/22/2003 D. Becker/P. Gortmaker PCI: No IRQ known for interrupt pin A of device 0000:00:03.0. Please try using pci=biosirq. eth0: RealTek RTL-8029 found at 0x1000, IRQ 0, 52:54:00:12:34:56. PCI: No IRQ known for interrupt pin A of device 0000:00:04.0. Please try using pci=biosirq. IRQ handler type mismatch for IRQ 0 current handler: timer Pid: 490, comm: modprobe Not tainted 2.6.25-14.fc9.i686 #1 [<c045cae6>] setup_irq+0x19a/0x1b2 [<c48ec2fe>] ? vp_interrupt+0x0/0x9a [virtio_pci] [<c045cbc6>] request_irq+0xc8/0xe6 [<c48ec53a>] virtio_pci_probe+0x138/0x193 [virtio_pci] [<c04feac9>] pci_device_probe+0x39/0x59 [<c0562826>] driver_probe_device+0xa0/0x136 [<c0562935>] __driver_attach+0x79/0xaf [<c05621d3>] bus_for_each_dev+0x3b/0x63 [<c05626cb>] driver_attach+0x14/0x16 [<c05628bc>] ? __driver_attach+0x0/0xaf [<c0561ba4>] bus_add_driver+0x9d/0x1ba [<c0562ab8>] driver_register+0x47/0xa7 [<c04fec75>] __pci_register_driver+0x35/0x64 [<c480e028>] virtio_pci_init+0x28/0x3d [virtio_pci] [<c0446f93>] sys_init_module+0x17be/0x18f6 [<c04d3577>] ? selinux_file_permission+0x100/0x106 [<c04cc41c>] ? security_file_permission+0xf/0x11 [<c04835e1>] ? sys_read+0x3b/0x60 [<c0405bf2>] syscall_call+0x7/0xb ======================= virtio-pci: probe of 0000:00:04.0 failed with error -16 --- IRQ handler type mismatch for IRQ 0 current handler: timer Pid: 1524, comm: NetworkManager Not tainted 2.6.25-14.fc9.i686 #1 [<c045cae6>] setup_irq+0x19a/0x1b2 [<c488ff10>] ? ei_interrupt+0x0/0xa [8390] [<c045cbc6>] request_irq+0xc8/0xe6 [<c48e8447>] ne2k_pci_open+0x1c/0x79 [ne2k_pci] [<c05baccf>] dev_open+0x46/0x7e [<c05ba84e>] dev_change_flags+0x9f/0x152 [<c05c12f6>] do_setlink+0x211/0x2c3 [<c05c148a>] rtnl_setlink+0xe2/0xe6 [<c05c13a8>] ? rtnl_setlink+0x0/0xe6 [<c05c231f>] rtnetlink_rcv_msg+0x1a0/0x1ba [<c05c217f>] ? rtnetlink_rcv_msg+0x0/0x1ba [<c05cf18e>] netlink_rcv_skb+0x30/0x86 [<c05c2177>] rtnetlink_rcv+0x1c/0x24 [<c05cecb8>] netlink_unicast+0x1b1/0x20f [<c05cef6b>] netlink_sendmsg+0x255/0x262 [<c05afda0>] sock_sendmsg+0xde/0xf9 [<c04387e7>] ? autoremove_wake_function+0x0/0x33 [<c04387e7>] ? autoremove_wake_function+0x0/0x33 [<c04cf49e>] ? socket_has_perm+0x53/0x5d [<c04f5874>] ? copy_from_user+0x39/0x121 [<c05b6309>] ? verify_iovec+0x40/0x6f [<c05afefa>] sys_sendmsg+0x13f/0x192 [<c05b08e7>] ? sys_recvmsg+0x116/0x17b [<c04f5997>] ? copy_to_user+0x3b/0x10a [<c05b07b9>] ? move_addr_to_user+0x56/0x6e [<c05b0aef>] ? sys_getsockname+0x59/0x76 [<c062bb5a>] ? _spin_unlock_bh+0xe/0x10 [<c05b18b2>] ? release_sock+0x80/0x88 [<c05b2f92>] ? sock_setsockopt+0x506/0x510 [<c04d2097>] ? selinux_socket_setsockopt+0x2d/0x32 [<c05b0deb>] sys_socketcall+0x16b/0x188 [<c0405bf2>] syscall_call+0x7/0xb = ====================== cat /proc/interrupts shows - CPU0 0: 154394 XT-PIC-XT timer 1: 221 XT-PIC-XT i8042 2: 0 XT-PIC-XT cascade 4: 4 XT-PIC-XT 12: 111 XT-PIC-XT i8042 14: 5125 XT-PIC-XT ata_piix 15: 753 XT-PIC-XT ata_piix NMI: 0 Non-maskable interrupts LOC: 102 Local timer interrupts RES: 0 Rescheduling interrupts CAL: 0 function call interrupts TLB: 0 TLB shootdowns TRM: 0 Thermal event interrupts SPU: 0 Spurious interrupts ERR: 0 MIS: 0 Thanks, -Rukhsana

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Re: [coreboot] flashrom fails to write/erase on VIA VT8237
by vinuxesgmail 07 Apr '09

07 Apr '09

Hello Peter, > >1. Which vendor and board is this? > The M/B model name is PPAP-2020VL, and the vendor is Portwell. > >2. Please find out where pin 7 WP# and 8 TBL# on the flash chip are > connected. To which pin on which chip? > Pin 7 and 8 of the flash-chip are connected to GPIOA. GPIOA connects to 8237R AE5 PIN. Please find the attached board diagram image "8237.jpg". Let me know if u need any further information. Regards, Vinod

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Re: [coreboot] [v3] r1162 - coreboot-v3/northbridge/intel/i440bxemulation
by Carl-Daniel Hailfinger 02 Apr '09

02 Apr '09

On 24.03.2009 00:55, svn(a)coreboot.org wrote: > Author: rminnich > Date: 2009-03-24 00:55:58 +0100 (Tue, 24 Mar 2009) > New Revision: 1162 > > Modified: > coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c > Log: > This is an emergency fix for building for qemu. > > With this fix, FILO works. > This was already fixed with a weak function since r1161. Changelog was: Emergency fixup for the missing is_coldboot(). Note that the weak is_coldboot() returns always 1. The i945 is_coldboot() returns 1 for a warm boot? Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot March 2009