Hello Peter,
- Which vendor and board is this?
The M/B model name is PPAP-2020VL, and the vendor is Portwell.
- Please find out where pin 7 WP# and 8 TBL# on the flash chip are
connected. To which pin on which chip?
Pin 7 and 8 of the flash-chip are connected to GPIOA. GPIOA connects to 8237R AE5 PIN. Please find the attached board diagram image "8237.jpg".
Let me know if u need any further information.
Regards, Vinod
Dear Vinod,
vinuxesgmail wrote:
- Which vendor and board is this?
The M/B model name is PPAP-2020VL, and the vendor is Portwell.
Great!
- Please find out where pin 7 WP# and 8 TBL# on the flash chip
are connected. To which pin on which chip?
Pin 7 and 8 of the flash-chip are connected to GPIOA. GPIOA connects to 8237R AE5 PIN. Please find the attached board diagram image "8237.jpg".
Perfect information! Thank you very much.
Let me know if u need any further information.
Please apply the attached patch to the flashrom code, build and run to see if my idea for enabling writes on this board works.
Unfortunately you must use flashrom -m ppap-2020vl while testing, because of this I would also appreciate if you can supply lspci -vnn output, so that the board can be autodetected instead, if there are unique PCI subsystem IDs.
Best regards
//Peter
Hello Peter, I applied the patch that u had sent, but still its not working.
Here's the output: {------------------------------- # ./flashrom -m "portwell:ppap-2020vl" -E
Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK.
Unknown vendor:board from coreboot table or -m option: portwell:ppap-2020vl
Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49 --------------------------------}
I looked at the code and found that in "board_flash_enable" routine, "board_match_coreboot_name" fails in "pci_dev_find", and so board is returned as NULL.
Please find the attached output of lspci -vnn.
Please guide me further!
Rgds, Vinod
stress:/tmp # lspci -i ./pci.ids -vnn 0000:00:00.0 Class 0600: 1106:0314 Subsystem: 1106:0314 Flags: bus master, 66Mhz, medium devsel, latency 8 Memory at e8000000 (32-bit, prefetchable) Capabilities: [80] AGP version 3.5 Capabilities: [50] Power Management version 2
0000:00:00.1 Class 0600: 1106:1314 Flags: bus master, medium devsel, latency 0
0000:00:00.2 Class 0600: 1106:2314 Flags: bus master, medium devsel, latency 0
0000:00:00.3 Class 0600: 1106:3208 Flags: bus master, medium devsel, latency 0
0000:00:00.4 Class 0600: 1106:4314 Flags: bus master, medium devsel, latency 0
0000:00:00.7 Class 0600: 1106:7314 Flags: bus master, medium devsel, latency 0
0000:00:01.0 Class 0604: 1106:b198 Flags: bus master, 66Mhz, medium devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: f4000000-f5ffffff Prefetchable memory behind bridge: f0000000-f3ffffff Secondary status: SERR Capabilities: [70] Power Management version 2
0000:00:08.0 Class 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Flags: bus master, medium devsel, latency 32, IRQ 10 I/O ports at d000 Memory at f6000000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2
0000:00:09.0 Class 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Flags: bus master, medium devsel, latency 32, IRQ 11 I/O ports at d400 Memory at f6001000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2
0000:00:0a.0 Class 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Flags: bus master, medium devsel, latency 32, IRQ 7 I/O ports at d800 Memory at f6002000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2
0000:00:0b.0 Class 0200: 10ec:8139 (rev 10) Subsystem: 10ec:8139 Flags: bus master, medium devsel, latency 32, IRQ 5 I/O ports at dc00 Memory at f6003000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2
0000:00:0f.0 Class 0101: 1106:3149 (rev 80) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: 1106:3149 Flags: bus master, medium devsel, latency 32, IRQ 11 I/O ports at e800 I/O ports at e400 [size=4] I/O ports at e500 [size=8] I/O ports at e600 [size=4] I/O ports at e700 [size=16] I/O ports at e000 [size=256] Capabilities: [c0] Power Management version 2
0000:00:0f.1 Class 0101: 1106:0571 (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: 1106:0571 Flags: bus master, medium devsel, latency 32, IRQ 10 I/O ports at e900 [size=16] Capabilities: [c0] Power Management version 2
0000:00:10.0 Class 0c03: 1106:3038 (rev 81) Subsystem: 1106:3038 Flags: bus master, medium devsel, latency 32, IRQ 10 I/O ports at ea00 [size=32] Capabilities: [80] Power Management version 2
0000:00:10.1 Class 0c03: 1106:3038 (rev 81) Subsystem: 1106:3038 Flags: bus master, medium devsel, latency 32, IRQ 10 I/O ports at eb00 [size=32] Capabilities: [80] Power Management version 2
0000:00:10.2 Class 0c03: 1106:3038 (rev 81) Subsystem: 1106:3038 Flags: bus master, medium devsel, latency 32, IRQ 11 I/O ports at ec00 [size=32] Capabilities: [80] Power Management version 2
0000:00:10.3 Class 0c03: 1106:3038 (rev 81) Subsystem: 1106:3038 Flags: bus master, medium devsel, latency 32, IRQ 11 I/O ports at ed00 [size=32] Capabilities: [80] Power Management version 2
0000:00:10.4 Class 0c03: 1106:3104 (rev 86) (prog-if 20) Subsystem: 1106:3104 Flags: bus master, medium devsel, latency 32, IRQ 7 Memory at f6004000 (32-bit, non-prefetchable) Capabilities: [80] Power Management version 2
0000:00:11.0 Class 0601: 1106:3227 Subsystem: 1106:3227 Flags: bus master, stepping, medium devsel, latency 0 Capabilities: [c0] Power Management version 2
0000:01:00.0 Class 0300: 1106:3344 (rev 01) Subsystem: 1106:3344 Flags: bus master, 66Mhz, medium devsel, latency 32, IRQ 10 Memory at f0000000 (32-bit, prefetchable) [size=f5000000] Memory at f4000000 (32-bit, non-prefetchable) [size=16M] Expansion ROM at 00010000 [disabled] Capabilities: [60] Power Management version 2 Capabilities: [70] AGP version 3.0
Hi again Vinod,
vinuxesgmail wrote:
I applied the patch that u had sent, but still its not working.
Sorry, my mistake. It is not possible to leave PCI IDs completely empty. Please try this attached patch instead. If it works, send a line like:
Acked-by: Your Name your@email
and I will be happy to commit this patch. :)
Please find the attached output of lspci -vnn.
Thank you very much. Unfortunately there are no unique subsystem ids that can be used to autodetect the board, so you will always have to run flashrom with -m.
//Peter
vinuxesgmail wrote:
Peter, i could not find any attached patch :)
Gah! Sorry. Here it is.
//Peter
Peter, I am stuck with the same error even after applying the new patch. Here's the command output: {------------------- stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49 ------------------- stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! -------------------}
Please guide me further.
Regards, Vinod
Peter Stuge wrote:
Gah! Sorry. Here it is.
//Peter
Hello Peter, Is there something that i can look into? or any pointers? Please help!
Rgds, Vinod
On Tue, Mar 31, 2009 at 10:31 AM, vinuxesgmail vinuxes@gmail.com wrote:
Peter, I am stuck with the same error even after applying the new patch. Here's the command output: {------------------- stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! -------------------}
Please guide me further.
Regards, Vinod
Peter Stuge wrote:
Gah! Sorry. Here it is.
//Peter
Look through the vt823x code in chipset_enable.c and also the epia-cn code in board_enable.c. Check the values of the registers modified by those functions, and if your board's registers don't match those values, call the appropriate function at the end of the board_enable for your board. Sorry I can't be more specific, I only have a few minutes to check email.
-Corey
2009/4/1 vinuxes gmail vinuxes@gmail.com
Hello Peter, Is there something that i can look into? or any pointers? Please help!
Rgds, Vinod
On Tue, Mar 31, 2009 at 10:31 AM, vinuxesgmail vinuxes@gmail.com wrote:
Peter, I am stuck with the same error even after applying the new patch. Here's the command output: {------------------- stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED! -------------------}
Please guide me further.
Regards, Vinod
Peter Stuge wrote:
Gah! Sorry. Here it is.
//Peter
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Hi Vinod,
vinuxes gmail wrote:
Is there something that i can look into? or any pointers?
Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED!
Ok. I guess my board enable code doesn't work properly. Maybe you can help me look into the relevant registers manually?
Please download http://stuge.se/io.c and compile it using: gcc -O2 -o io io.c
Please run: setpci -d 1106:3227 e6.b 88.l
The command should print one hexadecimal byte and one hex long. Please save these values.
Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please run io: ./io r__4f
(Replace __ here with bits 8-15 from the hex long value from setpci.)
After this, please run flashrom with the patch. (It will still fail.)
Then please run the setpci and io command again, and finally send an email with the output from all commands.
Thanks for your help!
//Peter
Hi Peter, Here's the output of all the commands:
stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l 00 00000401
Extract 8-15 bits from long value: 04
stress:/tmp # ./io r044f r0x044f=ff
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -r backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Reading flash... done.
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED!
stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l 00 00000401
stress:/tmp # ./io r044f r0x044f=ff
Rgds, Vinod
Peter Stuge wrote:
Ok. I guess my board enable code doesn't work properly. Maybe you can help me look into the relevant registers manually?
Please download http://stuge.se/io.c and compile it using: gcc -O2 -o io io.c
Please run: setpci -d 1106:3227 e6.b 88.l
The command should print one hexadecimal byte and one hex long. Please save these values.
Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please run io: ./io r__4f
(Replace __ here with bits 8-15 from the hex long value from setpci.)
After this, please run flashrom with the patch. (It will still fail.)
Then please run the setpci and io command again, and finally send an email with the output from all commands.
Thanks for your help!
//Peter
Hello [again] Peter, Could u derives anything from the output that i have sent? Awaiting reply!
Rgds, Vinod
vinuxesgmail wrote:
Hi Peter, Here's the output of all the commands:
stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l 00 00000401
Extract 8-15 bits from long value: 04
stress:/tmp # ./io r044f r0x044f=ff
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -r backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Reading flash... done.
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49
stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found board "Portwell PPAP-2020VL", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. ERASE FAILED!
stress:/tmp # ./setpci -d 1106:3227 e6.b 88.l 00 00000401
stress:/tmp # ./io r044f r0x044f=ff
Rgds, Vinod
Peter Stuge wrote:
Ok. I guess my board enable code doesn't work properly. Maybe you can help me look into the relevant registers manually?
Please download http://stuge.se/io.c and compile it using: gcc -O2 -o io io.c
Please run: setpci -d 1106:3227 e6.b 88.l
The command should print one hexadecimal byte and one hex long. Please save these values.
Use bits 8-15 as port bits 8-15 and use 4f as bits 0-7, then please run io: ./io r__4f
(Replace __ here with bits 8-15 from the hex long value from setpci.)
After this, please run flashrom with the patch. (It will still fail.)
Then please run the setpci and io command again, and finally send an email with the output from all commands.
Thanks for your help!
//Peter
Hi Vinod,
vinuxesgmail wrote:
Could u derives anything from the output that i have sent? Awaiting reply!
The output is surprising. If I interpret the 8237 datasheet correctly, GPO24 should already be high, and the chip should be writable.
These are open drain outputs however so if the GPIOA net does not have a pullup resistor (should be on page 14 in the schematic) that could explain the behavior we are seeing.
Another explanation is that the correct IO register is actually offset 0x4c and not 0x4f. Then I have simply misunderstood the byte ordering of the GPOVAL, that is definately a possibility.
Suggestions:
* Check for a pullup on the GPIOA net. If it is missing, try adding one. * Run ./io r44c r44d r44e r44f If the first byte has some bits unset, I misunderstood the byte order.
I hope this brings us closer to a solution!
//Peter
Hi Peter,
- Check for a pullup on the GPIOA net. If it is missing, try adding one.
GPIOA net has pull-high 4.4Komh (3.3V).
- Run ./io r44c r44d r44e r44f If the first byte has some bits unset, I misunderstood the byte order.
stress:/tmp # ./io r44c r44d r44e r44f r0x044c=ff r0x044d=ff r0x044e=ff r0x044f=ff
Rgds, Vinod
-
Corey Osgood -
Peter Stuge -
vinuxes gmail -
vinuxesgmail