coreboot March 2009

coreboot@coreboot.org

64 participants
316 discussions

Questions to ACPI, Interrupts, APICS (M57SLI)
by Harald Gutmann 29 Mar '09

29 Mar '09

Hello, a few days ago i happily sent a patch for fixing the PCI-issues on the m57sli to the list. After some further tests, i just have gotten more questions, and nothing seems to be "really" fixed. I attached two patches, one corrects just the GPIOS and does some changes to mptable.c, but nothing special. The second corrects the GPIO stuff, and adds acpi support to the m57sli. Now i've the following situation: With the first patch (GPIO, mptable) nothing is "really" fixed, because PCI-E doesn't receive interrupts, and also another PCI-slot has interrupt problems. Here is for example a little output from the dmesg according to interrupts: "[ 31.542432] Pid: 0, comm: swapper Tainted: P 2.6.26-1-amd64 #1 [ 31.542434] [ 31.542435] Call Trace: [ 31.542436] <IRQ> [<ffffffff8026c6c3>] __report_bad_irq+0x30/0x72 [ 31.542459] [<ffffffff8026c902>] note_interrupt+0x1fd/0x23b [ 31.542464] [<ffffffff8026d18b>] handle_fasteoi_irq+0xa5/0xc8 [ 31.542468] [<ffffffff8020f5e4>] do_IRQ+0x6d/0xd9 [ 31.542470] [<ffffffff8020b0a3>] default_idle+0x0/0x49 [ 31.542472] [<ffffffff8020c46d>] ret_from_intr+0x0/0x19 [ 31.542474] <EOI> [<ffffffff8021eb54>] native_safe_halt+0x2/0x3 [ 31.542481] [<ffffffff8021eb54>] native_safe_halt+0x2/0x3 [ 31.542484] [<ffffffff8020b0cd>] default_idle+0x2a/0x49 [ 31.542486] [<ffffffff8020ac79>] cpu_idle+0x89/0xb3 [ 31.542493] [ 31.542494] handlers: [ 31.542495] [<ffffffffa02a6b8d>] (snd_ice1712_interrupt+0x0/0x1c2 [snd_ice1712]) [ 31.542507] Disabling IRQ #19" (Ideas for fixing that problem? This device is on a pci-slot, and has in mptable.c irq 19 assigned. Therefore i don't see in CB-code what could be done to fix it.) With the second patch, including ACPI with the original (proprietary) dsdt.asl file, everything works fine. The PCI-E graphic card works like a charm, there are no strange messages according to IRQ19 in the dmesg, ... So now my basic question is: What does the acpi part do, to get all the IRQ's correct? Why doesn't that work without ACPI support? (Is this maybe done in the dsdt.asl?) Where do i have to correct things, to get PCI/PCI-E interrupts correct, and without ACPI? Kind Regards, Harald Gutmann

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new students looking for some help
by 于小倩 29 Mar '09

29 Mar '09

Hi all, I am a student of Peking University, I am going to apply for GSOC2009 with Coreboot. My classmates Jaosn Wang introduced coreboot to me. I really like to join in this fantasy group. In the past days I had already learning some thing about Coreboot from the website www.coreboot.org. Because there is only few days for me to write my proposal, I need some help. I want to choose VGA BIOS for Geode LX from the as my proposal. Now my understanding is to write an vga rom for Geode LX which is used for certain graphics cards. Is that right? Or is there any one whol can give me more details about that? Thanks again. Lookin forward... best wishes....

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Paraflasher Update
by Joseph Smith 29 Mar '09

29 Mar '09

Hello, Just wanted to let everyone know I finally had time to finish the Paraflasher board with the SOIC FET Bus Switch With Level Shifting. I uploaded new images. I just have to get a daughter board togethor with a PLCC32 socket on it and I will be ready to get going on a flashrom add-on. Check out the new images: http://www.coreboot.org/Paraflasher -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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prettyprint for hardware registers
by Carl-Daniel Hailfinger 28 Mar '09

28 Mar '09

Could this be something useful for us, especially considering it looks like a combination of msrtool, inteltool etc? I'd like to make sure we don't reinvent the wheel here. Quoting from the description page: "PP is intended to provide infrastructure and tools to describe and manipulate hardware registers and fields. Once described, it is possible to read and write fields symbolically. This allows one to browse the state of their hardware." http://code.google.com/p/prettyprint/ Regards, Carl-Daniel -- http://www.hailfinger.org/

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9fs (9vfs) dicussions going on off list
by Gregg C Levine 28 Mar '09

28 Mar '09

Hello! Ron here's something that will cause you to have a good weekend when you see this: A group of Linux enthusiasts are discussing applications for the Plan 9 file system port that you, and one other fellow, worked on, and eventually contributed to the Source Forge setup. I now understand that it is officially part of the Linux kernel as of the young 2.6 series of kernels, which is good, but the group discussing the whole idea is, reluctantly looking at making it work for them on different sets of Linux images on the S/390 platform. Lets just say that the whole good idea behind it and the corresponding Plan 9 from user space tools that emerged about the same time period are driving them towards the brink of being confused. This is a good thing. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

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Crosscompiler script
by Patrick Georgi 28 Mar '09

28 Mar '09

Hi, after the recent troubles with various compilers miscompiling coreboot, we decided to publish the script we use to build the compiler we use at coresystems. It requires a gnu compatible tar, gnu patch, wget and probably has other, hidden dependencies on behaviour as found on Linux and Mac OS X. Running buildgcc downloads the tarballs (tarball subdirectory), patches the trees slightly (the attached patches must reside in the same directory), links them together (in a totally unsupported but working way), and builds and installs the toolchain (into $PWD/xgcc). Add $PWD/xgcc/bin to your PATH, abuild should pick up the crosscompiler automatically. Regards, Patrick

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[Fwd: Re: [Qemu-devel] Luvalley project: enable Qemu to utilize hardware virtualization extensions on arbitrary operating system]
by Carl-Daniel Hailfinger 28 Mar '09

28 Mar '09

FYI. Regards, Carl-Daniel -------- Original Message -------- Subject: Re: [Qemu-devel] Luvalley project: enable Qemu to utilize hardware virtualization extensions on arbitrary operating system Date: Fri, 27 Mar 2009 22:45:02 +0200 From: Blue Swirl <blauwirbel(a)gmail.com> Reply-To: qemu-devel(a)nongnu.org To: qemu-devel(a)nongnu.org References: <3b0605b30903252037k12f20dft94f809e4b27e1af(a)mail.gmail.com> On 3/26/09, Xiaodong Yi <xdong.yi(a)gmail.com> wrote: > Luvalley is a Virtual Machine Monitor (VMM) spawned from the KVM > project. Its part of source codes are derived from KVM to virtualize > CPU instructions and memory management unit (MMU). However, its > overall architecture is completely different from KVM, but somewhat > like Xen. Luvalley runs outside of Linux, just like Xen's > architecture, but it still uses Linux as its scheduler, memory > manager, physical device driver provider and virtual IO device > emulator. Moreover, Luvalley may run WITHOUT Linux. In theory, any > operating system could take the place of Linux to provide the above > services. Currently, Luvalley supports Linux and Windows. That is to > say, one may run Luvalley to boot a Linux or Windows, and then run > multiple virtualized operating systems on such Linux or Windows. > > In KVM, Qemu is adopted as the IO device emulator. From the point of > view of Qemu, KVM enables Qemu to utilize hardware virtualization > extensions such as Intel's VT on Linux. As for Luvalley, Qemu is also > adopted as its IO device emulator. However, Luvalley could enable Qemu > to utilize hardware virtualization extensions on ANY operating system. > > If you are interested in Luvalley project, you may download Luvalley's > source codes from > http://sourceforge.net/projects/luvalley/ Interesting idea, maybe OpenBIOS or coreboot could be extended to provide the hypervisor interface. For Qemu it would be desirable if the same interface would be used as with plain KVM as far as possible. Comparing Luvalley version of Qemu to released version, the changes seem to be quick hacks with a lot of "#if 0". I guess KVM changes are more radical. -- http://www.hailfinger.org/

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flashrom fails to write/erase on VIA VT8237
by vinuxesgmail 27 Mar '09

27 Mar '09

Hello, While trying to flash the bios using flashrom, i get the following messages: {-------------------- # flashrom -E -f Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. *Erasing flash chip... ERASE FAILED! FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49 *--------------------} Here's the output of other commands: {-------------------- # flashrom -r bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Reading flash... done. # ./flashrom -v bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. # ./flashrom -w bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. *ERASE FAILED!* --------------------} But, when I tried to update the bios using *awdflash *utility, it worked successfully. To describe my board, here's the output of lspci: {------------------ 00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge 00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:01.0 PCI bridge: VIA Technologies, Inc. VT8237/VX700 PCI Bridge 00:09.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 10) 00:0a.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 10) 00:0c.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 10) 00:0d.0 Ethernet controller: Intel Corporation 8255xER/82551IT Fast Ethernet Controller (rev 10) 00:0f.0 IDE interface: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller (rev 80) 00:0f.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] 01:00.0 VGA compatible controller: VIA Technologies, Inc. CN700/P4M800 Pro/P4M800 CE/VN800 [S3 UniChrome Pro] (rev 01) ------------------} Output of biosdecode: {------------------ biosdecode 2.9 SMBIOS 2.3 present. Structure Table Length: 902 bytes Structure Table Address: 0x000F0800 Number Of Structures: 33 Maximum Structure Size: 81 bytes BIOS32 Service Directory present. Revision: 0 Calling Interface Address: 0x000F92C0 PNP BIOS 1.0 present. Event Notification: Not Supported Real Mode 16-bit Code Address: F000:9E58 Real Mode 16-bit Data Address: F000:0000 16-bit Protected Mode Code Address: 0x000F9E30 16-bit Protected Mode Data Address: 0x000F0000 ------------------} Output of dmidecode is attached as dmidecode.txt. Am i doing it wrong? Please guide me. Regards, Vinod # ./dmidecode # dmidecode 2.9 SMBIOS 2.3 present. 33 structures occupying 902 bytes. Table at 0x000F0800. Handle 0x0000, DMI type 0, 20 bytes BIOS Information Vendor: Phoenix Technologies, LTD Version: 6.00 PG Release Date: 07/25/2008 Address: 0xE0000 Runtime Size: 128 kB ROM Size: 512 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/360 KB floppy services are supported (int 13h) 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported AGP is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Handle 0x0001, DMI type 1, 25 bytes System Information Manufacturer: Product Name: Version: Serial Number: UUID: Not Present Wake-up Type: Power Switch Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: Product Name: CN700-8237 Version: Serial Number: Handle 0x0003, DMI type 3, 17 bytes Chassis Information Manufacturer: Type: Desktop Lock: Not Present Version: Serial Number: Asset Tag: Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown OEM Information: 0x00000000 Handle 0x0004, DMI type 4, 35 bytes Processor Information Socket Designation: Socket 370 Type: Central Processor Family: Other Manufacturer: Intel ID: D0 06 00 00 FF BB C9 A7 Version: VIA Eden Voltage: 0.8 V External Clock: 100 MHz Max Speed: 1500 MHz Current Speed: 1000 MHz Status: Populated, Enabled Upgrade: ZIF Socket L1 Cache Handle: 0x0008 L2 Cache Handle: 0x0009 L3 Cache Handle: Not Provided Serial Number: Asset Tag: Part Number: Handle 0x0005, DMI type 5, 20 bytes Memory Controller Information Error Detecting Method: None Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: Four-way Interleave Maximum Memory Module Size: 32 MB Maximum Total Memory Size: 64 MB Supported Speeds: 70 ns 60 ns Supported Memory Types: Standard EDO Memory Module Voltage: 5.0 V Associated Memory Slots: 2 0x0006 0x0007 Enabled Error Correcting Capabilities: None Handle 0x0006, DMI type 6, 12 bytes Memory Module Information Socket Designation: A0 Bank Connections: 0 Current Speed: 50 ns Type: Other Installed Size: 256 MB (Single-bank Connection) Enabled Size: 256 MB (Single-bank Connection) Error Status: OK Handle 0x0007, DMI type 6, 12 bytes Memory Module Information Socket Designation: A1 Bank Connections: None Current Speed: 50 ns Type: Other Installed Size: Not Installed Enabled Size: Not Installed Error Status: OK Handle 0x0008, DMI type 7, 19 bytes Cache Information Socket Designation: Internal Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0009, DMI type 7, 19 bytes Cache Information Socket Designation: External Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: External Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x000A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PRIMARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SECONDARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: FDD Internal Connector Type: On Board Floppy External Reference Designator: Not Specified External Connector Type: None Port Type: 8251 FIFO Compatible Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM1 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM2 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: LPT1 Internal Connector Type: DB-25 female External Reference Designator: External Connector Type: DB-25 female Port Type: Parallel Port ECP/EPP Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Keyboard Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PS/2 Mouse Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Mouse Port Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: USB0 External Connector Type: Other Port Type: USB Handle 0x0013, DMI type 9, 13 bytes System Slot Information Designation: PCI0 Type: 32-bit PCI Current Usage: Available Length: Long ID: 1 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0014, DMI type 9, 13 bytes System Slot Information Designation: PCI1 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 2 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0015, DMI type 9, 13 bytes System Slot Information Designation: PCI2 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 3 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0016, DMI type 9, 13 bytes System Slot Information Designation: PCI3 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 4 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0017, DMI type 9, 13 bytes System Slot Information Designation: AGP Type: 32-bit AGP Current Usage: In Use Length: Long ID: 8 Characteristics: 5.0 V is provided Handle 0x0018, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 3 n|US|iso8859-1 n|US|iso8859-1 r|CA|iso8859-1 Currently Installed Language: n|US|iso8859-1 Handle 0x0019, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 1 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x001A, DMI type 17, 27 bytes Memory Device Array Handle: 0x0019 Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: 256 MB Form Factor: DIMM Set: None Locator: A0 Bank Locator: Bank0/1 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: None Serial Number: None Asset Tag: None Part Number: None Handle 0x001B, DMI type 17, 27 bytes Memory Device Array Handle: 0x0019 Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: A1 Bank Locator: Bank2/3 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: None Serial Number: None Asset Tag: None Part Number: None Handle 0x001C, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000FFFFFFF Range Size: 256 MB Physical Array Handle: 0x0019 Partition Width: 0 Handle 0x001D, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000FFFFFFF Range Size: 256 MB Physical Device Handle: 0x001A Memory Array Mapped Address Handle: 0x001C Partition Row Position: 1 Handle 0x001E, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000000003FF Range Size: 1 kB Physical Device Handle: 0x001B Memory Array Mapped Address Handle: 0x001C Partition Row Position: 1 Handle 0x001F, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0x0020, DMI type 127, 4 bytes End Of Table

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How's the support for NF57SLI?
by Robin Björklin 26 Mar '09

26 Mar '09

I own a board with the NF57SLI chipset from DFI and as far as I can see from your website it works so now to the real questions. Does overclocking work? Can I use Grub2 as a payload and dualboot into windows? Hope someone can answer that for me. Kind regards Robin Bjorklin.

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[PATCH] Fix the NULL dev resource usage
by Rudolf Marek 26 Mar '09

26 Mar '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, During the suspend/resume programming I came to an issue that first 4KB of memory must be clear with 0s because otherwise the resources of K8 will be totally messed up. It took long to figure it out and here it is: res = probe_resource(dev, 0x100 + (reg | link)); This is called with dev = NULL and this is no good for probe_resource at all. The attached patch fixes the potential problems and of course the problem itself. On one particular place was missing test if the device really exists. This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check). The rest of the patch is just very paranoid and do all checkings. This was tested in SimNOW but I believe it will work on real hw too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Anyone knows if SimNOW can do breaks on memory ranges? Because it was quite stupid to get to the bug. When the resources just worked again I used data breakpoint to see what routine it is. Problem was that I needed to find the address where it stop to work. Maybe we really should allow writes to mem only in _RAMBASE - MEMTOPK range (of course with some exception for table stuff). - --- src/cpu/amd/car/clear_init_ram.c<-->(revision 4026) +++ src/cpu/amd/car/clear_init_ram.c<-->(working copy) @@ -6,7 +6,23 @@ <----->// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram <----->// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already <----->// so noline clear_init_ram - - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + clear_memory(_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) -_RAMBASE - DCACHE_RAM_SIZE)); +<----->//512 NOT OK - I previously though this works so I need to test MORE :/ +<----->//256 NOT OK +<----->//384 NOT OK +<----->//448 NOT OK +<----->//480 NOT OK +<----->//496 NOT OK +<----->//504 NOT OK +<----->//508 NOT OK +<----->// 768 NOT OK +<----->//896 NOT OK +<----->//960 OK +<----->//928 OK +<----->//912 NOT OK +<----->//920 NOT OK +<----->//924 OK + clear_memory(0, 924); . Oh btw the suspend/resume works, but the code needs to be fixed on some places. There is a copy_secondary_start_to_1m_below which just uses first 64KB of mem for some reason - I dont understand why it cannot be realocable to something different addr. Please check and tell. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAknKdOAACgkQ3J9wPJqZRNXabQCdFRWA4pYWDuY+VDyFROATejRC oDcAn02iYJM4fivIzcpJlQ/D9Qu4DFYE =dtVh -----END PGP SIGNATURE-----

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coreboot March 2009