coreboot March 2009

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[v2] r4030 - in trunk/coreboot-v2/src: devices northbridge/amd/amdfam10 northbridge/amd/amdk8
by svn＠coreboot.org 26 Mar '09

26 Mar '09

Author: ruik Date: 2009-03-26 22:45:26 +0100 (Thu, 26 Mar 2009) New Revision: 4030 Modified: trunk/coreboot-v2/src/devices/pci_ops.c trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c Log: During the suspend/resume programming I came to an issue that first 4KB of memory must be clear with 0s because otherwise the resources of K8 will be totally messed up. res = probe_resource(dev, 0x100 + (reg | link)); This is called with dev = NULL and this is no good for probe_resource at all. The attached patch fixes the potential problems and of course the problem itself. On one particular place was missing test if the device really exists. This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check). The rest of the patch is just very paranoid and do all checkings. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Myles Watson <mylesgw(a)gmail.com> --This line, and those below, will be igno red-- M src/devices/pci_ops.c M src/northbridge/amd/amdk8/northbridge.c M src/northbridge/amd/amdfam10/northbridge.c Modified: trunk/coreboot-v2/src/devices/pci_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-25 17:38:40 UTC (rev 4029) +++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-26 21:45:26 UTC (rev 4030) @@ -27,7 +27,13 @@ static struct bus *get_pbus(device_t dev) { - struct bus *pbus = dev->bus; + struct bus *pbus; + + if (!dev) + printk_alert("get_pbus: dev is NULL!\n"); + + pbus = dev->bus; + while(pbus && pbus->dev && !ops_pci_bus(pbus)) { if (pbus == pbus->dev->bus) { printk_alert("%s in endless loop looking for a parent " Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-25 17:38:40 UTC (rev 4029) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-26 21:45:26 UTC (rev 4030) @@ -338,6 +338,8 @@ for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) { device_t dev; dev = __f0_dev[nodeid]; + if (!dev) + continue; for(link = 0; !res && (link < 8); link++) { res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1, } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-25 17:38:40 UTC (rev 4029) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-03-26 21:45:26 UTC (rev 4030) @@ -291,9 +291,11 @@ unsigned nodeid, link; int result; res = 0; - for(nodeid = 0; !res && (nodeid < 8); nodeid++) { + for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) { device_t dev; dev = __f0_dev[nodeid]; + if (!dev) + continue; for(link = 0; !res && (link < 3); link++) { res = probe_resource(dev, 0x100 + (reg | link)); } @@ -760,14 +762,15 @@ mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; - for (i = 0; i < 8; i++) { + for (i = 0; i < FX_DEVS; i++) { uint32_t base; uint32_t hole; base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } - + if (!__f1_dev[i]) + continue; hole = pci_read_config32(__f1_dev[i], 0xf0); if(hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; @@ -834,15 +837,15 @@ limit = f1_read_config32(0x44 + (i << 3)); f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); dev = __f1_dev[i]; - hoist = pci_read_config32(dev, 0xf0); - if(hoist & 1) { - pci_write_config32(dev, 0xf0, 0); + if (dev) { + hoist = pci_read_config32(dev, 0xf0); + if(hoist & 1) { + pci_write_config32(dev, 0xf0, 0); + } else { + base = pci_read_config32(dev, 0x40 + (i << 3)); + f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); + } } - else { - base = pci_read_config32(dev, 0x40 + (i << 3)); - f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); - } - } static uint32_t hoist_memory(unsigned long hole_startk, int i) @@ -878,7 +881,7 @@ base |= (4*1024*1024)<<2; f1_write_config32(0x40 + (i<<3), base); } - else + else if (dev) { hoist = /* hole start address */ ((hole_startk << 10) & 0xff000000) + @@ -1020,7 +1023,7 @@ #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some uint32_t basek_pri; - for (i = 0; i < 8; i++) { + for (i = 0; i < FX_DEVS; i++) { uint32_t base; uint32_t basek; base = f1_read_config32(0x40 + (i << 3)); @@ -1045,7 +1048,7 @@ #endif idx = 0x10; - for(i = 0; i < 8; i++) { + for(i = 0; i < FX_DEVS; i++) { uint32_t base, limit; unsigned basek, limitk, sizek; base = f1_read_config32(0x40 + (i << 3));

1 0

[v2] r4029 - trunk/util/superiotool
by svn＠coreboot.org 25 Mar '09

25 Mar '09

Author: uwe Date: 2009-03-25 18:38:40 +0100 (Wed, 25 Mar 2009) New Revision: 4029 Modified: trunk/util/superiotool/README trunk/util/superiotool/smsc.c trunk/util/superiotool/superiotool.c Log: - List SMSC LPC47N227 runtime register block as supported. - Add missing contributor in README. - Cosmetic fixes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/README =================================================================== --- trunk/util/superiotool/README 2009-03-25 15:47:58 UTC (rev 4028) +++ trunk/util/superiotool/README 2009-03-25 17:38:40 UTC (rev 4029) @@ -89,6 +89,7 @@ Frieder Ferlemann <Frieder.Ferlemann(a)web.de> Idwer Vollering <idwer_v(a)hotmail.com> Josh Profitt <zorn169(a)gmail.com> +Michał Mirosław <mirq-linux(a)rere.qmqm.pl> Rasmus Wiman <rasmus(a)wiman.org> Robinson P. Tryon <bishop.robinson(a)gmail.com> Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2009-03-25 15:47:58 UTC (rev 4028) +++ trunk/util/superiotool/smsc.c 2009-03-25 17:38:40 UTC (rev 4029) @@ -438,7 +438,7 @@ {0x6f, "LPC47B397", { {EOT}}}, {0x74, "LPC47M182", { /* Only for LD_NUM = 0 */ - {NOLDN, NULL, + {NOLDN, NULL, {0x02,0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27, 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, {0x00,RSVD,0x00,0x74,RSVD,0x00,RSVD,0x44,MISC,0x00, @@ -655,6 +655,7 @@ uint8_t revreg) { uint8_t id, rev; + uint16_t runtime_base; const char *info = (idreg == 0x20) ? "(idregs=0x20/0x21) " : "(idregs=0x0d/0x0e) "; @@ -681,18 +682,16 @@ LDN_SEL); if (extra_dump) { - uint16_t runtime_base; switch (id) { - case 0x5a: + case 0x5a: /* LPC47N227 */ runtime_base = regval(port, 0x30) << 4; if (runtime_base) dump_io(runtime_base, 16); else - printf("Runtime Register Block not mapped on this SuperIO.\n"); - + printf("Runtime Register Block not mapped on this Super I/O.\n"); break; default: - printf("No extra registers known for this chip\n"); + printf("No extra registers known for this chip.\n"); } } @@ -708,4 +707,5 @@ void print_smsc_chips(void) { print_vendor_chips("SMSC", reg_table); + printf("SMSC LPC47N227 runtime register block\n\n"); } Modified: trunk/util/superiotool/superiotool.c =================================================================== --- trunk/util/superiotool/superiotool.c 2009-03-25 15:47:58 UTC (rev 4028) +++ trunk/util/superiotool/superiotool.c 2009-03-25 17:38:40 UTC (rev 4029) @@ -161,13 +161,13 @@ { uint16_t i; - printf("Dumping %d IO mapped registers at base 0x%04x:\n", + printf("Dumping %d I/O mapped registers at base 0x%04x:\n", length, iobase); - for (i=0; i<length; i++) - printf ("%02x ", i); + for (i = 0; i < length; i++) + printf("%02x ", i); printf("\n"); - for (i=0; i<length; i++) - printf ("%02x ", INB(iobase +i)); + for (i = 0; i < length; i++) + printf("%02x ", INB(iobase + i)); printf("\n"); }

1 0

[v2] r4028 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by svn＠coreboot.org 25 Mar '09

25 Mar '09

Author: mjones Date: 2009-03-25 16:47:58 +0100 (Wed, 25 Mar 2009) New Revision: 4028 Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h Log: The latest ucode patches for Family 10h: 9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: Zeng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000096.h 2009-03-25 15:47:58 UTC (rev 4028) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2009 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x08, 0x20, 0x05, 0x11, 0x96, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x85, 0xd4, 0x2d, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8b, 0x01, 0x00, 0x00, 0xc1, 0x08, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0x56, 0x0f, 0x00, 0x00, 0x9e, 0x0b, 0x00, 0x00, +0x70, 0x0c, 0x00, 0x00, 0x2a, 0xff, 0xff, 0x29, 0xc3, 0x5f, 0xd0, 0xc1, +0xbd, 0xff, 0xff, 0xb3, 0x0f, 0xff, 0x7e, 0xfd, 0xf6, 0x1f, 0xf8, 0x57, +0x3c, 0xbc, 0x63, 0x2d, 0x80, 0x96, 0xd6, 0x00, 0xaa, 0xff, 0xef, 0xaf, +0xe0, 0xd1, 0x9f, 0x15, 0x57, 0xef, 0xff, 0xff, 0xea, 0x87, 0x7f, 0xbf, +0x03, 0xfa, 0x0f, 0xfc, 0xfc, 0x1f, 0xbe, 0xf5, 0x00, 0xe0, 0x4a, 0x4b, +0x7f, 0xc8, 0xff, 0xf7, 0xb4, 0xf8, 0xf0, 0x2f, 0xff, 0x1f, 0xc5, 0xfe, +0xc0, 0xcf, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_0100009f.h 2009-03-25 15:47:58 UTC (rev 4028) @@ -0,0 +1,163 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2009 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +0x08, 0x20, 0x17, 0x12, 0x9f, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x8b, 0xb7, 0x4e, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x62, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x9a, 0x0b, 0x00, 0x00, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x6f, 0x58, 0x39, 0x00, 0x81, 0x3f, 0xa0, 0xd7, +0x04, 0x00, 0xfc, 0xb7, 0x0f, 0xff, 0x58, 0xf7, 0x72, 0xc0, 0xff, 0x6f, +0x3c, 0xfc, 0x03, 0xfc, 0xc0, 0x18, 0xd5, 0x00, 0x80, 0xff, 0x66, 0x3c, +0xeb, 0xc0, 0x9f, 0xd9, 0x4d, 0xee, 0xf8, 0xff, 0xff, 0x83, 0x7f, 0xa6, +0x07, 0xe8, 0xff, 0xff, 0xe8, 0x1f, 0xbe, 0xb5, 0x00, 0x60, 0x2f, 0x6a, +0x1f, 0xc0, 0x7f, 0xe0, 0xe0, 0xdf, 0xf0, 0x0f, 0x7f, 0x00, 0xff, 0x81, +0x80, 0x7f, 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1 0

my Application of GSoC
by 王清培 25 Mar '09

25 Mar '09

Hi Stepan and all, I finished the draft of my GSoC Application. I would like to check if there is something I missed or I need to add. Is there someone who can be my mentor? Please feel free to tell me. Abstract: Add USB ROM support for SeaBIOS payload which followed by Stefan or some others.The main taks may include: 1) Realize the USB support for SeaBIOS as a PCI option rom which use the libpayload USB stack. 2) Finish USB hot controller interface including UHCI/EHCI/OHCI 3) Finish the USB Mass Storage implementation 4) Add USB keyboard and mouse support for SeaBIOS 5) fix some little problems about SATA support of SeaBIOS Content. 1.Who are you? What are you studying? I am Jason Wang, the one who is a student from Peking University, China. Since I finished my EE master degree, I am working for another master degree of GIS. I also have two years Software Intern experience in AMD which still to be. 2.Why are you the right person for this task? 2 First, I am full experience with X86 Computer Architecture. Second, I am familiar with coreboot. Which means I have a strong ability of Communication with the motors of Coreboot, I have deep knowledge of SeaBIOS, and also used to boot windows 7(build 7000) with AMD DBM690T Main board. 3. Do you have any other commitments that we should know about? I am a quick learner, and also have enough time to complete the projects. More important, I have the ability to deal with difficult tasks and bugs. 4. List your C, Assembler or Java experience. (Depending on the project) I have a strong background of C language. It's my working language. I also learned Assembler Language. I can read Assembler language properly. I used to fully analysed the disassemble code of MBR. 5List your history with open source projects. Coreboot: Figured out the fast-link problem of filo-0.5. fixed some bugs of filo. Implement the SB600 Flashrom support. sucessfully booting window 7 with DBM690T by SeaBIOS. What is your preferred method of contact? (Phone, email, Skype, etc) Email:wangqingpei@hotmail.com <Email%3Awangqingpei(a)hotmail.com> Phone:(86)13426369984 -- Jason Wang Peking University

1 0

Re: [coreboot] r1157 - coreboot-v3/northbridge/amd/geodelx
by Peter Stuge 24 Mar '09

24 Mar '09

svn(a)coreboot.org wrote: > - speed = 2 * ((10000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)))); > + speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F)); .. > - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + > - (spd_byte & 0x0F))); > + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); .. > - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); > + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); .. .. > - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); > + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); .. > - dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); > + dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); Anyone else thinks this calls for a macro? Maybe even a generic SPD macro? //Peter

2 3

[PATCH] fix object/driver confusion of all northbridge code
by Stefan Reinauer 24 Mar '09

24 Mar '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

5 9

Asus A8N-SLI Deluxe_support
by Matt Price 24 Mar '09

24 Mar '09

> Oliver Niesner wrote: > > Hi, all > > > > I'am very new to all the coreboot stuff and i need some info - > > hope someone can help. > > > > I have an ASUS A8N-SLI-Deluxe mainboard. > > According to the list on coreboot.org the A8V-E Deluxe is supported, but > > i found nothing about A8N-SLI-Deluxe. > > Has somebody info about the support for that mainboard? > > > > Thanks, > > > > Oliver > > > Sorry for my blindness, i overlooked it!! > Will be more careful in the future. > > Oliver > Oliver, I can't see the a8n-sli deluxe anywhere in the 'supported boards' list here: http://www.coreboot.org/Supported_Motherboards . where did you find the status? I have also seen lots of emails from 2006&2007 from people who seemed to have been working on it, but none of them reports a resolution. If you (or anyone else) has more info i'd like to hear it (i have this board too). thanks,matt -- Matt Price matt.price(a)utoronto.ca

1 0

[v2] r4027 - in trunk/coreboot-v2/src/northbridge: amd/amdfam10 amd/amdk8 amd/gx1 amd/gx2 amd/lx intel/i440bx intel/i82810 intel/i82830 via/cn700 via/vt8601 via/vt8623
by svn＠coreboot.org 24 Mar '09

24 Mar '09

Author: stepan Date: 2009-03-24 13:28:44 +0100 (Tue, 24 Mar 2009) New Revision: 4027 Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb Log: Every object file with a struct pci_driver ... __pci_driver needs to be marked as "driver" instead of "object" in order to get the init code actually executed. This patch fixes up all northbridges that did not do this before. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -27,7 +27,7 @@ config chip.h end -object northbridge.o +driver northbridge.o driver misc_control.o if HAVE_ACPI_TABLES Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -8,7 +8,7 @@ config chip.h end -object northbridge.o +driver northbridge.o driver misc_control.o makerule raminit_test Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -1,2 +1,2 @@ config chip.h -object northbridge.o +driver northbridge.o Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -1,5 +1,5 @@ config chip.h -object northbridge.o +driver northbridge.o object northbridgeinit.o object chipsetinit.o object grphinit.o Modified: trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/amd/lx/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -1,4 +1,4 @@ config chip.h -object northbridge.o +driver northbridge.o object northbridgeinit.o object grphinit.o Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -19,4 +19,4 @@ ## config chip.h -object northbridge.o +driver northbridge.o Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -19,4 +19,4 @@ ## config chip.h -object northbridge.o +driver northbridge.o Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -19,4 +19,4 @@ ## config chip.h -object northbridge.o +driver northbridge.o Modified: trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/via/cn700/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -20,6 +20,6 @@ config chip.h object vgabios.o -object northbridge.o +driver northbridge.o driver agp.o driver vga.o Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -1,2 +1,2 @@ config chip.h -object northbridge.o +driver northbridge.o Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb 2009-03-23 17:43:12 UTC (rev 4026) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/Config.lb 2009-03-24 12:28:44 UTC (rev 4027) @@ -1,2 +1,2 @@ config chip.h -object northbridge.o +driver northbridge.o

1 0

Custom VGA Driver - Help
by Joseph Smith 24 Mar '09

24 Mar '09

Hello, I am trying to setup a custom vga driver to run code before and after the vga rom executes. It builds and runs ok but I can't seem to get any of my output to show (yes my debug level is set 9). Do vga option roms not use the device ops (pci_dev_init())? Am I doing something wrong(patch and bootlog attached)? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 4

not really new news ... but ...
by ron minnich 23 Mar '09

23 Mar '09

http://it.slashdot.org/article.pl?sid=09/03/23/1248214&art_pos=10 so they infected a commercial bios. And they used flashrom, it appears. :-) I think I first started warning people about this 10 years ago, but I could not get interest. They did not believe it could be done, then I showed them some examples, and the reaction was -- literally in one case -- "I don't want to know". . Expect the usual level of clue you get on slashdot in the comments section :-) ron

2 1

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coreboot March 2009