coreboot March 2009

coreboot@coreboot.org

64 participants
316 discussions

[patch][v2]:fam10 microcode
by Bao, Zheng 01 Jul '09

01 Jul '09

Attached are the latest ucode patches for Family 10h: 9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: <zheng.bao(a)amd.com> Zheng

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Bug in cache_as_ram.inc and cache_as_ram_post.c
by Thomas Jourdan 01 Jul '09

01 Jul '09

Hi guys I don't know how usefull is it but there is a bug in cache_as_ram.inc and cache_as_ram_post.c for the 6fx intel processors. The code disable / enable the prefetcher in IA32_MISC_ENABLES MSR register. cache_as_ram.inc : /* Disable prefetchers */ movl $0x01a0, %eax rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx wrmsr should be movl $0x01a0, %ecx Same thing in cache_as_ram_post.c /* Enable prefetchers */ "movl $0x01a0, %eax\n" "rdmsr\n" "andl $~((1 << 9) | (1 << 19)), %eax\n" "andl $~((1 << 5) | (1 << 7)), %edx\n" "wrmsr\n" should be "movl $0x01a0, %ecx\n" Regards, Thomas

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#122: Add links to logs of successful builds on the QA pages
by coreboot 19 Jun '09

19 Jun '09

#122: Add links to logs of successful builds on the QA pages ------------------------------------+--------------------------------------- Reporter: hailfinger | Owner: stepan Type: enhancement | Status: new Priority: major | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- http://qa.coreboot.org/log_buildrev.php?revision=3962 and other build status pages contain only links to failing builds. Please add links to successful logs as well. Benefits: * easier comparisons between failing and successful builds * the ability to look for warnings in the compiler output -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/122> coreboot <http://www.coreboot.org/>

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#100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e.
by coreboot 19 Jun '09

19 Jun '09

#100: flashrom: Change start/end -s and -e to -S and -E, and change erase -E to -e. -------------------------------------+-------------------------------------- Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: usability cli options | Dependencies: Patchstatus: patch needs review | -------------------------------------+-------------------------------------- -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/100> coreboot <http://www.coreboot.org/>

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[flashrom] Asus A7N8X-E Support.
by Luc Verhaegen 22 May '09

22 May '09

With the discussion of the board_enables table, i ended up looking at the flashrom page on coreboot.org and spotted a bunch of boards that are known to not work. The first one i looked at was the aforementioned and this here is what is needed for the flash enable of that board. { uint8_t tmp; pci_write_byte(dev, 0x92, 0); tmp = pci_read_byte(dev, 0x6D); tmp |= 0x01; pci_write_byte(dev, 0x6D, tmp); } While it seems that the second operation seems to match both ck804 and mcp55 chip enables, this is not true. The device used is 0:01.0 (ISA bridge) and not 0:01.1 (SMB controller). I googled, but could not find a report to the coreboot (or linuxbios) list of this board being tested. Does anyone remember who reported this as broken? Luc Verhaegen.

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[patch] flashrom: resending my patch about SPI/LPC conflicts
by Bao, Zheng 18 May '09

18 May '09

Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> This patch is about flashrom running on dbm690t. It was sent several months ago and hasn't got any response yet. Now it deals with 3 problems. 1. Fix the bug that the flashrom would hang if there is not SPI chip. A timeout detection was added. 2. We only access LPC ROM if we boot via LPC ROM. And only SPI ROM if we boot via SPI ROM. Doing crossly is not allowed. Anybody has better idea? 3. When we read/write SPI, we use memory read/write instead of sending SPI command. Joe

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Flashrom problems on SB600
by Tiago Marques 16 May '09

16 May '09

Hi all, I tried to run flashrom on an ECS AMD690GM-M2 motherboard and it detects the SB600 southbridge and enables flash writing but hangs before trying to find the flash/EEPROM chip. The system itself doesn't hang, just flashrom that stays stalled apparently waiting for something. Any ideas? Best regards, Tiago Marques

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#118: Flashrom Makefile improvements
by coreboot 15 May '09

15 May '09

#118: Flashrom Makefile improvements ----------------------------------+----------------------------------------- Reporter: spooky85@… | Owner: somebody Type: task | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- hi guys, i wrote a small Makefile patch for flashrom. a few improvements and i corrected LD/C-FLAGS usage and link order e.g. for --as-needed. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/118> coreboot <http://www.coreboot.org/>

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Re: [coreboot] Tyan Product Listings
by joelr＠tyan.com 07 May '09

07 May '09

Stefan, Here is a list of products we have tested thus far and have found will work just fine with FlashROM Motherboard Flash Utility Support Spreadsheet Bios Chip Vendor Bios Chip Part # Motherboard Linux Flash Utility FlashROM (v3332) FlashROM (v3332) OS Support 32-bit Distributions 64-bit Distributions S5377 Yes SST 49LF008A S5376G2NR Yes Yes SST 49LF008A S5376WAG2NR Yes Yes SST 49LF008A S5375 Yes SST 49LF008A S5375-1U Yes SST 49LF008A S5220 Yes SST 49LF008A S5211 Yes Yes SST 49LF008A S5211-1U Yes Yes SST 49LF008A S5197 Yes SST 49LF008A S5191 Yes SST 49LF008A S5180 Yes SST 49LF008A S3095 Yes SST 49LF008A S2882 Yes Yes PMC 49LF004T S2882-D Yes Yes PMC 49LF004T S2881 Yes Yes PMC 49LF004T Our process is still ongoing so we will have new updates periodically to help include new FlashROM versions as well as new Tyan motherboards to this listing. Our plans are to go through our current product listings and see if we can get FlashROM to work on them. We want to be able to add something other than AMI, Award or Phoenix as a flash utility for our customers. We have been pleased with what the FlashROM utility does and we are working on further validation with this particular utility. Thanks again for your reply and we will continue to stay in touch as new updates are made available. Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 ________________________________ From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Tuesday, August 26, 2008 5:39 PM To: joelr (joelr - TYANUS) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Tyan Product Listings Dear Joel Robertson, thank you very much for your interest in coreboot and flashrom! If a specific mainboard was tested and is working, please send a mail containing the mainboard and the flash chip you used, and what you tested on that mainboard+flash combination (verify, read, erase, write) to either coreboot(a)coreboot.rom or flashrom(a)coreboot.rom. Then we can update the web pages accordingly. In case you wish to have new, currently unsupported mainboards supported by flashrom, let us know here, too. I think we can help. Best regards, Stefan Reinauer joelr(a)tyan.com wrote: To Whomever it may concern: We would like to update the motherboard listings that support the FlashROM software. We have additional motherboards that we would like to have listed but we need clarification on the process of how to go about this. We have verified that the FlashROM does work in a 32-bit and 64-bit linux environment. We have also made sure that it will verify, read, erase and write a bios chip successfully. Please let us know what we need to update the current support listings on the coreboot.org site. Thanks, Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 -- coreboot mailing list coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg * HRB 7656 Geschäftsführer: Stefan Reinauer * Ust-IdNr.: DE245674866

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[PATCH] First support for HP DL145 G3
by Mondrian Nuessle 22 Apr '09

22 Apr '09

Hi everybody, I prepared an initial set of patches to support the HP DL145 G3 server, which is a Broadcom HT-1000/HT-2100 based Socket F machine. The current status of the port is: * we have serial output (using the serverengines pilot chip on the board, see attached pilot_superio.patch) * CPU and memory gets initialized * on-board eth0 is working * SATA is working * the on-board graphic was not tested (not important for a server and the graphics sucks anyway...) * USB and PS2 work * no ACPI * I remember that I could also use a PCIe card, see attached bcm21000.patch * HTX card does work. * Earlier problems we had in respect to timer interrupt are not there anymore. * the hp_dl145_g3.patch includes the mainboard and the target dirs BUT: * if I coldboot, the CPUs are only running at 1 GHz and not with 2.6 GHz as they should... * if we boot the factory BIOS and then perform a warm-reset into Coreboot, the CPUs run with 2.6 GHz. I hope someone on the list can help. * There are also some more problems with the HT-1000 (aka bcm5785) southbridge: - if I activate IDE in bcm5785_early_setup.c, the machine will freeze shortly after being completely booted - if I activate the second IOAPIC (line 179 in bcm5785_early_setup.c), my linux boot hangs when starting udevd... - with both features disabled (see attached bcm5785_noide.patch), the machine boots and does not crash, of course PATA drives are not available. To boot the machine, I tested FILO. The on-board SATA adapter uses a class id of 0x104 in sata mode (which we use). FILO does not accept this class ID; I prepared a patch that adds this class ID to the respective if statement in driver/ide.c. FILO does then boot from SATA without any problems (see attached filo_dl145_sata.patch). I hope this gets you started Samuel, and I hope the list can provide some insight regarding the CPU frequency problem. Regards, Mondrian -- Dr. Mondrian Nuessle Phone: +49 621 181 2717 University of Heidelberg Fax: +49 621 181 2713 Computer Architecture Group mailto:nuessle@uni-hd.de http://ra.ziti.uni-heidelberg.de

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coreboot March 2009