coreboot November 2009

coreboot@coreboot.org

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232 discussions

[PATCH 1/9] Fix cpuflag in mptable (| has higher priority than ?:)
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mptable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 3945d2e..805fe1b 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -60,7 +60,7 @@ mptable_init(void) cpu->apicver = 0x11; /* cpu flags: enabled, bootstrap cpu */ if (i < CountCPUs) - cpu->cpuflag = 1 | (i == 0) ? 2 : 0; + cpu->cpuflag = 1 | ((i == 0) ? 2 : 0); else cpu->cpuflag = 0; if (cpuid_signature) { -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0002-Only-add-the-first-logical-CPU-in-each-physical-CPU.pat"; filename*1="ch"

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build service results for r4914
by coreboot information 05 Nov '09

05 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4914 to the coreboot repository. This caused the following changes: Change Log: fix Qemu Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4913
by coreboot information 05 Nov '09

05 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4913 to the coreboot repository. This caused the following changes: Change Log: http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html This function is not called right now,... Please step in and fix up your code, folks. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4913&device=qemu-x86&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4914 - trunk/util/x86emu
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 12:44:50 +0000 (Thu, 05 Nov 2009) New Revision: 4914 Modified: trunk/util/x86emu/x86_interrupts.c Log: fix Qemu Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/x86emu/x86_interrupts.c =================================================================== --- trunk/util/x86emu/x86_interrupts.c 2009-11-05 12:38:34 UTC (rev 4913) +++ trunk/util/x86emu/x86_interrupts.c 2009-11-05 12:44:50 UTC (rev 4914) @@ -73,6 +73,9 @@ short devindex; unsigned char bus; struct device *dev; + u32 dword; + u16 word; + u8 byte, reg; switch (func) { case PCIBIOS_CHECK: @@ -115,11 +118,6 @@ case PCIBIOS_WRITECONFDWORD: case PCIBIOS_WRITECONFWORD: case PCIBIOS_WRITECONFBYTE: - unsigned long dword; - unsigned short word; - unsigned char byte; - unsigned char reg; - devfn = regs->ebx & 0xff; bus = regs->ebx >> 8; reg = regs->edi;

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[v2] r4913 - in trunk/src: include/pc80 pc80
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 12:38:34 +0000 (Thu, 05 Nov 2009) New Revision: 4913 Added: trunk/src/include/pc80/i8254.h trunk/src/pc80/i8254.c Modified: trunk/src/pc80/Config.lb trunk/src/pc80/Makefile.inc Log: http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html This function is not called right now,... Please step in and fix up your code, folks. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/include/pc80/i8254.h =================================================================== --- trunk/src/include/pc80/i8254.h (rev 0) +++ trunk/src/include/pc80/i8254.h 2009-11-05 12:38:34 UTC (rev 4913) @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef PC80_I8254_H +#define PC80_I8254_H + +/* Ports for the 8254 timer chip */ +#define TIMER0_PORT 0x40 +#define TIMER1_PORT 0x41 +#define TIMER2_PORT 0x42 +#define TIMER_MODE_PORT 0x43 + +/* Meaning of the mode bits */ +#define TIMER0_SEL 0x00 +#define TIMER1_SEL 0x40 +#define TIMER2_SEL 0x80 +#define READBACK_SEL 0xC0 + +#define LATCH_COUNT 0x00 +#define LOBYTE_ACCESS 0x10 +#define HIBYTE_ACCESS 0x20 +#define WORD_ACCESS 0x30 + +#define MODE0 0x00 +#define MODE1 0x02 +#define MODE2 0x04 +#define MODE3 0x06 +#define MODE4 0x08 +#define MODE5 0x0A + +#define BINARY_COUNT 0x00 +#define BCD_COUNT 0x01 + +/* Timers tick over at this rate */ +#define TICKS_PER_MS 1193 + +/* Parallel Peripheral Controller Port B */ +#define PPC_PORTB 0x61 + +/* Meaning of the port bits */ +#define PPCB_T2OUT 0x20 /* Bit 5 */ +#define PPCB_SPKR 0x02 /* Bit 1 */ +#define PPCB_T2GATE 0x01 /* Bit 0 */ + +#endif Modified: trunk/src/pc80/Config.lb =================================================================== --- trunk/src/pc80/Config.lb 2009-11-05 10:02:59 UTC (rev 4912) +++ trunk/src/pc80/Config.lb 2009-11-05 12:38:34 UTC (rev 4913) @@ -5,7 +5,6 @@ object mc146818rtc.o object isa-dma.o object i8259.o -#object udelay_timer2.o CONFIG_UDELAY_TIMER2 if CONFIG_UDELAY_IO object udelay_io.o Modified: trunk/src/pc80/Makefile.inc =================================================================== --- trunk/src/pc80/Makefile.inc 2009-11-05 10:02:59 UTC (rev 4912) +++ trunk/src/pc80/Makefile.inc 2009-11-05 12:38:34 UTC (rev 4913) @@ -1,7 +1,6 @@ obj-y += mc146818rtc.o obj-y += isa-dma.o obj-y += i8259.o -#obj-y += udelay_timer2.o CONFIG_UDELAY_TIMER2 obj-$(CONFIG_UDELAY_IO) += udelay_io.o obj-y += keyboard.o Added: trunk/src/pc80/i8254.c =================================================================== --- trunk/src/pc80/i8254.c (rev 0) +++ trunk/src/pc80/i8254.c 2009-11-05 12:38:34 UTC (rev 4913) @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <pc80/i8254.h> +#include <console/console.h> + +/* Initialize i8254 timers */ + +void setup_i8254(void) +{ + /* Timer 0 (taken from biosemu) */ + outb(TIMER0_SEL|WORD_ACCESS|MODE3|BINARY_COUNT, TIMER_MODE_PORT); + outb(0x00, TIMER0_PORT); + outb(0x00, TIMER0_PORT); + + /* Timer 1 */ + outb(TIMER1_SEL|LOBYTE_ACCESS|MODE3|BINARY_COUNT, TIMER_MODE_PORT); + outb(0x12, TIMER1_PORT); +} + +#ifdef CONFIG_UDELAY_TIMER2 +static void load_timer2(unsigned int ticks) +{ + /* Set up the timer gate, turn off the speaker */ + outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); + outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT); + outb(ticks & 0xFF, TIMER2_PORT); + outb(ticks >> 8, TIMER2_PORT); +} + + +void udelay(int usecs) +{ + load_timer2((usecs*TICKS_PER_MS)/1000); + while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) + ; +} +#endif

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build service results for r4912
by coreboot information 05 Nov '09

05 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 4912 to the coreboot repository. This caused the following changes: Change Log: If the coreboot and filo overlap, it will "slice off" a piece at the "beginning" or "end". In the beginning case, a new segment is inserted before the current one. But the ptr will move forward and doesn't seem to have any other chance to process the "new" segment. ptr ---------+ move ---> | V +--------+ +--------+ | | | | | new | <---> |current | <---> ..... | | | | +--------+ +--------+ Now we change the ptr to the previous one and restart the loop. The new and current segment will both be processed. Even if the current segment is done twice, no new segment will come up and ptr will move forward as we expect. +----------------ptr move ---> | V +--------+ +--------+ +--------+ | | | | | | | prev | <---> | new | <---> |current | <---> ..... | | | | | | +--------+ +--------+ +--------+ It is tested and fixes the crashing on my AMD Family 10 board. Some trailing whitespaces were deleted. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4912&device=qemu-x86&vendo… If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4912 - trunk/src/boot
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: zbao Date: 2009-11-05 10:02:59 +0000 (Thu, 05 Nov 2009) New Revision: 4912 Modified: trunk/src/boot/selfboot.c Log: If the coreboot and filo overlap, it will "slice off" a piece at the "beginning" or "end". In the beginning case, a new segment is inserted before the current one. But the ptr will move forward and doesn't seem to have any other chance to process the "new" segment. ptr ---------+ move ---> | V +--------+ +--------+ | | | | | new | <---> |current | <---> ..... | | | | +--------+ +--------+ Now we change the ptr to the previous one and restart the loop. The new and current segment will both be processed. Even if the current segment is done twice, no new segment will come up and ptr will move forward as we expect. +----------------ptr move ---> | V +--------+ +--------+ +--------+ | | | | | | | prev | <---> | new | <---> |current | <---> ..... | | | | | | +--------+ +--------+ +--------+ It is tested and fixes the crashing on my AMD Family 10 board. Some trailing whitespaces were deleted. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/boot/selfboot.c =================================================================== --- trunk/src/boot/selfboot.c 2009-11-05 09:09:20 UTC (rev 4911) +++ trunk/src/boot/selfboot.c 2009-11-05 10:02:59 UTC (rev 4912) @@ -60,7 +60,7 @@ struct verify_callback { struct verify_callback *next; - int (*callback)(struct verify_callback *vcb, + int (*callback)(struct verify_callback *vcb, Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head); unsigned long desc_offset; unsigned long desc_addr; @@ -88,7 +88,7 @@ return (void *) -1; } -/* The problem: +/* The problem: * Static executables all want to share the same addresses * in memory because only a few addresses are reliably present on * a machine, and implementing general relocation is hard. @@ -97,16 +97,16 @@ * - Allocate a buffer the size of the coreboot image plus additional * required space. * - Anything that would overwrite coreboot copy into the lower part of - * the buffer. + * the buffer. * - After loading an ELF image copy coreboot to the top of the buffer. * - Then jump to the loaded image. - * + * * Benefits: * - Nearly arbitrary standalone executables can be loaded. * - Coreboot is preserved, so it can be returned to. * - The implementation is still relatively simple, * and much simpler than the general case implemented in kexec. - * + * */ static unsigned long bounce_size, bounce_buffer; @@ -138,7 +138,7 @@ msize = unpack_lb64(mem->map[i].size); mend = mstart + msize; tbuffer = mend - lb_size; - if (tbuffer < buffer) + if (tbuffer < buffer) continue; buffer = tbuffer; } @@ -190,10 +190,10 @@ mstart = unpack_lb64(mem->map[i].start); mend = mstart + unpack_lb64(mem->map[i].size); printk_err(" [0x%016lx, 0x%016lx) %s\n", - (unsigned long)mstart, - (unsigned long)mend, + (unsigned long)mstart, + (unsigned long)mend, (mtype == LB_MEM_RAM)?"RAM":"Reserved"); - + } return 0; } @@ -211,25 +211,27 @@ return !((end <= lb_start) || (start >= lb_end)); } -static void relocate_segment(unsigned long buffer, struct segment *seg) +static int relocate_segment(unsigned long buffer, struct segment *seg) { /* Modify all segments that want to load onto coreboot * to load onto the bounce buffer instead. */ - unsigned long start, middle, end; + /* ret: 1 : A new segment is inserted before the seg. + * 0 : A new segment is inserted after the seg, or no new one. */ + unsigned long start, middle, end, ret = 0; - printk_spew("lb: [0x%016lx, 0x%016lx)\n", + printk_spew("lb: [0x%016lx, 0x%016lx)\n", lb_start, lb_end); /* I don't conflict with coreboot so get out of here */ if (!overlaps_coreboot(seg)) - return; + return 0; start = seg->s_dstaddr; middle = start + seg->s_filesz; end = start + seg->s_memsz; - printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", + printk_spew("segment: [0x%016lx, 0x%016lx, 0x%016lx)\n", start, middle, end); if (seg->compression == CBFS_COMPRESS_NONE) { @@ -265,15 +267,17 @@ /* compute the new value of start */ start = seg->s_dstaddr; - - printk_spew(" early: [0x%016lx, 0x%016lx, 0x%016lx)\n", - new->s_dstaddr, + + printk_spew(" early: [0x%016lx, 0x%016lx, 0x%016lx)\n", + new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); + + ret = 1; } - - /* Slice off a piece at the end - * that doesn't conflict with coreboot + + /* Slice off a piece at the end + * that doesn't conflict with coreboot */ if (end > lb_end) { unsigned long len = lb_end - start; @@ -301,29 +305,31 @@ seg->phdr_next->phdr_prev = new; seg->phdr_next = new; - printk_spew(" late: [0x%016lx, 0x%016lx, 0x%016lx)\n", - new->s_dstaddr, + printk_spew(" late: [0x%016lx, 0x%016lx, 0x%016lx)\n", + new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); } } /* Now retarget this segment onto the bounce buffer */ - /* sort of explanation: the buffer is a 1:1 mapping to coreboot. + /* sort of explanation: the buffer is a 1:1 mapping to coreboot. * so you will make the dstaddr be this buffer, and it will get copied * later to where coreboot lives. */ seg->s_dstaddr = buffer + (seg->s_dstaddr - lb_start); - printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", - seg->s_dstaddr, - seg->s_dstaddr + seg->s_filesz, + printk_spew(" bounce: [0x%016lx, 0x%016lx, 0x%016lx)\n", + seg->s_dstaddr, + seg->s_dstaddr + seg->s_filesz, seg->s_dstaddr + seg->s_memsz); + + return ret; } static int build_self_segment_list( - struct segment *head, + struct segment *head, struct lb_memory *mem, struct cbfs_payload *payload, u32 *entry) { @@ -345,7 +351,7 @@ case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: - printk_debug(" %s (compression=%x)\n", + printk_debug(" %s (compression=%x)\n", segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", ntohl(segment->compression)); new = malloc(sizeof(*new)); @@ -394,7 +400,7 @@ segment++; - // FIXME: Explain what this is + // FIXME: Explain what this is for(ptr = head->next; ptr != head; ptr = ptr->next) { if (new->s_srcaddr < ntohl((u32) segment->load_addr)) break; @@ -422,7 +428,7 @@ struct cbfs_payload *payload) { struct segment *ptr; - + unsigned long bounce_high = lb_end; for(ptr = head->next; ptr != head; ptr = ptr->next) { if (!overlaps_coreboot(ptr)) continue; @@ -443,10 +449,13 @@ unsigned char *dest, *src; printk_debug("Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); - + /* Modify the segment to load onto the bounce_buffer if necessary. */ - relocate_segment(bounce_buffer, ptr); + if (relocate_segment(bounce_buffer, ptr)) { + ptr = (ptr->prev)->prev; + continue; + } printk_debug("Post relocation: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -454,7 +463,7 @@ /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); src = (unsigned char *)(ptr->s_srcaddr); - + /* Copy data from the initial buffer */ if (ptr->s_filesz) { unsigned char *middle, *end; @@ -496,7 +505,7 @@ if (middle < end) { printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", (unsigned long)middle, (unsigned long)(end - middle)); - + /* Zero the extra bytes */ memset(middle, 0, end - middle); }

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build service results for r4911
by coreboot information 05 Nov '09

05 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4911 to the coreboot repository. This caused the following changes: Change Log: Get the passed in Bus/Device/Function from the correct location on the stack. Signed-off-by: Mark Marshall <mark.marshall(a)csr.com> Clarified the comment and Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4911&device=qemu-x86&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4910
by coreboot information 05 Nov '09

05 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4910 to the coreboot repository. This caused the following changes: Change Log: Use more care when implementing the PCI BIOS functions. The READ_CONF and WRITE_CONF functions would both do the wrong thing if the passed in BDF was not found. We should return and error to the caller, but not stop running the option ROM. Signed-off-by: Mark Marshall <mark.marshall(a)csr.com> I slightly reworked the patch: The 'CHECK' function seemed to be both wrong code and the wrong number. In fact the CHECK function was given the function number of the "Microsoft Real-Time Compression Interface". Since this is definitely wrong I removed the code. Dropped some unneeded scopes, too, to make the code easier to read. Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4910&device=qemu-x86&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH 8/8] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/config.h | 1 + src/smp.c | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index f2c08ff..e9d63e7 100644 --- a/src/config.h +++ b/src/config.h @@ -191,5 +191,6 @@ /* Options for running on the Virtutech Simics x86-440bx machine model */ #define VIRTUTECH_PC_SHADOW 0 +#define USE_CMOS_BIOS_SMP_COUNT 1 #endif // config.h diff --git a/src/smp.c b/src/smp.c index b0852f8..caec5f1 100644 --- a/src/smp.c +++ b/src/smp.c @@ -105,7 +105,7 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) { + if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) { msleep(10); } else { u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); -- 1.6.2.5 --------------010303080000070006010407--

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coreboot November 2009