coreboot November 2009

coreboot@coreboot.org

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232 discussions

[PATCH 8/9] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/config.h | 1 + src/smp.c | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index f2c08ff..e9d63e7 100644 --- a/src/config.h +++ b/src/config.h @@ -191,5 +191,6 @@ /* Options for running on the Virtutech Simics x86-440bx machine model */ #define VIRTUTECH_PC_SHADOW 0 +#define USE_CMOS_BIOS_SMP_COUNT 1 #endif // config.h diff --git a/src/smp.c b/src/smp.c index b0852f8..caec5f1 100644 --- a/src/smp.c +++ b/src/smp.c @@ -105,7 +105,7 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) { + if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) { msleep(10); } else { u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); -- 1.6.2.5 --------------020508030901070003090208--

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[PATCH 7/8] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/config.h | 3 +++ src/shadow.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 0 deletions(-) diff --git a/src/config.h b/src/config.h index 3033133..f2c08ff 100644 --- a/src/config.h +++ b/src/config.h @@ -189,4 +189,7 @@ #define DEBUG_HDL_pmm 1 #define DEBUG_thread 1 +/* Options for running on the Virtutech Simics x86-440bx machine model */ +#define VIRTUTECH_PC_SHADOW 0 + #endif // config.h diff --git a/src/shadow.c b/src/shadow.c index f0f97c5..4b7f15c 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -9,6 +9,7 @@ #include "pci.h" // pci_config_writeb #include "config.h" // CONFIG_* #include "pci_ids.h" // PCI_VENDOR_ID_INTEL +#include "ioport.h" // outb // Test if 'addr' is in the range from 'start'..'start+size' #define IN_RANGE(addr, start, size) ({ \ @@ -21,6 +22,40 @@ // On the emulators, the bios at 0xf0000 is also at 0xffff0000 #define BIOS_SRC_ADDR 0xffff0000 +#if VIRTUTECH_PC_SHADOW + +#define Read_Only 1 +#define Write_Only 2 +#define Read_Write 3 + +static void modify_shadow(unsigned long start, unsigned long len, int mode) +{ + int start_loc = ((int)(start >> 10) - 640) >> 1; + int len_remaining = len >> 11; + int i; + for (i = 0; i < len_remaining; i++) { + outb(start_loc + i, 0xfff4); + if (mode == Read_Only) { + outb(1, 0xfff5); + } else if (mode == Read_Write) { + outb(3, 0xfff5); + } else if (mode == Write_Only) { + outb(2, 0xfff5); + } else { + outb(0, 0xfff5); + } + } +} + +static void +__copy_bios(void) +{ + // Copy bios. + memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); +} + +#else + // Enable shadowing and copy bios. static void __make_bios_writable(u16 bdf) @@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf) memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); } +#endif // VIRTUTECH_PC_SHADOW + // Make the 0xc0000-0x100000 area read/writable. void make_bios_writable() @@ -68,6 +105,19 @@ make_bios_writable() dprintf(3, "enabling shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + /* Read (and execute) from PCI, write to RAM */ + modify_shadow(0xf0000, 0x10000, Write_Only); + + /* Run the copy from the high address to avoid simulator flushes after each + write (the flushes ruin performance) */ + u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR; + void (*func)(void) = (void*)pos; + func(); + + /* Keep BIOS read/write */ + modify_shadow(0xf0000, 0x10000, Read_Write); +#else // Locate chip controlling ram shadowing. int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { @@ -88,6 +138,7 @@ make_bios_writable() } // Ram already present - just enable writes __make_bios_writable(bdf); +#endif } // Make the BIOS code segment area (0xf0000) read-only. @@ -99,6 +150,9 @@ make_bios_readonly() dprintf(3, "locking shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + modify_shadow(0xf0000, 0x10000, Read_Only); +#else int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { dprintf(1, "Unable to lock ram - bridge not found\n"); @@ -122,4 +176,5 @@ make_bios_readonly() // Write protect 0xf0000-0x100000 pci_config_writeb(bdf, 0x59, 0x10); +#endif } -- 1.6.2.5 --------------010303080000070006010407 Content-Type: text/x-patch; name="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc"; filename*1="h"

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[PATCH 7/9] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/config.h | 3 +++ src/shadow.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 0 deletions(-) diff --git a/src/config.h b/src/config.h index 3033133..f2c08ff 100644 --- a/src/config.h +++ b/src/config.h @@ -189,4 +189,7 @@ #define DEBUG_HDL_pmm 1 #define DEBUG_thread 1 +/* Options for running on the Virtutech Simics x86-440bx machine model */ +#define VIRTUTECH_PC_SHADOW 0 + #endif // config.h diff --git a/src/shadow.c b/src/shadow.c index f0f97c5..4b7f15c 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -9,6 +9,7 @@ #include "pci.h" // pci_config_writeb #include "config.h" // CONFIG_* #include "pci_ids.h" // PCI_VENDOR_ID_INTEL +#include "ioport.h" // outb // Test if 'addr' is in the range from 'start'..'start+size' #define IN_RANGE(addr, start, size) ({ \ @@ -21,6 +22,40 @@ // On the emulators, the bios at 0xf0000 is also at 0xffff0000 #define BIOS_SRC_ADDR 0xffff0000 +#if VIRTUTECH_PC_SHADOW + +#define Read_Only 1 +#define Write_Only 2 +#define Read_Write 3 + +static void modify_shadow(unsigned long start, unsigned long len, int mode) +{ + int start_loc = ((int)(start >> 10) - 640) >> 1; + int len_remaining = len >> 11; + int i; + for (i = 0; i < len_remaining; i++) { + outb(start_loc + i, 0xfff4); + if (mode == Read_Only) { + outb(1, 0xfff5); + } else if (mode == Read_Write) { + outb(3, 0xfff5); + } else if (mode == Write_Only) { + outb(2, 0xfff5); + } else { + outb(0, 0xfff5); + } + } +} + +static void +__copy_bios(void) +{ + // Copy bios. + memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); +} + +#else + // Enable shadowing and copy bios. static void __make_bios_writable(u16 bdf) @@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf) memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); } +#endif // VIRTUTECH_PC_SHADOW + // Make the 0xc0000-0x100000 area read/writable. void make_bios_writable() @@ -68,6 +105,19 @@ make_bios_writable() dprintf(3, "enabling shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + /* Read (and execute) from PCI, write to RAM */ + modify_shadow(0xf0000, 0x10000, Write_Only); + + /* Run the copy from the high address to avoid simulator flushes after each + write (the flushes ruin performance) */ + u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR; + void (*func)(void) = (void*)pos; + func(); + + /* Keep BIOS read/write */ + modify_shadow(0xf0000, 0x10000, Read_Write); +#else // Locate chip controlling ram shadowing. int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { @@ -88,6 +138,7 @@ make_bios_writable() } // Ram already present - just enable writes __make_bios_writable(bdf); +#endif } // Make the BIOS code segment area (0xf0000) read-only. @@ -99,6 +150,9 @@ make_bios_readonly() dprintf(3, "locking shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + modify_shadow(0xf0000, 0x10000, Read_Only); +#else int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { dprintf(1, "Unable to lock ram - bridge not found\n"); @@ -122,4 +176,5 @@ make_bios_readonly() // Write protect 0xf0000-0x100000 pci_config_writeb(bdf, 0x59, 0x10); +#endif } -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0008-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc"; filename*1="h"

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[PATCH 6/8] Properly mask value for MTRR mask.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mtrr.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mtrr.c b/src/mtrr.c index a9cd5f7..6bd0dba 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -29,7 +29,7 @@ void mtrr_setup(void) if (CONFIG_COREBOOT) return; - u32 eax, ebx, ecx, cpuid_features; + u32 eax, ebx, ecx, edx, cpuid_features; cpuid(1, &eax, &ebx, &ecx, &cpuid_features); if (!(cpuid_features & CPUID_MTRR)) return; @@ -73,6 +73,16 @@ void mtrr_setup(void) wrmsr_smp(MSR_MTRRfix4K_F8000, 0); /* Mark 3.5-4GB as UC, anything not specified defaults to WB */ wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0); - wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800); + + int phys_bits = 36; + cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); + if (eax >= 0x80000008) { + /* Get physical bits from leaf 0x80000008 (if available) */ + cpuid(0x80000008u, &eax, &ebx, &ecx, &edx); + phys_bits = eax & 0xff; + } + u64 phys_mask = ((1ull << phys_bits) - 1); + wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800); + wrmsr_smp(MSR_MTRRdefType, 0xc06); } -- 1.6.2.5 --------------010303080000070006010407 Content-Type: text/x-patch; name="0007-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0007-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.pa"; filename*1="tch"

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[PATCH 6/9] Properly mask value for MTRR mask.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mtrr.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mtrr.c b/src/mtrr.c index a9cd5f7..6bd0dba 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -29,7 +29,7 @@ void mtrr_setup(void) if (CONFIG_COREBOOT) return; - u32 eax, ebx, ecx, cpuid_features; + u32 eax, ebx, ecx, edx, cpuid_features; cpuid(1, &eax, &ebx, &ecx, &cpuid_features); if (!(cpuid_features & CPUID_MTRR)) return; @@ -73,6 +73,16 @@ void mtrr_setup(void) wrmsr_smp(MSR_MTRRfix4K_F8000, 0); /* Mark 3.5-4GB as UC, anything not specified defaults to WB */ wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0); - wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800); + + int phys_bits = 36; + cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); + if (eax >= 0x80000008) { + /* Get physical bits from leaf 0x80000008 (if available) */ + cpuid(0x80000008u, &eax, &ebx, &ecx, &edx); + phys_bits = eax & 0xff; + } + u64 phys_mask = ((1ull << phys_bits) - 1); + wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800); + wrmsr_smp(MSR_MTRRdefType, 0xc06); } -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0007-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0007-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.pa"; filename*1="tch"

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[PATCH 5/8] Add MPS entries for LINT interrupts.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mptable.c | 23 +++++++++++++++++++++-- src/mptable.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 525188d..51b50db 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -22,7 +22,7 @@ mptable_init(void) + sizeof(struct mpt_cpu) * MaxCountCPUs + sizeof(struct mpt_bus) + sizeof(struct mpt_ioapic) - + sizeof(struct mpt_intsrc) * 16); + + sizeof(struct mpt_intsrc) * 18); struct mptable_config_s *config = malloc_fseg(length); struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating)); if (!config || !floating) { @@ -88,7 +88,7 @@ mptable_init(void) } } - config->entrycount = actual_cpu_count + 2 + 16; + config->entrycount = actual_cpu_count + 2 + 16 + 2; /* isa bus */ struct mpt_bus *bus = (void*)&cpus[actual_cpu_count]; @@ -125,6 +125,25 @@ mptable_init(void) intsrc++; } + /* Local interrupt assignment */ + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 3; /* ExtINT */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 0; /* LINTIN0 */ + intsrc++; + + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 1; /* NMI */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 1; /* LINTIN1 */ + intsrc++; + // Set checksum. config->length = (void*)intsrc - (void*)config; config->checksum -= checksum(config, config->length); diff --git a/src/mptable.h b/src/mptable.h index 4c4d52f..c4e3c51 100644 --- a/src/mptable.h +++ b/src/mptable.h @@ -38,6 +38,7 @@ struct mptable_config_s { #define MPT_TYPE_BUS 1 #define MPT_TYPE_IOAPIC 2 #define MPT_TYPE_INTSRC 3 +#define MPT_TYPE_LOCAL_INT 4 struct mpt_cpu { u8 type; -- 1.6.2.5 --------------010303080000070006010407 Content-Type: text/x-patch; name="0006-Properly-mask-value-for-MTRR-mask.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0006-Properly-mask-value-for-MTRR-mask.patch"

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[PATCH 5/9] Add MPS entries for LINT interrupts.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mptable.c | 23 +++++++++++++++++++++-- src/mptable.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 0c07cfb..b93d50a 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -31,7 +31,7 @@ mptable_init(void) + sizeof(struct mpt_cpu) * MaxCountCPUs + sizeof(struct mpt_bus) + sizeof(struct mpt_ioapic) - + sizeof(struct mpt_intsrc) * 16); + + sizeof(struct mpt_intsrc) * 18); struct mptable_config_s *config = malloc_fseg(length); struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating)); if (!config || !floating) { @@ -90,7 +90,7 @@ mptable_init(void) } } - config->entrycount = actual_cpu_count + 2 + 16; + config->entrycount = actual_cpu_count + 2 + 16 + 2; /* isa bus */ struct mpt_bus *bus = (void*)&cpus[actual_cpu_count]; @@ -127,6 +127,25 @@ mptable_init(void) intsrc++; } + /* Local interrupt assignment */ + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 3; /* ExtINT */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 0; /* LINTIN0 */ + intsrc++; + + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 1; /* NMI */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 1; /* LINTIN1 */ + intsrc++; + // Set checksum. config->length = (void*)intsrc - (void*)config; config->checksum -= checksum(config, config->length); diff --git a/src/mptable.h b/src/mptable.h index 4c4d52f..c4e3c51 100644 --- a/src/mptable.h +++ b/src/mptable.h @@ -38,6 +38,7 @@ struct mptable_config_s { #define MPT_TYPE_BUS 1 #define MPT_TYPE_IOAPIC 2 #define MPT_TYPE_INTSRC 3 +#define MPT_TYPE_LOCAL_INT 4 struct mpt_cpu { u8 type; -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0006-Properly-mask-value-for-MTRR-mask.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0006-Properly-mask-value-for-MTRR-mask.patch"

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[v2] r4911 - trunk/util/x86emu
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 09:09:20 +0000 (Thu, 05 Nov 2009) New Revision: 4911 Modified: trunk/util/x86emu/x86_asm.S Log: Get the passed in Bus/Device/Function from the correct location on the stack. Signed-off-by: Mark Marshall <mark.marshall(a)csr.com> Clarified the comment and Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/x86emu/x86_asm.S =================================================================== --- trunk/util/x86emu/x86_asm.S 2009-11-05 09:03:04 UTC (rev 4910) +++ trunk/util/x86emu/x86_asm.S 2009-11-05 09:09:20 UTC (rev 4911) @@ -68,8 +68,10 @@ /* Get devfn into %ecx */ movl %esp, %ebp - // FIXME: Should this function be called with regparm=0? - movl 8(%ebp), %ecx + /* This function is called with regparm=0 and we have + * to skip the 32 byte from pushal: + */ + movl 36(%ebp), %ecx /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f)

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[v2] r4910 - trunk/util/x86emu
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 09:03:04 +0000 (Thu, 05 Nov 2009) New Revision: 4910 Modified: trunk/util/x86emu/x86_interrupts.c Log: Use more care when implementing the PCI BIOS functions. The READ_CONF and WRITE_CONF functions would both do the wrong thing if the passed in BDF was not found. We should return and error to the caller, but not stop running the option ROM. Signed-off-by: Mark Marshall <mark.marshall(a)csr.com> I slightly reworked the patch: The 'CHECK' function seemed to be both wrong code and the wrong number. In fact the CHECK function was given the function number of the "Microsoft Real-Time Compression Interface". Since this is definitely wrong I removed the code. Dropped some unneeded scopes, too, to make the code easier to read. Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/x86emu/x86_interrupts.c =================================================================== --- trunk/util/x86emu/x86_interrupts.c 2009-11-05 08:10:12 UTC (rev 4909) +++ trunk/util/x86emu/x86_interrupts.c 2009-11-05 09:03:04 UTC (rev 4910) @@ -34,19 +34,22 @@ #endif enum { - CHECK = 0xb001, - FINDDEV = 0xb102, - READCONFBYTE = 0xb108, - READCONFWORD = 0xb109, - READCONFDWORD = 0xb10a, - WRITECONFBYTE = 0xb10b, - WRITECONFWORD = 0xb10c, - WRITECONFDWORD = 0xb10d + PCIBIOS_CHECK = 0xb101, + PCIBIOS_FINDDEV = 0xb102, + PCIBIOS_READCONFBYTE = 0xb108, + PCIBIOS_READCONFWORD = 0xb109, + PCIBIOS_READCONFDWORD = 0xb10a, + PCIBIOS_WRITECONFBYTE = 0xb10b, + PCIBIOS_WRITECONFWORD = 0xb10c, + PCIBIOS_WRITECONFDWORD = 0xb10d }; // errors go in AH. Just set these up so that word assigns // will work. KISS. enum { + PCIBIOS_SUCCESSFUL = 0x0000, + PCIBIOS_UNSUPPORTED = 0x8100, + PCIBIOS_BADVENDOR = 0x8300, PCIBIOS_NODEV = 0x8600, PCIBIOS_BADREG = 0x8700 }; @@ -63,7 +66,7 @@ int int1a_handler(struct eregs *regs) { - unsigned short func = (unsigned short) regs->eax; + unsigned short func = (unsigned short)regs->eax; int retval = 0; unsigned short devid, vendorid, devfn; /* Use short to get rid of gabage in upper half of 32-bit register */ @@ -71,14 +74,13 @@ unsigned char bus; struct device *dev; - switch(func) { - case CHECK: - regs->edx = 0x4350; - regs->ecx = 0x2049; + switch (func) { + case PCIBIOS_CHECK: + regs->edx = 0x20494350; /* ' ICP' */ + regs->edi = 0x00000000; /* protected mode entry */ retval = 0; break; - case FINDDEV: - { + case PCIBIOS_FINDDEV: devid = regs->ecx; vendorid = regs->edx; devindex = regs->esi; @@ -98,7 +100,7 @@ // busnum is an unsigned char; // devfn is an int, so we mask it off. busdevfn = (dev->bus->secondary << 8) - | (dev->path.pci.devfn & 0xff); + | (dev->path.pci.devfn & 0xff); printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn); regs->ebx = busdevfn; retval = 0; @@ -106,15 +108,13 @@ regs->eax = PCIBIOS_NODEV; retval = -1; } - } - break; - case READCONFDWORD: - case READCONFWORD: - case READCONFBYTE: - case WRITECONFDWORD: - case WRITECONFWORD: - case WRITECONFBYTE: - { + break; + case PCIBIOS_READCONFDWORD: + case PCIBIOS_READCONFWORD: + case PCIBIOS_READCONFBYTE: + case PCIBIOS_WRITECONFDWORD: + case PCIBIOS_WRITECONFWORD: + case PCIBIOS_WRITECONFBYTE: unsigned long dword; unsigned short word; unsigned char byte; @@ -124,49 +124,48 @@ bus = regs->ebx >> 8; reg = regs->edi; dev = dev_find_slot(bus, devfn); - if (! dev) { + if (!dev) { printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! regs->eax = PCIBIOS_BADREG; retval = -1; + return retval; } - switch(func) { - case READCONFBYTE: + switch (func) { + case PCIBIOS_READCONFBYTE: byte = pci_read_config8(dev, reg); regs->ecx = byte; break; - case READCONFWORD: + case PCIBIOS_READCONFWORD: word = pci_read_config16(dev, reg); regs->ecx = word; break; - case READCONFDWORD: + case PCIBIOS_READCONFDWORD: dword = pci_read_config32(dev, reg); regs->ecx = dword; break; - case WRITECONFBYTE: + case PCIBIOS_WRITECONFBYTE: byte = regs->ecx; pci_write_config8(dev, reg, byte); break; - case WRITECONFWORD: + case PCIBIOS_WRITECONFWORD: word = regs->ecx; pci_write_config16(dev, reg, word); break; - case WRITECONFDWORD: + case PCIBIOS_WRITECONFDWORD: dword = regs->ecx; pci_write_config32(dev, reg, dword); break; } - if (retval) - retval = PCIBIOS_BADREG; printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, regs->ecx); regs->eax = 0; retval = 0; - } - break; + break; default: - printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + retval = -1; break; }

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[v2] r4909 - trunk/src/devices
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 08:10:12 +0000 (Thu, 05 Nov 2009) New Revision: 4909 Modified: trunk/src/devices/pci_rom.c Log: When loading an option ROM use the class stored in the device to decide whether the option ROM is a special VGA type. An S3 card that I've got has the wrong class in the VGA BIOS. (A Stealth 64 DRAM T PCI, from 1994 - BIOS V2.02) Signed-off-by: Mark Marshall <mark.marshall(a)csr.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/pci_rom.c =================================================================== --- trunk/src/devices/pci_rom.c 2009-11-04 12:18:44 UTC (rev 4908) +++ trunk/src/devices/pci_rom.c 2009-11-05 08:10:12 UTC (rev 4909) @@ -116,7 +116,10 @@ rom_size = rom_header->size * 512; - if (PCI_CLASS_DISPLAY_VGA == rom_data->class_hi) { + // We check to see if the device thinks it is a VGA device not + // whether the ROM image is for a VGA device because some + // devices have a mismatch between the hardware and the ROM + if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { #if CONFIG_CONSOLE_VGA == 1 && CONFIG_CONSOLE_VGA_MULTI == 0 extern device_t vga_pri; // the primary vga device, defined in device.c if (dev != vga_pri) return NULL; // only one VGA supported

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coreboot November 2009