coreboot November 2009

coreboot@coreboot.org

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232 discussions

Re: [coreboot] [Fwd: Re: [Fwd: Re: [Fwd: Re: arima hdama problem]]]
by Hugh Greenberg 05 Nov '09

05 Nov '09

Below is the end of the output. I have no idea what coreboot_ram.map should look like, so I've attached that file. before scan bus of PCI: 00:18.0 In scan bus of PCI: 00:18.0 scan_bus() = 0010131c amdk8_scan_chains: PCI: 00:18.0, node 0 amdk8_scan_chains: PCI: 00:18.0, node 0, link 0 amdk8_scan_chain: PCI: 00:18.0, node 0, link 0 connected Init Complete non coherent scan chain -- Hugh Greenberg Myles Watson wrote: > > > On Wed, Oct 21, 2009 at 11:03 AM, Myles Watson <mylesgw(a)gmail.com > <mailto:mylesgw@gmail.com>> wrote: > > > > On Wed, Oct 21, 2009 at 10:32 AM, Hugh Greenberg <hng(a)lanl.gov > <mailto:hng@lanl.gov>> wrote: > > Attached is a patch that contains the extra debug statements I > added. Below is the new output: > > before scan bus of PCI: 00:18.0 > In scan bus of PCI: 00:18.0 > > OK. This next patch prints the location of scan_bus > > I forgot to say that you can look in build/coreboot_ram.map to see if > the value matches what you expect. > > Thanks, > Myles > 00000000 A CONFIG_ACPI_SSDTX_NUM 00000000 A CONFIG_APIC_ID_OFFSET 00000000 A CONFIG_AP_IN_SIPI_WAIT 00000000 A CONFIG_COMPRESSED_PAYLOAD_NRV2B 00000000 A CONFIG_CONSOLE_SERIAL_19200 00000000 A CONFIG_CONSOLE_SERIAL_38400 00000000 A CONFIG_CONSOLE_SERIAL_57600 00000000 A CONFIG_CONSOLE_SERIAL_9600 00000000 A CONFIG_CONSOLE_SERIAL_COM2 00000000 A CONFIG_CONSOLE_SERIAL_COM3 00000000 A CONFIG_CONSOLE_SERIAL_COM4 00000000 A CONFIG_CONSOLE_VGA 00000000 A CONFIG_CONSOLE_VGA_MULTI 00000000 A CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST 00000000 A CONFIG_COREBOOT_ROMSIZE_KB_1024 00000000 A CONFIG_COREBOOT_ROMSIZE_KB_128 00000000 A CONFIG_COREBOOT_ROMSIZE_KB_2048 00000000 A CONFIG_COREBOOT_ROMSIZE_KB_256 00000000 A CONFIG_COREBOOT_ROMSIZE_KB_4096 00000000 A CONFIG_CPU_SOCKET_TYPE 00000000 A CONFIG_DEBUG 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 00000000 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 00000000 A CONFIG_EXPERT 00000000 A CONFIG_HAVE_ACPI_RESUME 00000000 A CONFIG_HAVE_FAILOVER_BOOT 00000000 A CONFIG_HAVE_MAINBOARD_RESOURCES 00000000 A CONFIG_HAVE_SMI_HANDLER 00000000 A CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC 00000000 A CONFIG_HW_MEM_HOLE_SIZEK 00000000 A CONFIG_K8_REV_F_SUPPORT 00000000 A CONFIG_LIFT_BSP_APIC_ID 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 00000000 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 00000000 A CONFIG_MMCONF_SUPPORT 00000000 A CONFIG_MMCONF_SUPPORT_DEFAULT 00000000 A CONFIG_MULTIBOOT 00000000 A CONFIG_PAYLOAD_NONE 00000000 A CONFIG_PCI_64BIT_PREF_MEM 00000000 A CONFIG_PCI_BUS_SEGN_BITS 00000000 A CONFIG_PCI_IO_CFG_EXT 00000000 A CONFIG_PCI_OPTION_ROM_RUN_X86EMU 00000000 A CONFIG_PCI_OPTION_ROM_RUN_YABEL 00000000 A CONFIG_PIRQ_ROUTE 00000000 A CONFIG_SB_HT_CHAIN_ON_BUS0 00000000 A CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 00000000 A CONFIG_UDELAY_IO 00000000 A CONFIG_UDELAY_LAPIC 00000000 A CONFIG_UDELAY_TSC 00000000 A CONFIG_USBDEBUG_DIRECT 00000000 A CONFIG_USE_FAILOVER_IMAGE 00000000 A CONFIG_USE_INIT 00000000 A CONFIG_USE_OPTION_TABLE 00000000 A CONFIG_USE_WATCHDOG_ON_BOOT 00000000 A CONFIG_VENDOR_ABIT 00000000 A CONFIG_VENDOR_ADVANTECH 00000000 A CONFIG_VENDOR_AMD 00000000 A CONFIG_VENDOR_ARTEC_GROUP 00000000 A CONFIG_VENDOR_ASI 00000000 A CONFIG_VENDOR_ASUS 00000000 A CONFIG_VENDOR_A_TREND 00000000 A CONFIG_VENDOR_AXUS 00000000 A CONFIG_VENDOR_AZZA 00000000 A CONFIG_VENDOR_BCOM 00000000 A CONFIG_VENDOR_BIOSTAR 00000000 A CONFIG_VENDOR_BROADCOM 00000000 A CONFIG_VENDOR_COMPAQ 00000000 A CONFIG_VENDOR_DELL 00000000 A CONFIG_VENDOR_DIGITAL_LOGIC 00000000 A CONFIG_VENDOR_EAGLELION 00000000 A CONFIG_VENDOR_EMULATION 00000000 A CONFIG_VENDOR_GIGABYTE 00000000 A CONFIG_VENDOR_HP 00000000 A CONFIG_VENDOR_IBM 00000000 A CONFIG_VENDOR_IEI 00000000 A CONFIG_VENDOR_INTEL 00000000 A CONFIG_VENDOR_IWILL 00000000 A CONFIG_VENDOR_JETWAY 00000000 A CONFIG_VENDOR_KONTRON 00000000 A CONFIG_VENDOR_LIPPERT 00000000 A CONFIG_VENDOR_MITAC 00000000 A CONFIG_VENDOR_MSI 00000000 A CONFIG_VENDOR_NEC 00000000 A CONFIG_VENDOR_NEWISYS 00000000 A CONFIG_VENDOR_NVIDIA 00000000 A CONFIG_VENDOR_OLPC 00000000 A CONFIG_VENDOR_PC_ENGINES 00000000 A CONFIG_VENDOR_RCA 00000000 A CONFIG_VENDOR_SOYO 00000000 A CONFIG_VENDOR_SUNW 00000000 A CONFIG_VENDOR_SUPERMICRO 00000000 A CONFIG_VENDOR_TECHNEXION 00000000 A CONFIG_VENDOR_TECHNOLOGIC 00000000 A CONFIG_VENDOR_TELEVIDEO 00000000 A CONFIG_VENDOR_THOMSON 00000000 A CONFIG_VENDOR_TYAN 00000000 A CONFIG_VENDOR_VIA 00000000 A CONFIG_VGA 00000000 A CONFIG_VGA_BIOS 00000000 A CONFIG_VGA_ROM_RUN 00000000 A CONFIG_WAIT_BEFORE_CPUS_INIT 00000001 A _bogus 00000001 A CONFIG_AGP_PLUGIN_SUPPORT 00000001 A CONFIG_ARCH_X86 00000001 A CONFIG_BOARD_ARIMA_HDAMA 00000001 A CONFIG_BOARD_ROMSIZE_KB_512 00000001 A CONFIG_CARDBUS_PLUGIN_SUPPORT 00000001 A CONFIG_COMPRESSED_PAYLOAD_LZMA 00000001 A CONFIG_CONSOLE_SERIAL_115200 00000001 A CONFIG_CONSOLE_SERIAL8250 00000001 A CONFIG_CONSOLE_SERIAL_COM1 00000001 A CONFIG_COREBOOT_ROMSIZE_KB_512 00000001 A CONFIG_COREBOOT_V2 00000001 A CONFIG_COREBOOT_V4 00000001 A CONFIG_CPU_AMD_MODEL_FXX 00000001 A CONFIG_CPU_AMD_SOCKET_940 00000001 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 00000001 A CONFIG_GDB_STUB 00000001 A CONFIG_GENERATE_MP_TABLE 00000001 A CONFIG_GENERATE_PIRQ_TABLE 00000001 A CONFIG_HAVE_FALLBACK_BOOT 00000001 A CONFIG_HAVE_HARD_RESET 00000001 A CONFIG_HAVE_HIGH_TABLES 00000001 A CONFIG_HAVE_INIT_TIMER 00000001 A CONFIG_HAVE_LOW_TABLES 00000001 A CONFIG_HAVE_MOVNTI 00000001 A CONFIG_HAVE_MP_TABLE 00000001 A CONFIG_HAVE_OPTION_TABLE 00000001 A CONFIG_HAVE_PIRQ_TABLE 00000001 A CONFIG_HT_CHAIN_UNITID_BASE 00000001 A CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT 00000001 A CONFIG_IOAPIC 00000001 A CONFIG_K8_HT_FREQ_1G_SUPPORT 00000001 A CONFIG_LOGICAL_CPUS 00000001 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8 00000001 A CONFIG_NORTHBRIDGE_AMD_AMDK8 00000001 A CONFIG_NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX 00000001 A CONFIG_PAYLOAD_ELF 00000001 A CONFIG_PCIEXP_PLUGIN_SUPPORT 00000001 A CONFIG_PCI_OPTION_ROM_RUN_REALMODE 00000001 A CONFIG_PCI_ROM_RUN 00000001 A CONFIG_PCIX_PLUGIN_SUPPORT 00000001 A CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY 00000001 A CONFIG_SERIAL_CPU_INIT 00000001 A CONFIG_SERIAL_POST 00000001 A CONFIG_SMP 00000001 A CONFIG_SOUTHBRIDGE_AMD_AMD8111 00000001 A CONFIG_SOUTHBRIDGE_AMD_AMD8131 00000001 A CONFIG_SUPERIO_NSC_PC87360 00000001 A CONFIG_USE_DCACHE_RAM 00000001 A CONFIG_USE_FALLBACK_IMAGE 00000001 A CONFIG_USE_PRINTK_IN_CAR 00000001 A CONFIG_VAR_MTRR_HOLE 00000001 A CONFIG_VENDOR_ARIMA 00000001 A CONFIG_VGA_BRIDGE_SETUP 00000001 A CONFIG_WRITE_HIGH_TABLES 00000002 A CONFIG_MAX_PHYSICAL_CPUS 00000003 A CONFIG_MAX_REBOOT_CNT 00000003 A CONFIG_TTYS0_LCS 00000004 A CONFIG_MAX_CPUS 00000008 A CONFIG_DEFAULT_CONSOLE_LOGLEVEL 00000008 A CONFIG_MAXIMUM_CONSOLE_LOGLEVEL 00000009 A CONFIG_IRQ_SLOT_COUNT 00000009 A __idt_handler_size 00000020 A CONFIG_HT_CHAIN_END_UNITID_BASE 00000028 A CONFIG_CPU_ADDR_BITS 00000031 A CONFIG_LB_CKS_RANGE_START 00000037 A gdt_limit 0000007a A CONFIG_LB_CKS_RANGE_END 0000007b A CONFIG_LB_CKS_LOC 000001a6 A __realmode_code_size 00000200 A CONFIG_COREBOOT_ROMSIZE_KB 000003f8 A CONFIG_TTYS0_BASE 00000500 A __realmode_idt 00000508 a __stack 0000050c A __run_optionrom 00000593 A __run_interrupt 00000623 a __interrupt_handler_16bit 00001000 A CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE 0000161f A CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID 00003016 A CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID 00004000 A CONFIG_HEAP_SIZE 00008000 A CONFIG_DCACHE_RAM_SIZE 00008000 A CONFIG_STACK_SIZE 0001c200 A CONFIG_TTYS0_BAUD 00020000 A CONFIG_XIP_ROM_SIZE 00080000 A CONFIG_ROM_IMAGE_SIZE 00080000 A CONFIG_ROM_SIZE 000c8000 A CONFIG_DCACHE_RAM_BASE 00100000 A CONFIG_RAMBASE 00100000 T _ram_seg 00100000 T _start 00100000 T _text 001000a0 t vec0 001000a6 t vec1 001000ac t vec2 001000b2 t vec3 001000b8 t vec4 001000be t vec5 001000c4 t vec6 001000ca t vec7 001000d0 t vec8 001000d6 t vec9 001000dc t vec10 001000e2 t vec11 001000e8 t vec12 001000ee t vec13 001000f4 t vec14 001000fa t vec15 00100100 t vec16 00100106 t vec17 0010010c t vec18 00100112 t vec19 00100118 t int_hand 00100137 T gdb_stub_breakpoint 00100141 t gdtaddr 00100148 t ttyS0_tst_byte 00100159 t ttyS0_rx_byte 0010016a t ttyS0_tx_byte 00100181 t ttyS0_init 00100198 T amd8111_enable 001002b4 t lpci_set_subsystem 001002d8 t lpci_set_subsystem 001002fc t lpc_init 00100496 t amd8111_lpc_enable_resources 001004b1 t amd8111_lpc_read_resources 00100550 t lpci_set_subsystem 00100574 t ide_init 001005f8 t lsmbus_write_byte 00100706 t lsmbus_read_byte 00100816 t lsmbus_send_byte 0010091a t lsmbus_recv_byte 00100a20 t lpci_set_subsystem 00100a44 t acpi_init 00100ab6 t acpi_enable_resources 00100af5 t acpi_read_resources 00100b60 t amd8111_usb2_enable 00100b84 t lpci_set_subsystem 00100ba8 t lpci_set_subsystem 00100bcc t nic_init 00100c30 t pci_init 00100cb4 t lpci_set_subsystem 00100cd8 t amd8131_walk_children 00100d13 t amd8131_count_dev 00100d33 t amd8131_scan_bridge 00100d4c t ioapic_enable 00100d7c t amd8131_scan_bus 00100eb7 t amd8131_pcix_tune_dev 00101064 t amd8131_pcix_init 001011d0 t mcf0_control_init 001011d1 t tolm_test 00101205 t cpu_bus_noop 00101206 t root_complex_enable_dev 0010122d t get_fx_devs 001012b2 t f1_read_config32 001012d9 t f1_write_config32 0010131c t amdk8_scan_chains 001016e0 t amdk8_enable_resources 001016fb t amdk8_find_reg 001017af t amdk8_set_resources 00101b1f t amdk8_read_resources 00101d2d t cpu_bus_scan 00102059 t cpu_bus_init 00102066 t amdk8_domain_scan_bus 00102145 t amdk8_domain_set_resources 00102424 t amdk8_domain_read_resources 001024b8 t misc_control_init 00102708 t mcf3_set_resources 001027be t mcf3_read_resources 00102834 T cpus_ready_for_init 00102835 T is_e0_later_in_bsp 001028ca T model_fxx_init 00102f44 T uart8250_tx_byte 00102f67 T uart8250_can_rx_byte 00102f73 T uart8250_rx_byte 00102f87 T uart8250_init 00102fd0 T init_uart8250 00103008 T mdelay 0010302b T delay 00103050 T hardwaremain 00103118 T cbfs_load_payload 00103c0c T do_printk 00103c58 T console_init 00103c84 T console_tx_flush 00103ca7 T console_tx_byte 00103cfa T console_rx_byte 00103d33 T console_tst_byte 00103d50 T post_code 00103d71 T die 00103da4 t number 00104006 T vtxprintf 00104408 t str_tx_byte.927 00104413 T vsprintf 0010445f T sprintf 0010447c t pick_largest_resource 001044ff T reset_bus 0010453c t read_resources 001045fb t constrain_resources 001047af T scan_bus 001048d2 T enable_resources 0010491b T dev_enable 00104948 T assign_resources 001049ef T dev_initialize 00104aa1 t compute_resources 00104f3b t allocate_resources 001054de T dev_configure 001059ee T dev_enumerate 00105a82 T alloc_dev 00105b38 T root_dev_init 00105b39 T root_dev_set_resources 00105b51 T root_dev_read_resources 00105b69 T root_dev_reset 00105b80 T enable_childrens_resources 00105bc0 T root_dev_enable_resources 00105bc5 T scan_static_bus 00105d50 T root_dev_scan_bus 00105d58 T dev_find_slot 00105d88 T dev_find_slot_on_smbus 00105db8 T dev_find_device 00105de1 T dev_find_class 00105e0b T probe_resource 00105e3c T resource_end 00105e9a T resource_max 00105ee4 T search_bus_resources 00105f75 T search_global_resources 00105fcc T dev_set_enabled 00106018 T disable_children 00106061 T path_eq 001060be T find_dev_path 001060f0 T resource_type 00106185 T compact_resources 001061eb T new_resource 0010629a T dev_path 0010638a T show_one_resource 0010646f T show_all_devs_resources 001064f7 T show_all_devs 0010655b T show_devs_tree 001065fe T show_all_devs_tree 00106633 T show_devs_subtree 0010667e T resource_tree 001067e1 T print_resource_tree 00106849 T report_resource_stored 00106971 T find_resource 001069c6 T bus_path 001069f4 T alloc_find_dev 00106a24 T pci_moving_config8 00106a8b T pci_assign_irqs 00106b1c T pci_find_next_capability 00106bdf T pci_find_capability 00106bf5 T pci_dev_enable_resources 00106c92 T pci_moving_config16 00106cfa T do_pci_scan_bridge 00106e05 T pci_scan_bridge 00106e1e T pci_dev_set_subsystem 00106e42 T pci_moving_config32 00106ea4 T pci_probe_dev 0010726c T pci_scan_bus 00107400 T pci_domain_scan_bus 00107421 T pci_dev_init 00107466 T pci_bus_reset 001074bc T pci_bus_enable_resources 00107520 T pci_dev_set_resources 0010785e T pci_domain_read_resources 001078ad t pci_record_bridge_resource 00107936 T pci_get_resource 00107afa t pci_read_bases 00107b3f t pci_get_rom_resource 00107c33 T pci_bus_read_resources 00107d6a T pci_dev_read_resources 00107d90 T ht_scan_bridge 00107da9 t ht_lookup_slave_capability 00107df2 t ht_collapse_early_enumeration 00107f80 T hypertransport_scan_chain 001082fc T hypertransport_scan_chain_x 00108320 T pcix_speed 0010835d T pcix_scan_bridge 001083cc T pcix_scan_bus 001084e0 T pciexp_scan_bridge 001084f9 T pciexp_scan_bus 0010856c T cardbus_scan_bus 00108571 T cardbus_scan_bridge 0010867d T cardbus_enable_resources 001086d7 t cardbus_record_bridge_resource 001087ac T cardbus_read_resources 00108908 t ops_pci_bus 00108929 t get_pbus 001089a1 T pci_write_config32 001089d7 T pci_write_config16 00108a0e T pci_write_config8 00108a47 T pci_read_config32 00108a76 T pci_read_config16 00108aa5 T pci_read_config8 00108ad4 T get_pbus_smbus 00108b3f T smbus_block_write 00108ba0 T smbus_block_read 00108c01 T smbus_process_call 00108c53 T smbus_write_word 00108ca5 T smbus_read_word 00108ceb T smbus_write_byte 00108d3f T smbus_read_byte 00108d85 T smbus_send_byte 00108dcb T smbus_recv_byte 00108e03 T smbus_quick_write 00108e3b T smbus_quick_read 00108e72 T smbus_set_link 00108f04 T pci_rom_load 00108fb7 T pci_rom_probe 00109130 T interrupt_handler 001092c0 t intXX_unknown_handler 001092dd T run_bios 00109412 t intXX_exception_handler 00109438 T __idt_handler 00109441 T __realmode_code 001095e8 T int12_handler 001095f5 T int15_handler 00109710 T int1a_handler 00109910 t rtc_checksum_valid 001099b9 T rtc_init 00109ac0 T isa_dma_init 00109ad0 T setup_i8259 00109af5 T i8259_configure_irq_trigger 00109b74 T elf_check_arch 00109b96 T jmp_to_elf_entry 00109ce8 T move_gdt 00109d40 T write_tables 00109f30 t pci_conf1_read_config8 00109f63 t pci_conf1_read_config16 00109f97 t pci_conf1_read_config32 00109fbf t pci_conf1_write_config8 00109ffa t pci_conf1_write_config16 0010a036 t pci_conf1_write_config32 0010a064 t pci_sanity_check 0010a0d5 T pci_check_direct 0010a182 T pci_remember_direct 0010a1a1 T pci_set_method 0010a1d4 t parse_ulong 0010a22d t copy_from_hex 0010a2ac t put_packet 0010a32a T x86_exception 0010a6d0 T hard_reset 0010a7d4 T init_timer 0010a7f3 T udelay 0010a814 T model_fxx_update_microcode 0010a854 T init_processor_name 0010a998 T read_nb_cfg_54 0010a9a8 T get_node_core_id 0010a9f0 T get_apicid_base 0010ab18 t set_fixed_mtrrs 0010ac09 t set_fixed_mtrr_resource 0010ad08 T amd_setup_mtrrs 0010ae4c T amd_update_microcode 0010aef8 T setup_lapic 0010af98 T secondary_cpu_init 0010afc5 T start_cpu 0010b31e T initialize_cpus 0010c000 T _secondary_start 0010c055 t gdtaddr 0010c05b T _secondary_start_end 0010c05c T x86_enable_cache 0010c084 T enable_fixed_mtrr 0010c091 t set_fixed_mtrrs 0010c182 t set_var_mtrr 0010c250 t range_to_mtrr 0010c37e t set_fixed_mtrr_resource 0010c447 T set_var_mtrr_resource 0010c525 T x86_mtrr_check 0010c5bc T x86_setup_var_mtrrs 0010c6c8 T x86_setup_fixed_mtrrs 0010c73a T x86_setup_mtrrs 0010c754 T map_2M_page 0010c8b4 T max_apicid 0010c8d7 t node_link_to_bus 0010c947 T reboot_if_hotswap 0010ca3f T smp_write_processors_inorder 0010cad1 T smp_write_config_table 0010d0d7 T write_smp_table 0010d0fc T write_pirq_routing_table 0010d104 T memset 0010d11c T memcpy 0010d13c T memmove 0010d180 T free 0010d197 T malloc 0010d208 T set_boot_successful 0010d22c T boot_successful 0010d234 T compute_ip_checksum 0010d283 T add_ip_checksums 0010d2c4 T cbfs_check_magic 0010d2f9 t tohex16 0010d351 T run_address 0010d357 T cbfs_master_header 0010d3fa T cbfs_find 0010d5a9 T cbfs_get_file 0010d5ae T cbfs_find_file 0010d651 T cbfs_execute_stage 0010d713 T cbfs_decompress 0010d774 T cbfs_load_stage 0010d7ed T cbfs_load_optionrom 0010d8ac T LzmaDecodeProperties 0010d923 T LzmaDecode 0010e461 T ulzma 0010e528 T lb_memory_range 0010e575 T get_lb_mem 0010e57b t build_lb_mem_range 0010e599 T lb_mainboard 0010e654 t lb_cleanup_memory_ranges 0010e8d9 T lb_add_memory_range 0010eb44 t lb_table_fini 0010ec8e T write_coreboot_table 0010eff0 T copy_pirq_routing_table 0010f03c T cpu_initialize 0010f34c t pci_conf2_read_config8 0010f38f t pci_conf2_read_config16 0010f3d3 t pci_conf2_read_config32 0010f416 t pci_conf2_write_config8 0010f45a t pci_conf2_write_config16 0010f49f t pci_conf2_write_config32 0010f4e0 T smp_compute_checksum 0010f4f5 T smp_write_floating_table_physaddr 0010f544 T smp_write_floating_table 0010f55b T smp_next_mpc_entry 0010f566 T smp_next_mpe_entry 0010f577 T smp_write_compatibility_address_space 0010f5c6 T smp_write_bus_hierarchy 0010f61d T smp_write_address_space 0010f681 T smp_write_lintsrc 0010f6fe T smp_write_intsrc 0010f77b T smp_write_ioapic 0010f7c8 T smp_write_processor 0010f827 T smp_write_processors 0010f8a8 T smp_write_intsrc_pci_bridge 0010fa07 T smp_write_bus 0010fa50 t enable_dev 0010fa6c t init 0010fae8 t onboard_enable 0010faf8 T memcmp 0010fb28 T pnp_write_config 0010fb41 T pnp_read_config 0010fb52 T pnp_set_logical_device 0010fb62 T pnp_set_enable 0010fbb7 T pnp_read_enable 0010fbd5 T pnp_set_iobase 0010fc04 T pnp_set_irq 0010fc17 T pnp_set_drq 0010fc2a T pnp_read_resources 0010fc2b T pnp_enable_resources 0010fc45 T pnp_enable 0010fc65 t pnp_get_ioresource 0010fcd8 T pnp_enable_devices 0010fe48 T pnp_set_resources 0010ff90 t kbc_output_buffer_full 0010ffcf t kbc_input_buffer_empty 0011000e t send_keyboard 00110052 t kbc_cleanup_buffers 001100af T set_kbc_ps2_mode 00110110 T init_pc_keyboard 00110330 R console_drivers 00110330 R _rodata 00110330 r uart8250_console 00110330 T _etext 00110344 R econsole_drivers 00110344 R pci_drivers 00110344 r usb_driver 0011034c r lpc_driver 00110354 r ide_driver 0011035c r acpi_driver 00110364 r usb2_driver 0011036c r ac97modem_driver 00110374 r ac97audio_driver 0011037c r nic_driver 00110384 r pci_driver 0011038c r smbus_driver 00110394 r ioapic_driver 0011039c r pcix_driver 001103a4 r mcf0_driver 001103ac r mcf3_driver 001103b4 R cpu_drivers 001103b4 R epci_drivers 001103b4 r model_fxx 001103bc R ecpu_drivers 001103bc r __func__.1990 001103d0 r __func__.1888 001103e4 r __func__.2116 001103f8 r __func__.1543 00110408 r __func__.1617 0011041c r __func__.1842 00110434 r __func__.1798 00110448 r __func__.1703 0011045c r __func__.1255 0011046c r __func__.1247 00110484 r __func__.1243 001104e8 r __func__.1831 001104fc r __func__.2109 00110550 r unknown.1298 00110558 r pcix_533mhz.1297 00110568 r pcix_266mhz.1296 00110578 r pcix_133mhz.1295 00110588 r pcix_100mhz.1294 00110598 r pcix_66mhz.1293 001105a4 r conventional.1292 001105b8 r __func__.1325 001105cc r __func__.1242 001105f0 r __func__.908 0011060c r __func__.1702 0011061c R pci_cf8_conf1 00110634 r exception_to_signal 00110658 r hexchars 0011066c r id_mapping_table.1408 00110718 r processor_names 00110804 r mtrr_msr 00110830 r __func__.1298 00110844 r mtrr_msr 00110870 r productid.1915 0011087c r oem.1914 00110884 r sig.1913 00110888 R intel_irq_routing_table 00110938 r free_mem_end_ptr 0011093c r __func__.825 00110944 R mainboard_vendor 0011094c R mainboard_part_number 00110954 R coreboot_version 00110958 R coreboot_extra_version 0011095c R coreboot_build 0011097c R coreboot_compile_time 00110988 R coreboot_compile_by 00110990 R coreboot_compile_host 00110998 R coreboot_compile_domain 0011099c R coreboot_compiler 001109c0 R coreboot_linker 001109e8 R coreboot_assembler 00110a18 r strings.1466 00110a68 r x86_vendors 00110ac0 r x86_vendor_name 00110aec R pci_cf8_conf2 00113ed0 D _data 00113ed0 D gdt 00113ed0 R _erodata 00113f08 D gdt_end 00113f08 D idtarg 00113f10 d _idt 00113fb0 d _idt_end 00113fb0 D mainboard_ops 00113fb8 D southbridge_amd_amd8111_ops 00113fc0 d usb_ops 00113fec d lops_pci 00113ff0 d ioapicregvalues 00114110 d lpc_ops 0011413c d lops_pci 00114140 d ide_ops 0011416c d lops_pci 00114170 d acpi_ops 0011419c d lops_pci 001141a0 d lops_smbus_bus 001141cc d usb2_ops 001141f8 d ac97modem_ops 00114224 d ac97audio_ops 00114250 d lops_pci 00114254 d nic_ops 00114280 d lops_pci 00114284 d pci_ops 001142b0 d smbus_ops 001142dc d lops_pci 001142e0 d ioapic_ops 0011430c d pcix_ops 00114338 d pci_ops_pci_dev 0011433c D northbridge_amd_amdk8_ops 00114344 D northbridge_amd_amdk8_root_complex_ops 0011434c d pci_domain_ops 00114378 d cpu_bus_ops 001143a4 d northbridge_operations 001143d0 d mcf3_ops 001143fc d cpu_dev_ops 00114428 d cpu_table 00114548 D console_loglevel 0011454c D default_message_loglevel 00114550 D minimum_console_loglevel 00114554 D default_console_loglevel 00114558 d console_lock 0011455c D all_devices 00114560 d dev_lock 00114564 D default_dev_ops_root 00114590 D default_pci_ops_dev 001145bc D default_pci_ops_bus 001145e8 d pci_dev_ops_pci 001145ec D default_ht_ops_bus 00114618 D default_pcix_ops_bus 00114644 D default_pciexp_ops_bus 00114670 D default_cardbus_ops_bus 0011469c d pci_ram_image_start 001146a0 D run_optionrom 001146a4 D vga_enable_console 001146a8 d elf_boot_notes 00114700 d microcode_updates 00115f10 d active_cpus 00115f14 d start_cpu_lock 00115f18 D last_dev_p 00115f1c D dev_root 00116368 D _dev2 001167b4 D _dev5 00116c00 D _dev4 0011704c D _dev7 00117498 D _dev64 001178e4 D _dev65 00117d30 D _dev66 0011817c D southbridge_amd_amd8111_info_13 00118180 D _dev9 001185cc D _dev10 00118a18 D _dev11 00118e64 D _dev12 001192b0 D _dev14 001196fc D _dev21 00119b48 D _dev34 00119f94 D _dev35 0011a3e0 D _dev36 0011a82c D _dev60 0011ac78 D _dev61 0011b0c4 D _dev15 0011b510 D _dev16 0011b95c D _dev17 0011bda8 D _dev18 0011c1f4 D drivers_pci_onboard_info_19 0011c1f8 D _dev20 0011c644 D _dev23 0011ca90 D _dev24 0011cedc D _dev25 0011d328 D _dev26 0011d774 D _dev27 0011dbc0 D _dev28 0011e00c D _dev29 0011e458 D _dev30 0011e8a4 D _dev31 0011ecf0 D _dev32 0011f13c D _dev33 0011f588 D _dev38 0011f9d4 D _dev40 0011fe20 D _dev45 0012026c D _dev47 001206b8 D _dev49 00120b04 D _dev51 00120f50 D _dev53 0012139c D _dev55 001217e8 D _dev57 00121c34 D _dev59 00122080 D _dev68 001224cc D _dev71 00122918 D _dev72 00122d64 D _dev73 001231b0 d free_mem_ptr 001231b4 D cpu_amd_socket_940_ops 001231bc D superio_nsc_pc87360_ops 001231c4 d ops 001231f0 d pnp_dev_info 001233d4 D drivers_pci_onboard_ops 001233dc D option_table 00123ad0 D pnp_ops 00123afc A _bss 00123afc B _SDA2_BASE_ 00123afc B _SDA_BASE_ 00123afc D _edata 00124000 b lops_pci 00124004 b lops_smbus_bus 00124030 B sysconf 001240c0 b fx_devs 001240c4 b __f0_dev 001240e4 b __f1_dev 00124104 b bounce_size 00124108 b bounce_buffer 0012410c B vga_pri 00124110 b smbus_max 00124114 b buffer.1653 00124128 b buffer.1506 00124150 b buffer.1474 00124170 b pci_bus_ops_pci 00124174 b ht_bus_ops_pci 00124178 b pcix_bus_ops_pci 0012417c b pciexp_bus_ops_pci 00124180 B intXX_handler 00124580 B high_tables_base 00124588 B high_tables_size 00124590 B pci_bus_fallback_ops 00124594 b gdb_stub_registers 001245d4 b in_buffer 00124764 b out_buffer 001248f4 B secondary_stack 001248f8 b last_cpu_index 00125000 b mapped_window.1332 00126000 b pgtbl.1331 0013a000 B _dev62 0013a44c B _dev63 0013a898 B _dev41 0013ace4 B _dev42 0013b130 B _dev43 0013b57c B _dev69 0013b9c8 B _dev70 0013be14 B mainboard_info_0 0013be18 B northbridge_amd_amdk8_root_complex_info_1 0013be19 B cpu_amd_socket_940_info_3 0013be1a B northbridge_amd_amdk8_info_6 0013be1b B northbridge_amd_amdk8_info_67 0013be1c B superio_nsc_pc87360_info_22 0013be24 b mem_ranges 0013be28 A _ebss 0013be28 A _end 00140000 A _stack 00160000 A _estack 00160000 A _heap 00164000 A _eheap 00164000 A _eram_seg 00200000 A CONFIG_RAMTOP 04000000 A CONFIG_AGP_APERTURE_SIZE fff80000 A CONFIG_ROMBASE fffe0000 A CONFIG_XIP_ROM_BASE

5 47

Re: [coreboot] failing fam10 code in coreboot
by Myles Watson 04 Nov '09

04 Nov '09

> -----Original Message----- > From: Maximilian Thuermer [mailto:Maximilian.Thuermer@ziti.uni- > heidelberg.de] > Sent: Wednesday, November 04, 2009 4:53 AM > To: Myles Watson > Subject: failing fam10 code in coreboot > > Myles, > > sorry it took so long to get back to you. I checked revs 4787 and 4788 > and attached the significant parts of the logs. You were right with the > assumption that the problem first occured in rev 4788. I also attached > the coreboot_ram.map files. > Hope this helps tracking down the bug... > > Best regards, > > > Maximilian > > Myles Watson wrote: > >> I did a fresh svn co the other day and tried building and > >> running a Tyan S2912_fam10 system. With older sources > >> (rev 4729) everything worked just fine, with the newest checkout > >> the booting process stops at setting MTRR registers or a little > >> later (depending on the compiler used: 3.4.6 builds faster code > >> and gets further than 4.3.3, both Ubuntu fashion). > >> I tried tracking down the problem and it appeared to me as if > >> the switch from CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP > >> > > It's possible. Could you try Rev 4787 & 4788 to make sure, then send me > the > > logs from both? I'm also interested in the coreboot_ram.map files. That's really weird. It looks like memory corruption, because CONFIG_RAMTOP (the top of memory that coreboot_ram can use) shouldn't affect the variable MTRR setup for the top of real RAM. I'm surprised that there was a difference in the coreboot_ram.map file too. I don't see how the changes affected the length of the stack! Which toolchain did you use to build these two? Are you using Kconfig or ./buildtarget? Can you try making the stack a lot bigger and seeing if that helps? CONFIG_STACK_SIZE is now 8K, but try 64K. (0x10000) I can't see why CONFIG_RAMTOP is 16M. Your coreboot_ram.map file says you could fit under 2M. That might not be true with a 64K stack, but for sure 4M. Thanks, Myles

1 0

Puzzles about coreboot when compiling "Kontron 986LCD-M"
by zhangxc 04 Nov '09

04 Nov '09

Hi Stepan, Glad to know that you're developing "Kontron 986LCD-M/mITX", and i'm trying to understand this excellent 986LCD-M board using Intel ICH7 as southbridge, i wanna create the bios image using Coreboot, but I even can't compile it after several tries. -------- My platform: Fedora 8 (Linux localhost.localdomain 2.6.23.1-42.fc8 #1 SMP Tue Oct 30 13:55:12 EDT 2007 i686 i686 i386 GNU/Linux) -------- Src code: http://tracker.coreboot.org/trac/coreboot/browser/branches/coreboot-v2-newb… -------- My steps: Reference to "http://www.coreboot.org/Kontron_986LCD-M_mITX" 1 Install "iasl" utility, and choose "filo" as the payload, and generate the "filo.elf" successfully. 2 ./buildtarget kontron/986lcd-m --> This will generate a new directory (naming "kontron_986lcd_m") where the key Makefile lies 3 Enter into the new dir, and copy the "filo.elf" to this new dir, but rename it as "payload.elf" 4 make -s --> This will fail, the message is as follows: ... /workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:25: warning: no previous prototype for soft_reset? /workstation/bios/branches/coreboot-v2-newbuild/src/mainboard/kontron/986lcd-m/reset.c:30: warning: no previous prototype for hard_reset? input/output = 302368/124894 = 2.421 /usr/bin/ld: coreboot: section `.id' can't be allocated in segment 1 /usr/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status make[1]: *** [coreboot] Error 1 make: *** [fallback/coreboot.rom] Error 2 ------------------ So, what is the problem? What kind of platform have you tried, Stepan? Thank you. ps: I also tried using "make menuconfig" "make" for the codes at "http://tracker.coreboot.org/trac/coreboot/browser/trunk/" the same mistake occurred. 2009-11-04 Terry Zhang Hardware R&D Engineer Beijing Brainaire Storage Technologies Ltd. Email: zhangxc(a)brainaire.com Tel: 86-10-6297-9839

2 1

[v2] r4908 - in trunk/src/cpu/intel: . model_106cx socket_441
by svn＠coreboot.org 04 Nov '09

04 Nov '09

Author: stepan Date: 2009-11-04 13:18:44 +0100 (Wed, 04 Nov 2009) New Revision: 4908 Added: trunk/src/cpu/intel/model_106cx/Kconfig trunk/src/cpu/intel/model_106cx/Makefile.inc trunk/src/cpu/intel/model_106cx/model_106cx_init.c trunk/src/cpu/intel/socket_441/Kconfig trunk/src/cpu/intel/socket_441/Makefile.inc Removed: trunk/src/cpu/intel/model_106cx/model_6cx_init.c Modified: trunk/src/cpu/intel/Kconfig trunk/src/cpu/intel/model_106cx/Config.lb Log: Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/Kconfig =================================================================== --- trunk/src/cpu/intel/Kconfig 2009-11-03 15:02:15 UTC (rev 4907) +++ trunk/src/cpu/intel/Kconfig 2009-11-04 12:18:44 UTC (rev 4908) @@ -3,6 +3,7 @@ source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig +source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/bga956/Kconfig source src/cpu/intel/ep80579/Kconfig @@ -13,3 +14,4 @@ #source src/cpu/intel/socket_mPGA603/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig +source src/cpu/intel/socket_441/Kconfig Modified: trunk/src/cpu/intel/model_106cx/Config.lb =================================================================== --- trunk/src/cpu/intel/model_106cx/Config.lb 2009-11-03 15:02:15 UTC (rev 4907) +++ trunk/src/cpu/intel/model_106cx/Config.lb 2009-11-04 12:18:44 UTC (rev 4908) @@ -28,4 +28,4 @@ dir /cpu/intel/microcode dir /cpu/intel/hyperthreading dir /cpu/intel/speedstep -driver model_6cx_init.o +driver model_106cx_init.o Added: trunk/src/cpu/intel/model_106cx/Kconfig =================================================================== --- trunk/src/cpu/intel/model_106cx/Kconfig (rev 0) +++ trunk/src/cpu/intel/model_106cx/Kconfig 2009-11-04 12:18:44 UTC (rev 4908) @@ -0,0 +1,3 @@ +config CPU_INTEL_ATOM_230 + bool + select SMP Added: trunk/src/cpu/intel/model_106cx/Makefile.inc =================================================================== --- trunk/src/cpu/intel/model_106cx/Makefile.inc (rev 0) +++ trunk/src/cpu/intel/model_106cx/Makefile.inc 2009-11-04 12:18:44 UTC (rev 4908) @@ -0,0 +1 @@ +driver-y += model_106cx_init.o Copied: trunk/src/cpu/intel/model_106cx/model_106cx_init.c (from rev 4907, trunk/src/cpu/intel/model_106cx/model_6cx_init.c) =================================================================== --- trunk/src/cpu/intel/model_106cx/model_106cx_init.c (rev 0) +++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c 2009-11-04 12:18:44 UTC (rev 4908) @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/hyperthreading.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <usbdebug_direct.h> + +static const uint32_t microcode_updates[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +#define IA32_FEATURE_CONTROL 0x003a + +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + if (regs.ecx & CPUID_VMX) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +#define PMG_CST_CONFIG_CONTROL 0xe2 +#define PMG_IO_BASE_ADDR 0xe3 +#define PMG_IO_CAPTURE_ADDR 0xe4 +#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */ +#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state. + See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */ +#define HIGHEST_CLEVEL 3 +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 15); // Lock configuration + msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(PMG_CST_CONFIG_CONTROL, msr); + + // set P_BLK address + msr = rdmsr(PMG_IO_BASE_ADDR); + msr.lo = (PMB0 + 4) | (PMB1 << 16); + wrmsr(PMG_IO_BASE_ADDR, msr); + + // set C_LVL controls + msr = rdmsr(PMG_IO_CAPTURE_ADDR); + msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted + wrmsr(PMG_IO_CAPTURE_ADDR, msr); +} + +#define IA32_MISC_ENABLE 0x1a0 +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + + // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + + // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + +static void model_106cx_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk_info("CPU: %s.\n", processor_name); + +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + setup_lapic(); + + /* Enable virtualization */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* TODO: PIC thermal sensor control */ + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_106cx_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + Deleted: trunk/src/cpu/intel/model_106cx/model_6cx_init.c =================================================================== --- trunk/src/cpu/intel/model_106cx/model_6cx_init.c 2009-11-03 15:02:15 UTC (rev 4907) +++ trunk/src/cpu/intel/model_106cx/model_6cx_init.c 2009-11-04 12:18:44 UTC (rev 4908) @@ -1,224 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/intel/hyperthreading.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> -#include <usbdebug_direct.h> - -static const uint32_t microcode_updates[] = { - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - -static inline void strcpy(char *dst, char *src) -{ - while (*src) *dst++ = *src++; -} - -static void fill_processor_name(char *processor_name) -{ - struct cpuid_result regs; - char temp_processor_name[49]; - char *processor_name_start; - unsigned int *name_as_ints = (unsigned int *)temp_processor_name; - int i; - - for (i=0; i<3; i++) { - regs = cpuid(0x80000002 + i); - name_as_ints[i*4 + 0] = regs.eax; - name_as_ints[i*4 + 1] = regs.ebx; - name_as_ints[i*4 + 2] = regs.ecx; - name_as_ints[i*4 + 3] = regs.edx; - } - - temp_processor_name[48] = 0; - - /* Skip leading spaces */ - processor_name_start = temp_processor_name; - while (*processor_name_start == ' ') - processor_name_start++; - - memset(processor_name, 0, 49); - strcpy(processor_name, processor_name_start); -} - -#define IA32_FEATURE_CONTROL 0x003a - -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -static void enable_vmx(void) -{ - struct cpuid_result regs; - msr_t msr; - - msr = rdmsr(IA32_FEATURE_CONTROL); - - if (msr.lo & (1 << 0)) { - /* VMX locked. If we set it again we get an illegal - * instruction - */ - return; - } - - regs = cpuid(1); - if (regs.ecx & CPUID_VMX) { - msr.lo |= (1 << 2); - if (regs.ecx & CPUID_SMX) - msr.lo |= (1 << 1); - } - - wrmsr(IA32_FEATURE_CONTROL, msr); - - msr.lo |= (1 << 0); /* Set lock bit */ - - wrmsr(IA32_FEATURE_CONTROL, msr); -} - -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */ -#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state. - See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */ -#define HIGHEST_CLEVEL 3 -static void configure_c_states(void) -{ - msr_t msr; - - msr = rdmsr(PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // Lock configuration - msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(PMG_CST_CONFIG_CONTROL, msr); - - // set P_BLK address - msr = rdmsr(PMG_IO_BASE_ADDR); - msr.lo = (PMB0 + 4) | (PMB1 << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); - - // set C_LVL controls - msr = rdmsr(PMG_IO_CAPTURE_ADDR); - msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); -} - -#define IA32_MISC_ENABLE 0x1a0 -static void configure_misc(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 3); /* TM1 enable */ - msr.lo |= (1 << 13); /* TM2 enable */ - msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ - - msr.lo |= (1 << 10); /* FERR# multiplexing */ - - // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - - // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(IA32_MISC_ENABLE, msr); - - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); -} - -#if CONFIG_USBDEBUG_DIRECT -static unsigned ehci_debug_addr; -#endif - -static void model_6ex_init(device_t cpu) -{ - char processor_name[49]; - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Update the microcode */ - intel_update_microcode(microcode_updates); - - /* Print processor name */ - fill_processor_name(processor_name); - printk_info("CPU: %s.\n", processor_name); - -#if CONFIG_USBDEBUG_DIRECT - // Is this caution really needed? - if(!ehci_debug_addr) - ehci_debug_addr = get_ehci_debug(); - set_ehci_debug(0); -#endif - - /* Setup MTRRs */ - x86_setup_mtrrs(36); - x86_mtrr_check(); - -#if CONFIG_USBDEBUG_DIRECT - set_ehci_debug(ehci_debug_addr); -#endif - - /* Enable the local cpu apics */ - setup_lapic(); - - /* Enable virtualization */ - enable_vmx(); - - /* Configure C States */ - configure_c_states(); - - /* Configure Enhanced SpeedStep and Thermal Sensors */ - configure_misc(); - - /* TODO: PIC thermal sensor control */ - - /* Start up my cpu siblings */ - intel_sibling_init(cpu); -} - -static struct device_operations cpu_dev_ops = { - .init = model_6ex_init, -}; - -static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */ - { X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */ - { X86_VENDOR_INTEL, 0x06ec }, /* Intel Core Solo/Core Duo */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; - Added: trunk/src/cpu/intel/socket_441/Kconfig =================================================================== --- trunk/src/cpu/intel/socket_441/Kconfig (rev 0) +++ trunk/src/cpu/intel/socket_441/Kconfig 2009-11-04 12:18:44 UTC (rev 4908) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_441 + bool + select CPU_INTEL_MODEL_106CX + select MMX + select SSE Added: trunk/src/cpu/intel/socket_441/Makefile.inc =================================================================== --- trunk/src/cpu/intel/socket_441/Makefile.inc (rev 0) +++ trunk/src/cpu/intel/socket_441/Makefile.inc 2009-11-04 12:18:44 UTC (rev 4908) @@ -0,0 +1,10 @@ +obj-y += socket_441.o +subdirs-y += ../model_106cx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading +

1 0

[PATCH] x86emu: add SMSW, RDMSR, WRMSR, INVD, WBINVD
by Stefan Reinauer 04 Nov '09

04 Nov '09

See patch.. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 x86emu: Add support for the following opcodes: * SMSW * INVD * WBINVD * RDMSR * WRMSR The implementation is kept very simple (mostly dummies) but it should get us successfully through the Poulsbo VGA OPROM code in order to determine further requirements. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: util/x86emu/x86emu/ops2.c =================================================================== --- util/x86emu/x86emu/ops2.c (revision 4905) +++ util/x86emu/x86emu/ops2.c (working copy) @@ -49,8 +49,7 @@ REMARKS: Handles illegal opcodes. ****************************************************************************/ -void x86emuOp2_illegal_op( - u8 op2) +void x86emuOp2_illegal_op(u8 op2) { START_OF_INSTR(); DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); @@ -61,6 +60,98 @@ END_OF_INSTR(); } +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x01 + * ****************************************************************************/ + +static void x86emuOp2_opc_01(u8 op2) +{ + int mod, rl, rh; + u16 *destreg; + + /* dummy implementation: smsw always returns 0 */ + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + + if(rh == 4 && mod == 3) { + DECODE_PRINTF("SMSW\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + *destreg = 0; + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + } + else { + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-2,op2); + HALT_SYS(); + } + + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x08 + * ****************************************************************************/ +static void x86emuOp2_invd(u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("INVD\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x09 + * ****************************************************************************/ +static void x86emuOp2_wbinvd(u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("WBINVD\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x30 + * ****************************************************************************/ +static void x86emuOp2_wrmsr(u8 op2) +{ + /* dummy implementation, does nothing */ + + START_OF_INSTR(); + DECODE_PRINTF("WRMSR\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x32 + * ****************************************************************************/ +static void x86emuOp2_rdmsr(u8 op2) +{ + /* dummy implementation, always return 0 */ + + START_OF_INSTR(); + DECODE_PRINTF("RDMSR\n"); + TRACE_AND_STEP(); + M.x86.R_EDX = 0; + M.x86.R_EAX = 0; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + #define xorl(a,b) (((a) && !(b)) || (!(a) && (b))) /**************************************************************************** @@ -1552,15 +1643,15 @@ void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ -/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x01 */ x86emuOp2_opc_01, /* Group G (ring 0 PM) */ /* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ /* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ /* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ -/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x08 */ x86emuOp2_invd, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_wbinvd, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, /* 0x0c */ x86emuOp2_illegal_op, @@ -1602,9 +1693,9 @@ /* 0x2e */ x86emuOp2_illegal_op, /* 0x2f */ x86emuOp2_illegal_op, -/* 0x30 */ x86emuOp2_illegal_op, +/* 0x30 */ x86emuOp2_wrmsr, /* 0x31 */ x86emuOp2_illegal_op, -/* 0x32 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_rdmsr, /* 0x33 */ x86emuOp2_illegal_op, /* 0x34 */ x86emuOp2_illegal_op, /* 0x35 */ x86emuOp2_illegal_op,

3 4

[PATCH] Atom 106cx fixes
by Stefan Reinauer 03 Nov '09

03 Nov '09

See patch Some fixes. Atom does not like 36bit MTRRs in CAR setup. Enable XIP setup again (works with 32bit MTRRs) Keep code more similar to 6ex code.. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/cpu/intel/model_106cx/cache_as_ram_post.c =================================================================== --- src/cpu/intel/model_106cx/cache_as_ram_post.c (revision 2551) +++ src/cpu/intel/model_106cx/cache_as_ram_post.c (working copy) @@ -62,7 +62,7 @@ "wrmsr\n" "movl $MTRRphysMask_MSR(0), %ecx\n" "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" - "movl $0x0000000f, %edx\n" // 36bit address space + "movl $0x00000000, %edx\n" "wrmsr\n" "movb $0x35, %al\noutb %al, $0x80\n" #endif @@ -99,7 +99,7 @@ "wrmsr\n" "movl $MTRRphysMask_MSR(0), %ecx\n" "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" - "movl $0x0000000f, %edx\n" // 36bit address space + "movl $0x00000000, %edx\n" "wrmsr\n" "movb $0x39, %al\noutb %al, $0x80\n" Index: src/cpu/intel/model_106cx/cache_as_ram.inc =================================================================== --- src/cpu/intel/model_106cx/cache_as_ram.inc (revision 2551) +++ src/cpu/intel/model_106cx/cache_as_ram.inc (working copy) @@ -103,7 +103,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif post_code(0x29) /* Enable Cache As RAM mode by disabling cache */ @@ -111,29 +110,33 @@ orl $(1 << 30), %eax movl %eax, %cr0 -#if 0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) - /* Enable cache for our code in Flash because we do CONFIG_XIP here */ + /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $0x00000000, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#endif post_code(0x2a) /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */

2 2

[v2] r4907 - trunk/src/cpu/intel/model_106cx
by svn＠coreboot.org 03 Nov '09

03 Nov '09

Author: stepan Date: 2009-11-03 16:02:15 +0100 (Tue, 03 Nov 2009) New Revision: 4907 Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c Log: Some fixes. Atom does not like 36bit MTRRs in CAR setup. Enable XIP setup again (works with 32bit MTRRs) Keep code more similar to 6ex code.. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc =================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc 2009-11-03 14:59:43 UTC (rev 4906) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc 2009-11-03 15:02:15 UTC (rev 4907) @@ -103,7 +103,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif post_code(0x29) /* Enable Cache As RAM mode by disabling cache */ @@ -111,29 +110,33 @@ orl $(1 << 30), %eax movl %eax, %cr0 -#if 0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) - /* Enable cache for our code in Flash because we do CONFIG_XIP here */ + /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $0x00000000, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#endif post_code(0x2a) /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */ Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c =================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2009-11-03 14:59:43 UTC (rev 4906) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2009-11-03 15:02:15 UTC (rev 4907) @@ -60,7 +60,7 @@ "wrmsr\n" "movl $MTRRphysMask_MSR(0), %ecx\n" "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" - "movl $0x0000000f, %edx\n" // 36bit address space + "movl $0x00000000, %edx\n" "wrmsr\n" "movb $0x35, %al\noutb %al, $0x80\n" #endif @@ -97,7 +97,7 @@ "wrmsr\n" "movl $MTRRphysMask_MSR(0), %ecx\n" "movl $(~(1024*1024 -1) | (1 << 11)), %eax\n" - "movl $0x0000000f, %edx\n" // 36bit address space + "movl $0x00000000, %edx\n" "wrmsr\n" "movb $0x39, %al\noutb %al, $0x80\n"

1 0

[v2] r4906 - in trunk/util/x86emu: include/x86emu x86emu
by svn＠coreboot.org 03 Nov '09

03 Nov '09

Author: stepan Date: 2009-11-03 15:59:43 +0100 (Tue, 03 Nov 2009) New Revision: 4906 Modified: trunk/util/x86emu/include/x86emu/x86emu.h trunk/util/x86emu/x86emu/decode.c trunk/util/x86emu/x86emu/ops.c trunk/util/x86emu/x86emu/ops.h trunk/util/x86emu/x86emu/ops2.c trunk/util/x86emu/x86emu/prim_ops.c trunk/util/x86emu/x86emu/prim_ops.h trunk/util/x86emu/x86emu/sys.c Log: x86emu: Add support for the following opcodes: * SMSW * INVD/WBINVD * RDMSR/WRMSR * CPUID The implementation is kept very simple (mostly dummies) but it should get us successfully through the Poulsbo VGA OPROM code in order to determine further requirements. Also, fix up a lot of warnings (mostly about missing prototypes for functions that should be static anyways) This version adds a break in smsw that was missing in the patch that was sent to the list. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/x86emu/include/x86emu/x86emu.h =================================================================== --- trunk/util/x86emu/include/x86emu/x86emu.h 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/include/x86emu/x86emu.h 2009-11-03 14:59:43 UTC (rev 4906) @@ -44,6 +44,7 @@ /* FIXME: redefine printk for the moment */ #ifdef CONFIG_COREBOOT_V2 +#include <stddef.h> #include <console/console.h> #undef printk #define printk(x...) do_printk(BIOS_DEBUG, x) @@ -160,7 +161,7 @@ void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); void X86EMU_prepareForInt(int num); -//void X86EMU_setMemBase(void *base, size_t size); +void X86EMU_setMemBase(void *base, size_t size); /* decode.c */ Modified: trunk/util/x86emu/x86emu/decode.c =================================================================== --- trunk/util/x86emu/x86emu/decode.c 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/decode.c 2009-11-03 14:59:43 UTC (rev 4906) @@ -735,7 +735,7 @@ Decodes scale/index of SIB byte and returns relevant offset part of effective address. ****************************************************************************/ -unsigned decode_sib_si( +static unsigned decode_sib_si( int scale, int index) { @@ -785,7 +785,7 @@ REMARKS: Decodes SIB addressing byte and returns calculated effective address. ****************************************************************************/ -unsigned decode_sib_address( +static unsigned decode_sib_address( int mod) { int sib = fetch_byte_imm(); Modified: trunk/util/x86emu/x86emu/ops.c =================================================================== --- trunk/util/x86emu/x86emu/ops.c 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/ops.c 2009-11-03 14:59:43 UTC (rev 4906) @@ -171,7 +171,7 @@ REMARKS: Handles illegal opcodes. ****************************************************************************/ -void x86emuOp_illegal_op( +static void x86emuOp_illegal_op( u8 op1) { START_OF_INSTR(); @@ -198,7 +198,7 @@ REMARKS: Handles opcodes 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38 ****************************************************************************/ -void x86emuOp_genop_byte_RM_R(u8 op1) +static void x86emuOp_genop_byte_RM_R(u8 op1) { int mod, rl, rh; uint destoffset; @@ -239,7 +239,7 @@ REMARKS: Handles opcodes 0x01, 0x09, 0x11, 0x19, 0x21, 0x29, 0x31, 0x39 ****************************************************************************/ -void x86emuOp_genop_word_RM_R(u8 op1) +static void x86emuOp_genop_word_RM_R(u8 op1) { int mod, rl, rh; uint destoffset; @@ -307,7 +307,7 @@ REMARKS: Handles opcodes 0x02, 0x0a, 0x12, 0x1a, 0x22, 0x2a, 0x32, 0x3a ****************************************************************************/ -void x86emuOp_genop_byte_R_RM(u8 op1) +static void x86emuOp_genop_byte_R_RM(u8 op1) { int mod, rl, rh; u8 *destreg, *srcreg; @@ -343,7 +343,7 @@ REMARKS: Handles opcodes 0x03, 0x0b, 0x13, 0x1b, 0x23, 0x2b, 0x33, 0x3b ****************************************************************************/ -void x86emuOp_genop_word_R_RM(u8 op1) +static void x86emuOp_genop_word_R_RM(u8 op1) { int mod, rl, rh; uint srcoffset; @@ -400,7 +400,7 @@ REMARKS: Handles opcodes 0x04, 0x0c, 0x14, 0x1c, 0x24, 0x2c, 0x34, 0x3c ****************************************************************************/ -void x86emuOp_genop_byte_AL_IMM(u8 op1) +static void x86emuOp_genop_byte_AL_IMM(u8 op1) { u8 srcval; @@ -421,7 +421,7 @@ REMARKS: Handles opcodes 0x05, 0x0d, 0x15, 0x1d, 0x25, 0x2d, 0x35, 0x3d ****************************************************************************/ -void x86emuOp_genop_word_AX_IMM(u8 op1) +static void x86emuOp_genop_word_AX_IMM(u8 op1) { u32 srcval; @@ -452,7 +452,7 @@ REMARKS: Handles opcode 0x06 ****************************************************************************/ -void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tES\n"); @@ -466,7 +466,7 @@ REMARKS: Handles opcode 0x07 ****************************************************************************/ -void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tES\n"); @@ -480,7 +480,7 @@ REMARKS: Handles opcode 0x0e ****************************************************************************/ -void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tCS\n"); @@ -494,7 +494,7 @@ REMARKS: Handles opcode 0x0f. Escape for two-byte opcode (286 or better) ****************************************************************************/ -void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) { u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); @@ -505,7 +505,7 @@ REMARKS: Handles opcode 0x16 ****************************************************************************/ -void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tSS\n"); @@ -519,7 +519,7 @@ REMARKS: Handles opcode 0x17 ****************************************************************************/ -void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tSS\n"); @@ -533,7 +533,7 @@ REMARKS: Handles opcode 0x1e ****************************************************************************/ -void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tDS\n"); @@ -547,7 +547,7 @@ REMARKS: Handles opcode 0x1f ****************************************************************************/ -void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("POP\tDS\n"); @@ -561,7 +561,7 @@ REMARKS: Handles opcode 0x26 ****************************************************************************/ -void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("ES:\n"); @@ -578,7 +578,7 @@ REMARKS: Handles opcode 0x27 ****************************************************************************/ -void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DAA\n"); @@ -592,7 +592,7 @@ REMARKS: Handles opcode 0x2e ****************************************************************************/ -void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("CS:\n"); @@ -606,7 +606,7 @@ REMARKS: Handles opcode 0x2f ****************************************************************************/ -void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_das(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DAS\n"); @@ -620,7 +620,7 @@ REMARKS: Handles opcode 0x36 ****************************************************************************/ -void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("SS:\n"); @@ -634,7 +634,7 @@ REMARKS: Handles opcode 0x37 ****************************************************************************/ -void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("AAA\n"); @@ -648,7 +648,7 @@ REMARKS: Handles opcode 0x3e ****************************************************************************/ -void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DS:\n"); @@ -662,7 +662,7 @@ REMARKS: Handles opcode 0x3f ****************************************************************************/ -void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("AAS\n"); @@ -676,7 +676,7 @@ REMARKS: Handles opcode 0x40 - 0x47 ****************************************************************************/ -void x86emuOp_inc_register(u8 op1) +static void x86emuOp_inc_register(u8 op1) { START_OF_INSTR(); op1 &= 0x7; @@ -702,7 +702,7 @@ REMARKS: Handles opcode 0x48 - 0x4F ****************************************************************************/ -void x86emuOp_dec_register(u8 op1) +static void x86emuOp_dec_register(u8 op1) { START_OF_INSTR(); op1 &= 0x7; @@ -728,7 +728,7 @@ REMARKS: Handles opcode 0x50 - 0x57 ****************************************************************************/ -void x86emuOp_push_register(u8 op1) +static void x86emuOp_push_register(u8 op1) { START_OF_INSTR(); op1 &= 0x7; @@ -754,7 +754,7 @@ REMARKS: Handles opcode 0x58 - 0x5F ****************************************************************************/ -void x86emuOp_pop_register(u8 op1) +static void x86emuOp_pop_register(u8 op1) { START_OF_INSTR(); op1 &= 0x7; @@ -780,7 +780,7 @@ REMARKS: Handles opcode 0x60 ****************************************************************************/ -void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -820,7 +820,7 @@ REMARKS: Handles opcode 0x61 ****************************************************************************/ -void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -859,7 +859,7 @@ REMARKS: Handles opcode 0x64 ****************************************************************************/ -void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("FS:\n"); @@ -876,7 +876,7 @@ REMARKS: Handles opcode 0x65 ****************************************************************************/ -void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("GS:\n"); @@ -893,7 +893,7 @@ REMARKS: Handles opcode 0x66 - prefix for 32-bit register ****************************************************************************/ -void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("DATA:\n"); @@ -907,7 +907,7 @@ REMARKS: Handles opcode 0x67 - prefix for 32-bit address ****************************************************************************/ -void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("ADDR:\n"); @@ -921,7 +921,7 @@ REMARKS: Handles opcode 0x68 ****************************************************************************/ -void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) { u32 imm; @@ -946,7 +946,7 @@ REMARKS: Handles opcode 0x69 ****************************************************************************/ -void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; @@ -1053,7 +1053,7 @@ REMARKS: Handles opcode 0x6a ****************************************************************************/ -void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) { s16 imm; @@ -1074,7 +1074,7 @@ REMARKS: Handles opcode 0x6b ****************************************************************************/ -void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; @@ -1179,7 +1179,7 @@ REMARKS: Handles opcode 0x6c ****************************************************************************/ -void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("INSB\n"); @@ -1193,7 +1193,7 @@ REMARKS: Handles opcode 0x6d ****************************************************************************/ -void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -1212,7 +1212,7 @@ REMARKS: Handles opcode 0x6e ****************************************************************************/ -void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("OUTSB\n"); @@ -1226,7 +1226,7 @@ REMARKS: Handles opcode 0x6f ****************************************************************************/ -void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -1245,9 +1245,7 @@ REMARKS: Handles opcode 0x70 - 0x7F ****************************************************************************/ -int x86emu_check_jump_condition(u8 op); - -void x86emuOp_jump_near_cond(u8 op1) +static void x86emuOp_jump_near_cond(u8 op1) { s8 offset; u16 target; @@ -1272,7 +1270,7 @@ REMARKS: Handles opcode 0x80 ****************************************************************************/ -void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -1351,7 +1349,7 @@ REMARKS: Handles opcode 0x81 ****************************************************************************/ -void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -1457,7 +1455,7 @@ REMARKS: Handles opcode 0x82 ****************************************************************************/ -void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -1534,7 +1532,7 @@ REMARKS: Handles opcode 0x83 ****************************************************************************/ -void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -1635,7 +1633,7 @@ REMARKS: Handles opcode 0x84 ****************************************************************************/ -void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; @@ -1669,7 +1667,7 @@ REMARKS: Handles opcode 0x85 ****************************************************************************/ -void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -1729,7 +1727,7 @@ REMARKS: Handles opcode 0x86 ****************************************************************************/ -void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; @@ -1769,7 +1767,7 @@ REMARKS: Handles opcode 0x87 ****************************************************************************/ -void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -1840,7 +1838,7 @@ REMARKS: Handles opcode 0x88 ****************************************************************************/ -void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; @@ -1872,7 +1870,7 @@ REMARKS: Handles opcode 0x89 ****************************************************************************/ -void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -1928,7 +1926,7 @@ REMARKS: Handles opcode 0x8a ****************************************************************************/ -void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg, *srcreg; @@ -1962,7 +1960,7 @@ REMARKS: Handles opcode 0x8b ****************************************************************************/ -void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; @@ -2023,7 +2021,7 @@ REMARKS: Handles opcode 0x8c ****************************************************************************/ -void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *destreg, *srcreg; @@ -2057,7 +2055,7 @@ REMARKS: Handles opcode 0x8d ****************************************************************************/ -void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *srcreg; @@ -2089,7 +2087,7 @@ REMARKS: Handles opcode 0x8e ****************************************************************************/ -void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u16 *destreg, *srcreg; @@ -2129,7 +2127,7 @@ REMARKS: Handles opcode 0x8f ****************************************************************************/ -void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -2183,7 +2181,7 @@ REMARKS: Handles opcode 0x90 ****************************************************************************/ -void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("NOP\n"); @@ -2196,7 +2194,7 @@ REMARKS: Handles opcode 0x91-0x97 ****************************************************************************/ -void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) { u32 tmp; @@ -2231,7 +2229,7 @@ REMARKS: Handles opcode 0x98 ****************************************************************************/ -void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -2261,7 +2259,7 @@ REMARKS: Handles opcode 0x99 ****************************************************************************/ -void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -2292,7 +2290,7 @@ REMARKS: Handles opcode 0x9a ****************************************************************************/ -void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 farseg, faroff; @@ -2323,7 +2321,7 @@ REMARKS: Handles opcode 0x9b ****************************************************************************/ -void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("WAIT"); @@ -2337,7 +2335,7 @@ REMARKS: Handles opcode 0x9c ****************************************************************************/ -void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) { u32 flags; @@ -2364,7 +2362,7 @@ REMARKS: Handles opcode 0x9d ****************************************************************************/ -void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -2386,7 +2384,7 @@ REMARKS: Handles opcode 0x9e ****************************************************************************/ -void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("SAHF\n"); @@ -2403,7 +2401,7 @@ REMARKS: Handles opcode 0x9f ****************************************************************************/ -void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LAHF\n"); @@ -2420,7 +2418,7 @@ REMARKS: Handles opcode 0xa0 ****************************************************************************/ -void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; @@ -2438,7 +2436,7 @@ REMARKS: Handles opcode 0xa1 ****************************************************************************/ -void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; @@ -2463,7 +2461,7 @@ REMARKS: Handles opcode 0xa2 ****************************************************************************/ -void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; @@ -2481,7 +2479,7 @@ REMARKS: Handles opcode 0xa3 ****************************************************************************/ -void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) { u16 offset; @@ -2506,7 +2504,7 @@ REMARKS: Handles opcode 0xa4 ****************************************************************************/ -void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) { u8 val; u32 count; @@ -2545,7 +2543,7 @@ REMARKS: Handles opcode 0xa5 ****************************************************************************/ -void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) { u32 val; int inc; @@ -2597,7 +2595,7 @@ REMARKS: Handles opcode 0xa6 ****************************************************************************/ -void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) { s8 val1, val2; int inc; @@ -2644,7 +2642,7 @@ REMARKS: Handles opcode 0xa7 ****************************************************************************/ -void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) { u32 val1,val2; int inc; @@ -2707,7 +2705,7 @@ REMARKS: Handles opcode 0xa8 ****************************************************************************/ -void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) { int imm; @@ -2725,7 +2723,7 @@ REMARKS: Handles opcode 0xa9 ****************************************************************************/ -void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; @@ -2752,7 +2750,7 @@ REMARKS: Handles opcode 0xaa ****************************************************************************/ -void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) { int inc; @@ -2789,7 +2787,7 @@ REMARKS: Handles opcode 0xab ****************************************************************************/ -void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 count; @@ -2837,7 +2835,7 @@ REMARKS: Handles opcode 0xac ****************************************************************************/ -void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) { int inc; @@ -2874,7 +2872,7 @@ REMARKS: Handles opcode 0xad ****************************************************************************/ -void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 count; @@ -2922,7 +2920,7 @@ REMARKS: Handles opcode 0xae ****************************************************************************/ -void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) { s8 val2; int inc; @@ -2981,7 +2979,7 @@ REMARKS: Handles opcode 0xaf ****************************************************************************/ -void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) { int inc; u32 val; @@ -3063,7 +3061,7 @@ REMARKS: Handles opcode 0xb0 - 0xb7 ****************************************************************************/ -void x86emuOp_mov_byte_register_IMM(u8 op1) +static void x86emuOp_mov_byte_register_IMM(u8 op1) { u8 imm, *ptr; @@ -3083,7 +3081,7 @@ REMARKS: Handles opcode 0xb8 - 0xbf ****************************************************************************/ -void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) { u32 srcval; @@ -3114,7 +3112,7 @@ REMARKS: Handles opcode 0xc0 ****************************************************************************/ -void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -3191,7 +3189,7 @@ REMARKS: Handles opcode 0xc1 ****************************************************************************/ -void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -3292,7 +3290,7 @@ REMARKS: Handles opcode 0xc2 ****************************************************************************/ -void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) { u16 imm; @@ -3312,7 +3310,7 @@ REMARKS: Handles opcode 0xc3 ****************************************************************************/ -void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("RET\n"); @@ -3327,7 +3325,7 @@ REMARKS: Handles opcode 0xc4 ****************************************************************************/ -void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u16 *dstreg; @@ -3355,7 +3353,7 @@ REMARKS: Handles opcode 0xc5 ****************************************************************************/ -void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u16 *dstreg; @@ -3382,7 +3380,7 @@ REMARKS: Handles opcode 0xc6 ****************************************************************************/ -void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -3418,7 +3416,7 @@ REMARKS: Handles opcode 0xc7 ****************************************************************************/ -void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -3479,7 +3477,7 @@ REMARKS: Handles opcode 0xc8 ****************************************************************************/ -void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) { u16 local,frame_pointer; u8 nesting; @@ -3510,7 +3508,7 @@ REMARKS: Handles opcode 0xc9 ****************************************************************************/ -void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LEAVE\n"); @@ -3525,7 +3523,7 @@ REMARKS: Handles opcode 0xca ****************************************************************************/ -void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 imm; @@ -3546,7 +3544,7 @@ REMARKS: Handles opcode 0xcb ****************************************************************************/ -void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("RETF\n"); @@ -3562,7 +3560,7 @@ REMARKS: Handles opcode 0xcc ****************************************************************************/ -void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) { u16 tmp; @@ -3590,7 +3588,7 @@ REMARKS: Handles opcode 0xcd ****************************************************************************/ -void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) { u16 tmp; u8 intnum; @@ -3620,7 +3618,7 @@ REMARKS: Handles opcode 0xce ****************************************************************************/ -void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) { u16 tmp; @@ -3649,7 +3647,7 @@ REMARKS: Handles opcode 0xcf ****************************************************************************/ -void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("IRET\n"); @@ -3667,7 +3665,7 @@ REMARKS: Handles opcode 0xd0 ****************************************************************************/ -void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -3740,7 +3738,7 @@ REMARKS: Handles opcode 0xd1 ****************************************************************************/ -void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -3839,7 +3837,7 @@ REMARKS: Handles opcode 0xd2 ****************************************************************************/ -void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -3914,7 +3912,7 @@ REMARKS: Handles opcode 0xd3 ****************************************************************************/ -void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -4011,7 +4009,7 @@ REMARKS: Handles opcode 0xd4 ****************************************************************************/ -void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) { u8 a; @@ -4034,7 +4032,7 @@ REMARKS: Handles opcode 0xd5 ****************************************************************************/ -void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) { u8 a; @@ -4053,7 +4051,7 @@ REMARKS: Handles opcode 0xd7 ****************************************************************************/ -void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) { u16 addr; @@ -4072,7 +4070,7 @@ REMARKS: Handles opcode 0xe0 ****************************************************************************/ -void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) { s16 ip; @@ -4096,7 +4094,7 @@ REMARKS: Handles opcode 0xe1 ****************************************************************************/ -void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) { s16 ip; @@ -4120,7 +4118,7 @@ REMARKS: Handles opcode 0xe2 ****************************************************************************/ -void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) { s16 ip; @@ -4144,7 +4142,7 @@ REMARKS: Handles opcode 0xe3 ****************************************************************************/ -void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) { u16 target; s8 offset; @@ -4168,7 +4166,7 @@ REMARKS: Handles opcode 0xe4 ****************************************************************************/ -void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) { u8 port; @@ -4186,7 +4184,7 @@ REMARKS: Handles opcode 0xe5 ****************************************************************************/ -void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) { u8 port; @@ -4212,7 +4210,7 @@ REMARKS: Handles opcode 0xe6 ****************************************************************************/ -void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) { u8 port; @@ -4230,7 +4228,7 @@ REMARKS: Handles opcode 0xe7 ****************************************************************************/ -void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) { u8 port; @@ -4256,7 +4254,7 @@ REMARKS: Handles opcode 0xe8 ****************************************************************************/ -void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) { s16 ip; @@ -4277,7 +4275,7 @@ REMARKS: Handles opcode 0xe9 ****************************************************************************/ -void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) { int ip; @@ -4297,7 +4295,7 @@ REMARKS: Handles opcode 0xea ****************************************************************************/ -void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) { u16 cs, ip; @@ -4319,7 +4317,7 @@ REMARKS: Handles opcode 0xeb ****************************************************************************/ -void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) { u16 target; s8 offset; @@ -4340,7 +4338,7 @@ REMARKS: Handles opcode 0xec ****************************************************************************/ -void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("IN\tAL,DX\n"); @@ -4354,7 +4352,7 @@ REMARKS: Handles opcode 0xed ****************************************************************************/ -void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -4376,7 +4374,7 @@ REMARKS: Handles opcode 0xee ****************************************************************************/ -void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("OUT\tDX,AL\n"); @@ -4390,7 +4388,7 @@ REMARKS: Handles opcode 0xef ****************************************************************************/ -void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { @@ -4412,7 +4410,7 @@ REMARKS: Handles opcode 0xf0 ****************************************************************************/ -void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("LOCK:\n"); @@ -4427,7 +4425,7 @@ REMARKS: Handles opcode 0xf2 ****************************************************************************/ -void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("REPNE\n"); @@ -4443,7 +4441,7 @@ REMARKS: Handles opcode 0xf3 ****************************************************************************/ -void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("REPE\n"); @@ -4459,7 +4457,7 @@ REMARKS: Handles opcode 0xf4 ****************************************************************************/ -void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); DECODE_PRINTF("HALT\n"); @@ -4473,7 +4471,7 @@ REMARKS: Handles opcode 0xf5 ****************************************************************************/ -void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) { /* complement the carry flag. */ START_OF_INSTR(); @@ -4488,7 +4486,7 @@ REMARKS: Handles opcode 0xf6 ****************************************************************************/ -void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; u8 *destreg; @@ -4604,7 +4602,7 @@ REMARKS: Handles opcode 0xf7 ****************************************************************************/ -void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint destoffset; @@ -4830,7 +4828,7 @@ REMARKS: Handles opcode 0xf8 ****************************************************************************/ -void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) { /* clear the carry flag. */ START_OF_INSTR(); @@ -4845,7 +4843,7 @@ REMARKS: Handles opcode 0xf9 ****************************************************************************/ -void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) { /* set the carry flag. */ START_OF_INSTR(); @@ -4860,7 +4858,7 @@ REMARKS: Handles opcode 0xfa ****************************************************************************/ -void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); @@ -4875,7 +4873,7 @@ REMARKS: Handles opcode 0xfb ****************************************************************************/ -void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) { /* enable interrupts. */ START_OF_INSTR(); @@ -4890,7 +4888,7 @@ REMARKS: Handles opcode 0xfc ****************************************************************************/ -void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); @@ -4905,7 +4903,7 @@ REMARKS: Handles opcode 0xfd ****************************************************************************/ -void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_std(u8 X86EMU_UNUSED(op1)) { /* clear interrupts. */ START_OF_INSTR(); @@ -4920,7 +4918,7 @@ REMARKS: Handles opcode 0xfe ****************************************************************************/ -void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; u8 destval; @@ -4984,7 +4982,7 @@ REMARKS: Handles opcode 0xff ****************************************************************************/ -void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) { int mod, rh, rl; uint destoffset = 0; Modified: trunk/util/x86emu/x86emu/ops.h =================================================================== --- trunk/util/x86emu/x86emu/ops.h 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/ops.h 2009-11-03 14:59:43 UTC (rev 4906) @@ -42,4 +42,6 @@ extern void (*x86emu_optab[0x100])(u8 op1); extern void (*x86emu_optab2[0x100])(u8 op2); +int x86emu_check_jump_condition(u8 op); + #endif /* __X86EMU_OPS_H */ Modified: trunk/util/x86emu/x86emu/ops2.c =================================================================== --- trunk/util/x86emu/x86emu/ops2.c 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/ops2.c 2009-11-03 14:59:43 UTC (rev 4906) @@ -49,18 +49,129 @@ REMARKS: Handles illegal opcodes. ****************************************************************************/ -void x86emuOp2_illegal_op( - u8 op2) +static void x86emuOp2_illegal_op(u8 op2) { START_OF_INSTR(); DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2,op2); + M.x86.R_CS, M.x86.R_IP-2, op2); HALT_SYS(); END_OF_INSTR(); } +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x01 + * ****************************************************************************/ + +static void x86emuOp2_opc_01(u8 op2) +{ + int mod, rl, rh; + u16 *destreg; + uint destoffset; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch(rh) { + case 4: // SMSW (Store Machine Status Word) + // Decode the mod byte to find the addressing + // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1) +#define SMSW_INITIAL_VALUE 0x10 + DECODE_PRINTF("SMSW\t"); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + store_data_word(destoffset, SMSW_INITIAL_VALUE); + break; + case 1: + destoffset = decode_rm01_address(rl); + store_data_word(destoffset, SMSW_INITIAL_VALUE); + break; + case 2: + destoffset = decode_rm10_address(rl); + store_data_word(destoffset, SMSW_INITIAL_VALUE); + break; + case 3: + destreg = DECODE_RM_WORD_REGISTER(rl); + *destreg = SMSW_INITIAL_VALUE; + break; + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + DECODE_PRINTF("\n"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE IN 0F 01\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-2, op2); + HALT_SYS(); + break; + } + + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x08 + * ****************************************************************************/ +static void x86emuOp2_invd(u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("INVD\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x09 + * ****************************************************************************/ +static void x86emuOp2_wbinvd(u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("WBINVD\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x30 + * ****************************************************************************/ +static void x86emuOp2_wrmsr(u8 op2) +{ + /* dummy implementation, does nothing */ + + START_OF_INSTR(); + DECODE_PRINTF("WRMSR\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** + * REMARKS: + * Handles opcode 0x0f,0x32 + * ****************************************************************************/ +static void x86emuOp2_rdmsr(u8 op2) +{ + /* dummy implementation, always return 0 */ + + START_OF_INSTR(); + DECODE_PRINTF("RDMSR\n"); + TRACE_AND_STEP(); + M.x86.R_EDX = 0; + M.x86.R_EAX = 0; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + #define xorl(a,b) (((a) && !(b)) || (!(a) && (b))) /**************************************************************************** @@ -137,7 +248,7 @@ } } -void x86emuOp2_long_jump(u8 op2) +static void x86emuOp2_long_jump(u8 op2) { s32 target; int cond; @@ -161,18 +272,18 @@ REMARKS: Handles opcode 0x0f,0xC8-0xCF ****************************************************************************/ -s32 x86emu_bswap(s32 reg) +static s32 x86emu_bswap(s32 reg) { // perform the byte swap s32 temp = reg; - reg = (temp & 0xFF000000) >> 24; - reg |= (temp & 0xFF0000) >> 8; - reg |= (temp & 0xFF00) << 8; - reg |= (temp & 0xFF) << 24; + reg = (temp & 0xFF000000) >> 24 | + (temp & 0xFF0000) >> 8 | + (temp & 0xFF00) << 8 | + (temp & 0xFF) << 24; return reg; } -void x86emuOp2_bswap(u8 op2) +static void x86emuOp2_bswap(u8 op2) { /* byte swap 32 bit register */ START_OF_INSTR(); @@ -220,12 +331,12 @@ REMARKS: Handles opcode 0x0f,0x90-0x9F ****************************************************************************/ -void x86emuOp2_set_byte(u8 op2) +static void x86emuOp2_set_byte(u8 op2) { int mod, rl, rh; uint destoffset; u8 *destreg; - char *name = 0; + const char *name = 0; int cond = 0; START_OF_INSTR(); @@ -316,7 +427,7 @@ REMARKS: Handles opcode 0x0f,0xa0 ****************************************************************************/ -void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tFS\n"); @@ -330,7 +441,7 @@ REMARKS: Handles opcode 0x0f,0xa1 ****************************************************************************/ -void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("POP\tFS\n"); @@ -341,10 +452,24 @@ } /**************************************************************************** +REMARKS: CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output +Handles opcode 0x0f,0xa2 +****************************************************************************/ +static void x86emuOp2_cpuid(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CPUID\n"); + TRACE_AND_STEP(); + x86emu_cpuid(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** REMARKS: Handles opcode 0x0f,0xa3 ****************************************************************************/ -void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -407,7 +532,7 @@ REMARKS: Handles opcode 0x0f,0xa4 ****************************************************************************/ -void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; @@ -478,7 +603,7 @@ REMARKS: Handles opcode 0x0f,0xa5 ****************************************************************************/ -void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; @@ -540,7 +665,7 @@ REMARKS: Handles opcode 0x0f,0xa8 ****************************************************************************/ -void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("PUSH\tGS\n"); @@ -554,7 +679,7 @@ REMARKS: Handles opcode 0x0f,0xa9 ****************************************************************************/ -void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) { START_OF_INSTR(); DECODE_PRINTF("POP\tGS\n"); @@ -568,7 +693,7 @@ REMARKS: Handles opcode 0x0f,0xaa ****************************************************************************/ -void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -641,7 +766,7 @@ REMARKS: Handles opcode 0x0f,0xac ****************************************************************************/ -void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; @@ -712,7 +837,7 @@ REMARKS: Handles opcode 0x0f,0xad ****************************************************************************/ -void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint destoffset; @@ -773,7 +898,7 @@ REMARKS: Handles opcode 0x0f,0xaf ****************************************************************************/ -void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -865,7 +990,7 @@ REMARKS: Handles opcode 0x0f,0xb2 ****************************************************************************/ -void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; @@ -894,7 +1019,7 @@ REMARKS: Handles opcode 0x0f,0xb3 ****************************************************************************/ -void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -966,7 +1091,7 @@ REMARKS: Handles opcode 0x0f,0xb4 ****************************************************************************/ -void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; @@ -995,7 +1120,7 @@ REMARKS: Handles opcode 0x0f,0xb5 ****************************************************************************/ -void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) { int mod, rh, rl; u16 *dstreg; @@ -1024,7 +1149,7 @@ REMARKS: Handles opcode 0x0f,0xb6 ****************************************************************************/ -void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1087,7 +1212,7 @@ REMARKS: Handles opcode 0x0f,0xb7 ****************************************************************************/ -void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1122,7 +1247,7 @@ REMARKS: Handles opcode 0x0f,0xba ****************************************************************************/ -void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1258,7 +1383,7 @@ REMARKS: Handles opcode 0x0f,0xbb ****************************************************************************/ -void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1330,7 +1455,7 @@ REMARKS: Handles opcode 0x0f,0xbc ****************************************************************************/ -void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1391,7 +1516,7 @@ REMARKS: Handles opcode 0x0f,0xbd ****************************************************************************/ -void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1452,7 +1577,7 @@ REMARKS: Handles opcode 0x0f,0xbe ****************************************************************************/ -void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1515,7 +1640,7 @@ REMARKS: Handles opcode 0x0f,0xbf ****************************************************************************/ -void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) { int mod, rl, rh; uint srcoffset; @@ -1552,15 +1677,15 @@ void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ -/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x01 */ x86emuOp2_opc_01, /* Group G (ring 0 PM) */ /* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ /* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ /* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ -/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x08 */ x86emuOp2_invd, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_wbinvd, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, /* 0x0c */ x86emuOp2_illegal_op, @@ -1602,9 +1727,9 @@ /* 0x2e */ x86emuOp2_illegal_op, /* 0x2f */ x86emuOp2_illegal_op, -/* 0x30 */ x86emuOp2_illegal_op, +/* 0x30 */ x86emuOp2_wrmsr, /* 0x31 */ x86emuOp2_illegal_op, -/* 0x32 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_rdmsr, /* 0x33 */ x86emuOp2_illegal_op, /* 0x34 */ x86emuOp2_illegal_op, /* 0x35 */ x86emuOp2_illegal_op, @@ -1723,7 +1848,7 @@ /* 0xa0 */ x86emuOp2_push_FS, /* 0xa1 */ x86emuOp2_pop_FS, -/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa2 */ x86emuOp2_cpuid, /* 0xa3 */ x86emuOp2_bt_R, /* 0xa4 */ x86emuOp2_shld_IMM, /* 0xa5 */ x86emuOp2_shld_CL, @@ -1732,7 +1857,7 @@ /* 0xa8 */ x86emuOp2_push_GS, /* 0xa9 */ x86emuOp2_pop_GS, /* 0xaa */ x86emuOp2_illegal_op, -/* 0xab */ x86emuOp2_bt_R, +/* 0xab */ x86emuOp2_bts_R, /* 0xac */ x86emuOp2_shrd_IMM, /* 0xad */ x86emuOp2_shrd_CL, /* 0xae */ x86emuOp2_illegal_op, Modified: trunk/util/x86emu/x86emu/prim_ops.c =================================================================== --- trunk/util/x86emu/x86emu/prim_ops.c 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/prim_ops.c 2009-11-03 14:59:43 UTC (rev 4906) @@ -2448,3 +2448,49 @@ return res; } +/**************************************************************************** +REMARKS: +CPUID takes EAX/ECX as inputs, writes EAX/EBX/ECX/EDX as output +****************************************************************************/ +void x86emu_cpuid(void) +{ + u32 feature = M.x86.R_EAX; + + switch (feature) { + case 0: + /* Regardless if we have real data from the hardware, the emulator + * will only support upto feature 1, which we set in register EAX. + * Registers EBX:EDX:ECX contain a string identifying the CPU. + */ + M.x86.R_EAX = 1; + /* EBX:EDX:ECX = "GenuineIntel" */ + M.x86.R_EBX = 0x756e6547; + M.x86.R_EDX = 0x49656e69; + M.x86.R_ECX = 0x6c65746e; + break; + case 1: + /* If we don't have x86 compatible hardware, we return values from an + * Intel 486dx4; which was one of the first processors to have CPUID. + */ + M.x86.R_EAX = 0x00000480; + M.x86.R_EBX = 0x00000000; + M.x86.R_ECX = 0x00000000; + M.x86.R_EDX = 0x00000002; /* VME */ + /* In the case that we have hardware CPUID instruction, we make sure + * that the features reported are limited to TSC and VME. + */ + M.x86.R_EDX &= 0x00000012; + break; + default: + /* Finally, we don't support any additional features. Most CPUs + * return all zeros when queried for invalid or unsupported feature + * numbers. + */ + M.x86.R_EAX = 0; + M.x86.R_EBX = 0; + M.x86.R_ECX = 0; + M.x86.R_EDX = 0; + break; + } +} + Modified: trunk/util/x86emu/x86emu/prim_ops.h =================================================================== --- trunk/util/x86emu/x86emu/prim_ops.h 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/prim_ops.h 2009-11-03 14:59:43 UTC (rev 4906) @@ -134,7 +134,8 @@ void push_word (u16 w); void push_long (u32 w); u16 pop_word (void); -u32 pop_long (void); +u32 pop_long (void); +void x86emu_cpuid (void); #if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) Modified: trunk/util/x86emu/x86emu/sys.c =================================================================== --- trunk/util/x86emu/x86emu/sys.c 2009-11-02 15:01:49 UTC (rev 4905) +++ trunk/util/x86emu/x86emu/sys.c 2009-11-03 14:59:43 UTC (rev 4906) @@ -68,7 +68,7 @@ /*----------------------------- Implementation ----------------------------*/ /* compute a pointer. This replaces code scattered all over the place! */ -u8 *mem_ptr(u32 addr, int size) +static u8 *mem_ptr(u32 addr, int size) { u8 *retaddr = 0;

1 0

[PATCH 10/10] Add USE_CMOS_BIOS_SMP_COUNT option. If disabled, we wait 10ms instead of relying on the cpu count stored in memory.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/config.h | 1 + src/smp.c | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/config.h b/src/config.h index 754559b..a9e79cb 100644 --- a/src/config.h +++ b/src/config.h @@ -192,5 +192,6 @@ /* Options for running on the Virtutech Simics x86-440bx machine model */ #define VIRTUTECH_IRQ0_OVERRIDE 1 #define VIRTUTECH_PC_SHADOW 1 +#define USE_CMOS_BIOS_SMP_COUNT 0 #endif // config.h diff --git a/src/smp.c b/src/smp.c index b0852f8..caec5f1 100644 --- a/src/smp.c +++ b/src/smp.c @@ -105,7 +105,7 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) { + if (CONFIG_COREBOOT || !USE_CMOS_BIOS_SMP_COUNT) { msleep(10); } else { u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); -- 1.6.2.5 --------------080100040501080908060605--

1 0

[PATCH 09/10] Properly mask value for MTRR mask.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/mtrr.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mtrr.c b/src/mtrr.c index a9cd5f7..6bd0dba 100644 --- a/src/mtrr.c +++ b/src/mtrr.c @@ -29,7 +29,7 @@ void mtrr_setup(void) if (CONFIG_COREBOOT) return; - u32 eax, ebx, ecx, cpuid_features; + u32 eax, ebx, ecx, edx, cpuid_features; cpuid(1, &eax, &ebx, &ecx, &cpuid_features); if (!(cpuid_features & CPUID_MTRR)) return; @@ -73,6 +73,16 @@ void mtrr_setup(void) wrmsr_smp(MSR_MTRRfix4K_F8000, 0); /* Mark 3.5-4GB as UC, anything not specified defaults to WB */ wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0); - wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800); + + int phys_bits = 36; + cpuid(0x80000000u, &eax, &ebx, &ecx, &edx); + if (eax >= 0x80000008) { + /* Get physical bits from leaf 0x80000008 (if available) */ + cpuid(0x80000008u, &eax, &ebx, &ecx, &edx); + phys_bits = eax & 0xff; + } + u64 phys_mask = ((1ull << phys_bits) - 1); + wrmsr_smp(MTRRphysMask_MSR(0), (~(0x20000000ull - 1) & phys_mask) | 0x800); + wrmsr_smp(MSR_MTRRdefType, 0xc06); } -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0010-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0010-Add-USE_CMOS_BIOS_SMP_COUNT-option.-If-disabled-we.patc"; filename*1="h"

1 0

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coreboot November 2009