coreboot November 2009

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[PATCH 08/10] Handle Virtutech Simics x86-440bx shadowing with the VIRTUTECH_PC_SHADOW option.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/config.h | 1 + src/shadow.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 0 deletions(-) diff --git a/src/config.h b/src/config.h index 71903bb..754559b 100644 --- a/src/config.h +++ b/src/config.h @@ -191,5 +191,6 @@ /* Options for running on the Virtutech Simics x86-440bx machine model */ #define VIRTUTECH_IRQ0_OVERRIDE 1 +#define VIRTUTECH_PC_SHADOW 1 #endif // config.h diff --git a/src/shadow.c b/src/shadow.c index f0f97c5..4b7f15c 100644 --- a/src/shadow.c +++ b/src/shadow.c @@ -9,6 +9,7 @@ #include "pci.h" // pci_config_writeb #include "config.h" // CONFIG_* #include "pci_ids.h" // PCI_VENDOR_ID_INTEL +#include "ioport.h" // outb // Test if 'addr' is in the range from 'start'..'start+size' #define IN_RANGE(addr, start, size) ({ \ @@ -21,6 +22,40 @@ // On the emulators, the bios at 0xf0000 is also at 0xffff0000 #define BIOS_SRC_ADDR 0xffff0000 +#if VIRTUTECH_PC_SHADOW + +#define Read_Only 1 +#define Write_Only 2 +#define Read_Write 3 + +static void modify_shadow(unsigned long start, unsigned long len, int mode) +{ + int start_loc = ((int)(start >> 10) - 640) >> 1; + int len_remaining = len >> 11; + int i; + for (i = 0; i < len_remaining; i++) { + outb(start_loc + i, 0xfff4); + if (mode == Read_Only) { + outb(1, 0xfff5); + } else if (mode == Read_Write) { + outb(3, 0xfff5); + } else if (mode == Write_Only) { + outb(2, 0xfff5); + } else { + outb(0, 0xfff5); + } + } +} + +static void +__copy_bios(void) +{ + // Copy bios. + memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); +} + +#else + // Enable shadowing and copy bios. static void __make_bios_writable(u16 bdf) @@ -59,6 +94,8 @@ __make_bios_writable(u16 bdf) memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE); } +#endif // VIRTUTECH_PC_SHADOW + // Make the 0xc0000-0x100000 area read/writable. void make_bios_writable() @@ -68,6 +105,19 @@ make_bios_writable() dprintf(3, "enabling shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + /* Read (and execute) from PCI, write to RAM */ + modify_shadow(0xf0000, 0x10000, Write_Only); + + /* Run the copy from the high address to avoid simulator flushes after each + write (the flushes ruin performance) */ + u32 pos = (u32)__copy_bios - BUILD_BIOS_ADDR + BIOS_SRC_ADDR; + void (*func)(void) = (void*)pos; + func(); + + /* Keep BIOS read/write */ + modify_shadow(0xf0000, 0x10000, Read_Write); +#else // Locate chip controlling ram shadowing. int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { @@ -88,6 +138,7 @@ make_bios_writable() } // Ram already present - just enable writes __make_bios_writable(bdf); +#endif } // Make the BIOS code segment area (0xf0000) read-only. @@ -99,6 +150,9 @@ make_bios_readonly() dprintf(3, "locking shadow ram\n"); +#if VIRTUTECH_PC_SHADOW + modify_shadow(0xf0000, 0x10000, Read_Only); +#else int bdf = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441); if (bdf < 0) { dprintf(1, "Unable to lock ram - bridge not found\n"); @@ -122,4 +176,5 @@ make_bios_readonly() // Write protect 0xf0000-0x100000 pci_config_writeb(bdf, 0x59, 0x10); +#endif } -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0009-Properly-mask-value-for-MTRR-mask.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0009-Properly-mask-value-for-MTRR-mask.patch"

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[PATCH 07/10] Always enable the IRQ0 override if the VIRTUTECH_IRQ0_OVERRIDE option is set.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/config.h | 3 +++ src/paravirt.c | 4 ++++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/config.h b/src/config.h index 3033133..71903bb 100644 --- a/src/config.h +++ b/src/config.h @@ -189,4 +189,7 @@ #define DEBUG_HDL_pmm 1 #define DEBUG_thread 1 +/* Options for running on the Virtutech Simics x86-440bx machine model */ +#define VIRTUTECH_IRQ0_OVERRIDE 1 + #endif // config.h diff --git a/src/paravirt.c b/src/paravirt.c index 6f48d2e..577c7e8 100644 --- a/src/paravirt.c +++ b/src/paravirt.c @@ -82,6 +82,9 @@ int qemu_cfg_show_boot_menu(void) int qemu_cfg_irq0_override(void) { +#if VIRTUTECH_IRQ0_OVERRIDE + return 1; +#else u8 v; if (!qemu_cfg_present) @@ -90,6 +93,7 @@ int qemu_cfg_irq0_override(void) qemu_cfg_read_entry(&v, QEMU_CFG_IRQ0_OVERRIDE, sizeof(v)); return v; +#endif } u16 qemu_cfg_acpi_additional_tables(void) -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0008-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0008-Handle-Virtutech-Simics-x86-440bx-shadowing-with-the.pa"; filename*1="tch"

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[PATCH 06/10] Add MPS entries for LINT interrupts.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/mptable.c | 23 +++++++++++++++++++++-- src/mptable.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 7e8486d..b91591d 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -22,7 +22,7 @@ mptable_init(void) + sizeof(struct mpt_cpu) * MaxCountCPUs + sizeof(struct mpt_bus) + sizeof(struct mpt_ioapic) - + sizeof(struct mpt_intsrc) * 16); + + sizeof(struct mpt_intsrc) * 18); struct mptable_config_s *config = malloc_fseg(length); struct mptable_floating_s *floating = malloc_fseg(sizeof(*floating)); if (!config || !floating) { @@ -94,7 +94,7 @@ mptable_init(void) break; } - config->entrycount = actual_cpu_count + 2 + 16; + config->entrycount = actual_cpu_count + 2 + 16 + 2; /* isa bus */ struct mpt_bus *bus = (void*)&cpus[actual_cpu_count]; @@ -131,6 +131,25 @@ mptable_init(void) intsrc++; } + /* Local interrupt assignment */ + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 3; /* ExtINT */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 0; /* LINTIN0 */ + intsrc++; + + intsrc->type = MPT_TYPE_LOCAL_INT; + intsrc->irqtype = 1; /* NMI */ + intsrc->irqflag = 0; /* PO, EL default */ + intsrc->srcbus = 0; + intsrc->srcbusirq = 0; + intsrc->dstapic = 0; /* BSP == APIC #0 */ + intsrc->dstirq = 1; /* LINTIN1 */ + intsrc++; + // Set checksum. config->length = (void*)intsrc - (void*)config; config->checksum -= checksum(config, config->length); diff --git a/src/mptable.h b/src/mptable.h index 4c4d52f..c4e3c51 100644 --- a/src/mptable.h +++ b/src/mptable.h @@ -38,6 +38,7 @@ struct mptable_config_s { #define MPT_TYPE_BUS 1 #define MPT_TYPE_IOAPIC 2 #define MPT_TYPE_INTSRC 3 +#define MPT_TYPE_LOCAL_INT 4 struct mpt_cpu { u8 type; -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0007-Always-enable-the-IRQ0-override-if-the-VIRTUTECH_IRQ.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0007-Always-enable-the-IRQ0-override-if-the-VIRTUTECH_IRQ.pa"; filename*1="tch"

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[PATCH 4/9] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/smp.c b/src/smp.c index 71b0da8..b0852f8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -13,6 +13,8 @@ #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) #define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0) +#define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350) +#define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360) #define APIC_ENABLED 0x0100 @@ -91,6 +93,12 @@ smp_probe(void) u32 val = readl(APIC_SVR); writel(APIC_SVR, val | APIC_ENABLED); + /* Set LINT0 as Ext_INT, level triggered */ + writel(APIC_LINT0, 0x8700); + + /* Set LINT1 as NMI, level triggered */ + writel(APIC_LINT1, 0x8400); + // broadcast SIPI writel(APIC_ICR_LOW, 0x000C4500); u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12; -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0005-Add-MPS-entries-for-LINT-interrupts.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0005-Add-MPS-entries-for-LINT-interrupts.patch"

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[PATCH 4/8] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/smp.c b/src/smp.c index 71b0da8..b0852f8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -13,6 +13,8 @@ #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) #define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0) +#define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350) +#define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360) #define APIC_ENABLED 0x0100 @@ -91,6 +93,12 @@ smp_probe(void) u32 val = readl(APIC_SVR); writel(APIC_SVR, val | APIC_ENABLED); + /* Set LINT0 as Ext_INT, level triggered */ + writel(APIC_LINT0, 0x8700); + + /* Set LINT1 as NMI, level triggered */ + writel(APIC_LINT1, 0x8400); + // broadcast SIPI writel(APIC_ICR_LOW, 0x000C4500); u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12; -- 1.6.2.5 --------------010303080000070006010407 Content-Type: text/x-patch; name="0005-Add-MPS-entries-for-LINT-interrupts.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0005-Add-MPS-entries-for-LINT-interrupts.patch"

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[PATCH 05/10] Initialize the LINT LVTs on the local APIC of the BSP. Since the APIC is enabled, we need to initialize LINT0 to ExtINT and LINT1 to NMI.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/smp.c b/src/smp.c index 71b0da8..b0852f8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -13,6 +13,8 @@ #define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300) #define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0) +#define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350) +#define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360) #define APIC_ENABLED 0x0100 @@ -91,6 +93,12 @@ smp_probe(void) u32 val = readl(APIC_SVR); writel(APIC_SVR, val | APIC_ENABLED); + /* Set LINT0 as Ext_INT, level triggered */ + writel(APIC_LINT0, 0x8700); + + /* Set LINT1 as NMI, level triggered */ + writel(APIC_LINT1, 0x8400); + // broadcast SIPI writel(APIC_ICR_LOW, 0x000C4500); u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12; -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0006-Add-MPS-entries-for-LINT-interrupts.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0006-Add-MPS-entries-for-LINT-interrupts.patch"

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[PATCH 3/9] Remove device access from loop to make it faster when running in emulation.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/smp.c b/src/smp.c index a912857..71b0da8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -97,11 +97,13 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT) { msleep(10); - else - while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs)) - ; + } else { + u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); + while (cmos_smp_count + 1 != readl(&CountCPUs)) + ; + } // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0004-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0004-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.pa"; filename*1="tch"

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[PATCH 3/8] Remove device access from loop to make it faster when running in emulation.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/smp.c b/src/smp.c index a912857..71b0da8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -97,11 +97,13 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT) { msleep(10); - else - while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs)) - ; + } else { + u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); + while (cmos_smp_count + 1 != readl(&CountCPUs)) + ; + } // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; -- 1.6.2.5 --------------010303080000070006010407 Content-Type: text/x-patch; name="0004-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0004-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.pa"; filename*1="tch"

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[PATCH 04/10] Remove device access from loop to make it faster when running in emulation.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/smp.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/smp.c b/src/smp.c index a912857..71b0da8 100644 --- a/src/smp.c +++ b/src/smp.c @@ -97,11 +97,13 @@ smp_probe(void) writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector); // Wait for other CPUs to process the SIPI. - if (CONFIG_COREBOOT) + if (CONFIG_COREBOOT) { msleep(10); - else - while (inb_cmos(CMOS_BIOS_SMP_COUNT) + 1 != readl(&CountCPUs)) - ; + } else { + u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT); + while (cmos_smp_count + 1 != readl(&CountCPUs)) + ; + } // Restore memory. *(u64*)BUILD_AP_BOOT_ADDR = old; -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0005-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0005-Initialize-the-LINT-LVTs-on-the-local-APIC-of-the-BS.pa"; filename*1="tch"

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[PATCH 03/10] Limit MPS tables to 15 CPUs to fit with 4-bit APIC addressing.
by Magnus Christensson 03 Nov '09

03 Nov '09

--- src/mptable.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 525188d..7e8486d 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -86,6 +86,12 @@ mptable_init(void) cpu->cpusignature = 0x600; cpu->featureflag = 0x201; } + + /* Limit the CPU count to 15 in the MPS tables, which is the limit in + the 4-bit legacy APIC addressing scheme. Operating systems can find + all CPUs through the ACPI tables. */ + if (actual_cpu_count >= 15) + break; } config->entrycount = actual_cpu_count + 2 + 16; -- 1.6.2.5 --------------080100040501080908060605 Content-Type: text/x-patch; name="0004-Remove-device-access-from-loop-to-make-it-faster-whe.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0004-Remove-device-access-from-loop-to-make-it-faster-whe.pa"; filename*1="tch"

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coreboot November 2009