coreboot November 2009

coreboot@coreboot.org

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[v2] r4919 - trunk/src/northbridge/amd/amdk8
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: myles Date: 2009-11-05 21:02:35 +0000 (Thu, 05 Nov 2009) New Revision: 4919 Added: trunk/src/northbridge/amd/amdk8/util.c Modified: trunk/src/northbridge/amd/amdk8/Makefile.inc trunk/src/northbridge/amd/amdk8/amdk8.h Log: Add debugging utility file for dumping routing registers on K8. Ported from Ron's code in v3. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/src/northbridge/amd/amdk8/Makefile.inc =================================================================== --- trunk/src/northbridge/amd/amdk8/Makefile.inc 2009-11-05 20:06:19 UTC (rev 4918) +++ trunk/src/northbridge/amd/amdk8/Makefile.inc 2009-11-05 21:02:35 UTC (rev 4919) @@ -3,6 +3,10 @@ obj-y += get_sblk_pci1234.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += amdk8_acpi.o +# Enable this if you want to check the values of the PCI routing registers. +# Call show_all_routes() anywhere amdk8.h is included. +#obj-y += util.o + # Not sure what to do with these yet. How did raminit_test even work? # Should be a target in -y form. #if CONFIG_K8_REV_F_SUPPORT Modified: trunk/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h 2009-11-05 20:06:19 UTC (rev 4918) +++ trunk/src/northbridge/amd/amdk8/amdk8.h 2009-11-05 21:02:35 UTC (rev 4919) @@ -8,4 +8,6 @@ #include "amdk8_pre_f.h" #endif +void showallroutes(int level, device_t dev); + #endif /* AMDK8_H */ Added: trunk/src/northbridge/amd/amdk8/util.c =================================================================== --- trunk/src/northbridge/amd/amdk8/util.c (rev 0) +++ trunk/src/northbridge/amd/amdk8/util.c 2009-11-05 21:02:35 UTC (rev 4919) @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Vincent Legoll <vincent.legoll(a)gmail.com> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/* + * K8 northbridge utilities (dump routing registers). + * Designed to be called at any time. + * It can be called before RAM is set up by including this file. + * It can be called after RAM is set up by including amdk8.h and enabling the + * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. + */ +#ifndef __ROMCC__ +#include <console/console.h> +#include <string.h> +#include <device/pci.h> +#include <cpu/amd/amdk8_sysconf.h> +#include <device/pci_ops.h> +#include "amdk8.h" +#endif + +/* Function 1 */ +/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at + * 0x78, 0xb8, and 0xd8 + */ +#define DRAM_ROUTE_START 0x40 +#define DRAM_ROUTE_END 0x78 +#define MMIO_ROUTE_START 0x80 +#define MMIO_ROUTE_END 0xb8 +#define PCIIO_ROUTE_START 0xc0 +#define PCIIO_ROUTE_END 0xd8 +#define CONFIG_ROUTE_START 0xe0 +#define CONFIG_ROUTE_END 0xec + +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE_VGA_EN (1 << 4) +#define PCI_IO_BASE_NO_ISA (1 << 5) + +#define BITS(r, shift, mask) (((r>>shift)&mask)) + +/** + * Return "R" if the register has read-enable bit set. + */ +static const char *re(u32 i) +{ + return ((i & 1) ? "R" : ""); +} + +/** + * Return "W" if the register has write-enable bit set. + */ +static const char *we(u32 i) +{ + return ((i & 1) ? "W" : ""); +} + +/** + * Return a string containing the interleave settings. + */ +static const char *ileave(u32 base) +{ + switch ((base >> 8) & 7) { + case 0: + return "No interleave"; + case 1: + return "2 nodes"; + case 3: + return "4 nodes"; + case 7: + return "8 nodes"; + default: + return "Reserved"; + } +} + +/** + * Return the node number. + * For one case (config registers) these are not the right bit fields. + */ +static int node(u32 reg) +{ + return BITS(reg, 0, 0x7); +} + +/** + * Return the link number. + * For one case (config registers) these are not the right bit fields. + */ +static int link(u32 reg) +{ + return BITS(reg, 4, 0x3); +} + +/** + * Print the DRAM routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and interleave information. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showdram(int level, u8 which, u32 base, u32 lim) +{ + do_printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", + which, (((u64) base & 0xffff0000) << 8), + (((u64) lim & 0xffff0000) << 8) + 0xffffff, + node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); +} + +/** + * Print the config routing info for a config register. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and device number compare enable + * + * @param level Printing level + * @param which Register number + * @param reg Config register + */ +static void showconfig(int level, u8 which, u32 reg) +{ + /* Don't use node() and link() here. */ + do_printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), + BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); +} + +/** + * Print the PCIIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and VGA and ISA Enable. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showpciio(int level, u8 which, u32 base, u32 lim) +{ + do_printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", + which, BITS(base, 12, 0x3fff) << 12, + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, node(lim), link(lim), + re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); +} + +/** + * Print the MMIO routing info for one base/limit pair. + * + * Show base, limit, dest node, dest link on that node, read and write + * enable, and CPU Disable, Lock, and Non-posted. + * + * @param level Printing level + * @param which Register number + * @param base Base register + * @param lim Limit register + */ +static void showmmio(int level, u8 which, u32 base, u32 lim) +{ + do_printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " + "CPU disable %d, Lock %d, Non posted %d\n", + which, ((u64) BITS(base, 0, 0xffffff00)) << 8, + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, node(lim), + link(lim), re(base), we(base), BITS(base, 4, 0x1), + BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); +} + +/** + * Show all DRAM routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showalldram(int level, device_t dev) +{ + u8 reg; + for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim!=(reg-DRAM_ROUTE_START)/8) + showdram(level, reg, base, lim); + } +} + +/** + * Show all MMIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallmmio(int level, device_t dev) +{ + u8 reg; + for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showmmio(level, reg, base, lim); + } +} + +/** + * Show all PCIIO routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallpciio(int level, device_t dev) +{ + u8 reg; + for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev, reg + 4); + if (base || lim) + showpciio(level, reg, base, lim); + } +} + +/** + * Show all config routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +static void showallconfig(int level, device_t dev) +{ + u8 reg; + for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) { + u32 val = pci_read_config32(dev, reg); + if (val) + showconfig(level, reg, val); + } +} + +/** + * Show all routing registers. This function is callable at any time. + * + * @param level The debug level. + * @param dev A 32-bit number in the standard bus/dev/fn format which is used + * raw config space. + */ +void showallroutes(int level, device_t dev) +{ + showalldram(level, dev); + showallmmio(level, dev); + showallpciio(level, dev); + showallconfig(level, dev); +}

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Coreboot V2 or V3 for Geode LX800 ?
by Guy Ellis 05 Nov '09

05 Nov '09

Hi all, We want to use coreboot on a new product we have designed at work. The PCB is a variant of the AMD NAS reference design (LX800 and CS5536) Coreboot V3 seems to be a fork going nowhere? Where is the best place to start - Coreboot V2 or V3 for the LX800? Cheers, - Guy.

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[v2] r4918 - trunk/src/devices
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: myles Date: 2009-11-05 20:06:19 +0000 (Thu, 05 Nov 2009) New Revision: 4918 Modified: trunk/src/devices/pci_device.c Log: Don't try to set fixed resources. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/devices/pci_device.c =================================================================== --- trunk/src/devices/pci_device.c 2009-11-05 18:08:16 UTC (rev 4917) +++ trunk/src/devices/pci_device.c 2009-11-05 20:06:19 UTC (rev 4918) @@ -479,6 +479,11 @@ return; } + /* If this resource is fixed don't worry about it. */ + if (resource->flags & IORESOURCE_FIXED) { + return; + } + /* If I have already stored this resource don't worry about it. */ if (resource->flags & IORESOURCE_STORED) { return;

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[v2] r4917 - in trunk/src/mainboard: intel/d945gclf kontron/986lcd-m via/vt8454c
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 18:08:16 +0000 (Thu, 05 Nov 2009) New Revision: 4917 Modified: trunk/src/mainboard/intel/d945gclf/dmi.h trunk/src/mainboard/kontron/986lcd-m/dmi.h trunk/src/mainboard/via/vt8454c/dmi.h Log: fix length field in dmi tables. Newer DMI versions through errors Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/intel/d945gclf/dmi.h =================================================================== --- trunk/src/mainboard/intel/d945gclf/dmi.h 2009-11-05 18:06:43 UTC (rev 4916) +++ trunk/src/mainboard/intel/d945gclf/dmi.h 2009-11-05 18:08:16 UTC (rev 4917) @@ -1,11 +1,12 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. + * published by the Free Software Foundation; version 2 of + * the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,14 +15,15 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ #define DMI_TABLE_SIZE 0x55 static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, Modified: trunk/src/mainboard/kontron/986lcd-m/dmi.h =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/dmi.h 2009-11-05 18:06:43 UTC (rev 4916) +++ trunk/src/mainboard/kontron/986lcd-m/dmi.h 2009-11-05 18:08:16 UTC (rev 4917) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,8 +22,8 @@ #define DMI_TABLE_SIZE 0x55 static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32, Modified: trunk/src/mainboard/via/vt8454c/dmi.h =================================================================== --- trunk/src/mainboard/via/vt8454c/dmi.h 2009-11-05 18:06:43 UTC (rev 4916) +++ trunk/src/mainboard/via/vt8454c/dmi.h 2009-11-05 18:08:16 UTC (rev 4917) @@ -22,8 +22,8 @@ #define DMI_TABLE_SIZE 0x55 static u8 dmi_table[DMI_TABLE_SIZE] = { - 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, + 0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00, 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20, 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,

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[v2] r4916 - trunk/src/arch/i386/boot
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 18:06:43 +0000 (Thu, 05 Nov 2009) New Revision: 4916 Modified: trunk/src/arch/i386/boot/acpi.c Log: if x86emu was running for VGA init a corrupted low table RSDP is generated in the F segment. Clear the memory before generating an RSDP to fix the problem. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/boot/acpi.c =================================================================== --- trunk/src/arch/i386/boot/acpi.c 2009-11-05 17:24:03 UTC (rev 4915) +++ trunk/src/arch/i386/boot/acpi.c 2009-11-05 18:06:43 UTC (rev 4916) @@ -424,6 +424,7 @@ void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt) { + memset(rsdp, 0, sizeof(acpi_rsdp_t)); memcpy(rsdp->signature, RSDP_SIG, 8); memcpy(rsdp->oem_id, OEM_ID, 6); rsdp->length = sizeof(acpi_rsdp_t);

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[v2] r4915 - trunk/util/x86emu
by svn＠coreboot.org 05 Nov '09

05 Nov '09

Author: stepan Date: 2009-11-05 17:24:03 +0000 (Thu, 05 Nov 2009) New Revision: 4915 Removed: trunk/util/x86emu/pcbios/ Modified: trunk/util/x86emu/Config.lb trunk/util/x86emu/Makefile trunk/util/x86emu/Makefile.inc trunk/util/x86emu/biosemu.c Log: biosemu (non-yabel) cleanup * Drop pcbios folder that only exists for a single function * include int1a handler in biosemu.c * Wipe a lot of dead code, and set up F segment correctly * include return value check from yabel. On the long run we should teach yabel to be able to run with a reduced feature set, ie. no emulation of (almost) all system hardware. Then we could drop the non-yabel x86emu. But for now this patch cleans up the non-yabel biosemu.c to a state where it's not all that ugly anymore.. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/util/x86emu/Config.lb =================================================================== --- trunk/util/x86emu/Config.lb 2009-11-05 12:44:50 UTC (rev 4914) +++ trunk/util/x86emu/Config.lb 2009-11-05 17:24:03 UTC (rev 4915) @@ -11,7 +11,6 @@ object x86_asm.S else object biosemu.o - dir pcbios dir x86emu end end Modified: trunk/util/x86emu/Makefile =================================================================== --- trunk/util/x86emu/Makefile 2009-11-05 12:44:50 UTC (rev 4914) +++ trunk/util/x86emu/Makefile 2009-11-05 17:24:03 UTC (rev 4915) @@ -22,7 +22,7 @@ X86EMU_SRC = debug.c decode.c fpu.c ops.c ops2.c prim_ops.c sys.c ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) -BIOSEMU_SRC = biosemu.c pcbios/pcibios.c +BIOSEMU_SRC = biosemu.c endif ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL),y) Modified: trunk/util/x86emu/Makefile.inc =================================================================== --- trunk/util/x86emu/Makefile.inc 2009-11-05 12:44:50 UTC (rev 4914) +++ trunk/util/x86emu/Makefile.inc 2009-11-05 17:24:03 UTC (rev 4915) @@ -20,7 +20,6 @@ subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += x86emu obj-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += biosemu.o -subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += pcbios obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86.o obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86_asm.o Modified: trunk/util/x86emu/biosemu.c =================================================================== --- trunk/util/x86emu/biosemu.c 2009-11-05 12:44:50 UTC (rev 4914) +++ trunk/util/x86emu/biosemu.c 2009-11-05 17:24:03 UTC (rev 4915) @@ -36,6 +36,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <string.h> #ifdef CONFIG_COREBOOT_V2 #include <arch/io.h> #include <console/console.h> @@ -47,11 +48,40 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <x86emu/x86emu.h> +#include "x86emu/prim_ops.h" -#include "pcbios/pcibios.h" +#define DATA_SEGMENT 0x2000 +#define STACK_SEGMENT 0x1000 //1000:xxxx +#define STACK_START_OFFSET 0xfffe +#define INITIAL_EBDA_SEGMENT 0xF600 // segment of the Extended BIOS Data Area +#define INITIAL_EBDA_SIZE 0x400 // size of the EBDA (at least 1KB!! since size is stored in KB!) +enum { + PCI_BIOS_PRESENT = 0xB101, + FIND_PCI_DEVICE = 0xB102, + FIND_PCI_CLASS_CODE = 0xB103, + GENERATE_SPECIAL_CYCLE = 0xB106, + READ_CONFIG_BYTE = 0xB108, + READ_CONFIG_WORD = 0xB109, + READ_CONFIG_DWORD = 0xB10A, + WRITE_CONFIG_BYTE = 0xB10B, + WRITE_CONFIG_WORD = 0xB10C, + WRITE_CONFIG_DWORD = 0xB10D, + GET_IRQ_ROUTING_OPTIONS = 0xB10E, + SET_PCI_IRQ = 0xB10F +}; + +enum { + SUCCESSFUL = 0x00, + FUNC_NOT_SUPPORTED = 0x81, + BAD_VENDOR_ID = 0x83, + DEVICE_NOT_FOUND = 0x86, + BAD_REGISTER_NUMBER = 0x87, + SET_FAILED = 0x88, + BUFFER_TOO_SMALL = 0x89 +}; + #define MEM_WB(where, what) wrb(where, what) #define MEM_WW(where, what) wrw(where, what) #define MEM_WL(where, what) wrl(where, what) @@ -60,45 +90,8 @@ #define MEM_RW(where) rdw(where) #define MEM_RL(where) rdl(where) -u8 x_inb(u16 port); -u16 x_inw(u16 port); -void x_outb(u16 port, u8 val); -void x_outw(u16 port, u16 val); -u32 x_inl(u16 port); -void x_outl(u16 port, u32 val); - -// -void X86EMU_setMemBase(void *base, size_t size); - -/* general software interrupt handler */ -u32 getIntVect(int num) +static u8 biosemu_inb(u16 port) { - return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4); -} - -/* FIXME: There is already a push_word() in the emulator */ -void pushw(u16 val) -{ - X86_ESP -= 2; - MEM_WW(((u32) X86_SS << 4) + X86_SP, val); -} - -int run_bios_int(int num) -{ - u32 eflags; - - eflags = X86_EFLAGS; - pushw(eflags); - pushw(X86_CS); - pushw(X86_IP); - X86_CS = MEM_RW((num << 2) + 2); - X86_IP = MEM_RW(num << 2); - - return 1; -} - -u8 x_inb(u16 port) -{ u8 val; val = inb(port); @@ -110,7 +103,7 @@ return val; } -u16 x_inw(u16 port) +static u16 biosemu_inw(u16 port) { u16 val; @@ -122,7 +115,7 @@ return val; } -u32 x_inl(u16 port) +static u32 biosemu_inl(u16 port) { u32 val; @@ -134,7 +127,7 @@ return val; } -void x_outb(u16 port, u8 val) +static void biosemu_outb(u16 port, u8 val) { #ifdef CONFIG_DEBUG if (port != 0x43) @@ -143,7 +136,7 @@ outb(val, port); } -void x_outw(u16 port, u16 val) +static void biosemu_outw(u16 port, u16 val) { #ifdef CONFIG_DEBUG printk("outw(0x%04x, 0x%04x)\n", val, port); @@ -151,7 +144,7 @@ outw(val, port); } -void x_outl(u16 port, u32 val) +static void biosemu_outl(u16 port, u32 val) { #ifdef CONFIG_DEBUG printk("outl(0x%08x, 0x%04x)\n", val, port); @@ -159,23 +152,245 @@ outl(val, port); } -X86EMU_pioFuncs myfuncs = { - x_inb, x_inw, x_inl, - x_outb, x_outw, x_outl +static X86EMU_pioFuncs biosemu_piofuncs = { + biosemu_inb, biosemu_inw, biosemu_inl, + biosemu_outb, biosemu_outw, biosemu_outl }; +/* Interrupt Handlers */ +static int int15_handler(void) +{ + /* This int15 handler is VIA Tech. and Intel specific. Other chipsets need other + * handlers. The right way to do this is to move this handler code into + * the mainboard or northbridge code. + */ + switch (X86_AX) { + case 0x5f19: + X86_EFLAGS |= FB_CF; /* set carry flag */ + break; + case 0x5f18: + X86_EAX = 0x5f; + // MCLK = 133, 32M frame buffer, 256 M main memory + X86_EBX = 0x545; + X86_ECX = 0x060; + X86_EFLAGS &= ~FB_CF; + break; + case 0x5f00: + X86_EAX = 0x8600; + X86_EFLAGS |= FB_CF; /* set carry flag */ + break; + case 0x5f01: + X86_EAX = 0x5f; + X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + X86_EFLAGS &= ~FB_CF; + break; + case 0x5f02: + X86_EAX = 0x5f; + X86_EBX = (X86_EBX & 0xffff0000) | 2; + X86_ECX = (X86_ECX & 0xffff0000) | 0x401; // PAL + crt only + X86_EDX = (X86_EDX & 0xffff0000) | 0; // TV Layout - default + X86_EFLAGS &= ~FB_CF; + break; + case 0x5f0f: + X86_EAX = 0x860f; + X86_EFLAGS |= FB_CF; /* set carry flag */ + break; + /* And now Intel IGD code */ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + case 0x5f35: + X86_EAX = 0x5f; + X86_ECX = BOOT_DISPLAY_DEFAULT; + X86_EFLAGS &= ~FB_CF; + break; + case 0x5f40: + X86_EAX = 0x5f; + X86_ECX = 3; // This is mainboard specific + printk("DISPLAY=%x\n", X86_ECX); + X86_EFLAGS &= ~FB_CF; + break; + default: + printk("Unknown INT15 function %04x!\n", X86_AX); + X86_EFLAGS |= FB_CF; /* set carry flag */ + } + + return 1; +} + +static int int1a_handler(void) +{ + int ret = 0; + struct device *dev = 0; + + switch (X86_AX) { + case PCI_BIOS_PRESENT: + X86_AH = 0x00; /* no config space/special cycle support */ + X86_AL = 0x01; /* config mechanism 1 */ + X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24; + X86_EBX = 0x0210; /* Version 2.10 */ + X86_ECX = 0xFF00; /* FIXME: Max bus number */ + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + case FIND_PCI_DEVICE: + /* FIXME: support SI != 0 */ +#ifdef CONFIG_COREBOOT_V2 + dev = dev_find_device(X86_DX, X86_CX, dev); +#else + dev = dev_find_pci_device(X86_DX, X86_CX, dev); +#endif + if (dev != 0) { + X86_BH = dev->bus->secondary; + X86_BL = dev->path.pci.devfn; + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case FIND_PCI_CLASS_CODE: + /* FixME: support SI != 0 */ + dev = dev_find_class(X86_ECX, dev); + if (dev != 0) { + X86_BH = dev->bus->secondary; + X86_BL = dev->path.pci.devfn; + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_BYTE: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_CL = pci_read_config8(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_WORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_CX = pci_read_config16(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_DWORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_ECX = pci_read_config32(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_BYTE: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config8(dev, X86_DI, X86_CL); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_WORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config16(dev, X86_DI, X86_CX); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_DWORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config16(dev, X86_DI, X86_ECX); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + default: + X86_AH = FUNC_NOT_SUPPORTED; + X86_EFLAGS |= FB_CF; + break; + } + + return ret; +} + /* Interrupt multiplexer */ -void do_int(int num) +/* Find base address of interrupt handler */ +static u32 getIntVect(int num) { + return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4); +} + +static int run_bios_int(int num) +{ + u32 eflags; + + eflags = X86_EFLAGS; + push_word(eflags); + push_word(X86_CS); + push_word(X86_IP); + X86_CS = MEM_RW((num << 2) + 2); + X86_IP = MEM_RW(num << 2); + + return 1; +} + +static void do_int(int num) +{ int ret = 0; - printk("int%x vector at %x\n", num, getIntVect(num)); + printk("int%x (AX=%04x) vector at %x\n", num, X86_AX, getIntVect(num)); switch (num) { -#ifndef _PC case 0x10: case 0x42: case 0x6D: @@ -188,9 +403,8 @@ ret = 1; } break; -#endif case 0x15: - //ret = int15_handler(); + ret = int15_handler(); ret = 1; break; case 0x16: @@ -198,7 +412,7 @@ ret = 0; break; case 0x1A: - ret = pcibios_handler(); + ret = int1a_handler(); ret = 1; break; case 0xe6: @@ -214,159 +428,124 @@ } -#if 0 -#define SYS_BIOS 0xf0000 /* * here we are really paranoid about faking a "real" * BIOS. Most of this information was pulled from * dosemu. */ -#if 0 -void setup_int_vect(void) +static void setup_system_bios(void) { int i; - /* let the int vects point to the SYS_BIOS seg */ - for (i = 0; i < 0x80; i++) { - MEM_WW(i << 2, 0); - MEM_WW((i << 2) + 2, SYS_BIOS >> 4); - } + /* Set up Interrupt Vectors. The IVT starts at 0x0000:0x0000 + * Additionally, we put some stub code into the F segment for + * those pesky little buggers that jmp to the hard coded addresses + * instead of calling int XX. This stub code looks like this + * + * CD XX int 0xXX + * C3 ret + * F4 hlt + */ - reset_int_vect(); - - /* font tables default location (int 1F) */ - MEM_WW(0x1f << 2, 0xfa6e); + /* int 05 default location (Bound Exceeded) */ + MEM_WL(0x05 << 2, 0xf000ff54); + MEM_WL(0xfff54, 0xf4c305cd); + /* int 08 default location (Double Fault) */ + MEM_WL(0x08 << 2, 0xf000fea5); + MEM_WL(0xffea5, 0xf4c308cd); + /* int 0E default location (Page Fault) */ + MEM_WL(0x0e << 2, 0xf000ef57); + MEM_WL(0xfef57, 0xf4c30ecd); + /* int 10 default location */ + MEM_WL(0x10 << 2, 0xf000f065); + MEM_WL(0xff065, 0xf4c310cd); /* int 11 default location (Get Equipment Configuration) */ - MEM_WW(0x11 << 2, 0xf84d); + MEM_WL(0x11 << 2, 0xf000f84d); + MEM_WL(0xff84d, 0xf4c311cd); /* int 12 default location (Get Conventional Memory Size) */ - MEM_WW(0x12 << 2, 0xf841); + MEM_WL(0x12 << 2, 0xf000f841); + MEM_WL(0xff841, 0xf4c312cd); + /* int 13 default location (Disk) */ + MEM_WL(0x13 << 2, 0xf000ec59); + MEM_WL(0xfec59, 0xf4c313cd); + /* int 14 default location (Disk) */ + MEM_WL(0x14 << 2, 0xf000e739); + MEM_WL(0xfe739, 0xf4c314cd); /* int 15 default location (I/O System Extensions) */ - MEM_WW(0x15 << 2, 0xf859); + MEM_WL(0x15 << 2, 0xf000f859); + MEM_WL(0xf859, 0xf4c315cd); + /* int 16 default location */ + MEM_WL(0x16 << 2, 0xf000e82e); + MEM_WL(0xfe82e, 0xf4c316cd); + /* int 17 default location (Parallel Port) */ + MEM_WL(0x17 << 2, 0xf000efd2); + MEM_WL(0xfefd2, 0xf4c317cd); /* int 1A default location (RTC, PCI and others) */ - MEM_WW(0x1a << 2, 0xff6e); - /* int 05 default location (Bound Exceeded) */ - MEM_WW(0x05 << 2, 0xff54); - /* int 08 default location (Double Fault) */ - MEM_WW(0x08 << 2, 0xfea5); - /* int 13 default location (Disk) */ - MEM_WW(0x13 << 2, 0xec59); - /* int 0E default location (Page Fault) */ - MEM_WW(0x0e << 2, 0xef57); - /* int 17 default location (Parallel Port) */ - MEM_WW(0x17 << 2, 0xefd2); - /* fdd table default location (int 1e) */ - MEM_WW(0x1e << 2, 0xefc7); + MEM_WL(0x1a << 2, 0xf000fe6e); + MEM_WL(0xffe6e, 0xf4c31acd); + /* int 1E default location (FDD table) */ + MEM_WL(0x1e << 2, 0xf000efc7); + MEM_WL(0xfefc7, 0xf4c31ecd); + /* font tables default location (int 1F) */ + MEM_WL(0x1f << 2, 0xf000fa6e); + MEM_WL(0xffa6e, 0xf4c31fcd); + /* int 42 default location */ + MEM_WL(0x42 << 2, 0xf000f065); + /* int 6D default location */ + MEM_WL(0x6D << 2, 0xf000f065); - /* Set Equipment flag to VGA */ - i = MEM_RB(0x0410) & 0xCF; - MEM_WB(0x0410, i); - /* XXX Perhaps setup more of the BDA here. See also int42(0x00). */ -} + /* Clear EBDA */ + for (i=(INITIAL_EBDA_SEGMENT << 4); + i<(INITIAL_EBDA_SEGMENT << 4) + INITIAL_EBDA_SIZE; i++) + MEM_WB(i, 0); + /* at offset 0h in EBDA is the size of the EBDA in KB */ + MEM_WW((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); -int setup_system_bios(void *base_addr) -{ - char *base = (char *) base_addr; + /* Clear BDA */ + for (i=0x400; i<0x500; i+=4) + MEM_WL(i, 0); - /* - * we trap the "industry standard entry points" to the BIOS - * and all other locations by filling them with "hlt" - * TODO: implement hlt-handler for these - */ - memset(base, 0xf4, 0x10000); + /* Set up EBDA */ + MEM_WW(0x40e, INITIAL_EBDA_SEGMENT); - /* set bios date */ - //strcpy(base + 0x0FFF5, "06/11/99"); - /* set up eisa ident string */ - //strcpy(base + 0x0FFD9, "PCI_ISA"); - /* write system model id for IBM-AT */ - //*((unsigned char *) (base + 0x0FFFE)) = 0xfc; + /* Set RAM size to 16MB (fake) */ + MEM_WW(0x413, 16384); - return 1; -} -#endif + // TODO Set up more of BDA here -void reset_int_vect(void) -{ - /* - * This table is normally located at 0xF000:0xF0A4. However, int 0x42, - * function 0 (Mode Set) expects it (or a copy) somewhere in the bottom - * 64kB. Note that because this data doesn't survive POST, int 0x42 should - * only be used during EGA/VGA BIOS initialisation. - */ - static const u8 VideoParms[] = { - /* Timing for modes 0x00 & 0x01 */ - 0x38, 0x28, 0x2d, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x02 & 0x03 */ - 0x71, 0x50, 0x5a, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x04, 0x05 & 0x06 */ - 0x38, 0x28, 0x2d, 0x0a, 0x7f, 0x06, 0x64, 0x70, - 0x02, 0x01, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for mode 0x07 */ - 0x61, 0x50, 0x52, 0x0f, 0x19, 0x06, 0x19, 0x19, - 0x02, 0x0d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, - /* Display page lengths in little endian order */ - 0x00, 0x08, /* Modes 0x00 and 0x01 */ - 0x00, 0x10, /* Modes 0x02 and 0x03 */ - 0x00, 0x40, /* Modes 0x04 and 0x05 */ - 0x00, 0x40, /* Modes 0x06 and 0x07 */ - /* Number of columns for each mode */ - 40, 40, 80, 80, 40, 40, 80, 80, - /* CGA Mode register value for each mode */ - 0x2c, 0x28, 0x2d, 0x29, 0x2a, 0x2e, 0x1e, 0x29, - /* Padding */ - 0x00, 0x00, 0x00, 0x00 - }; - int i; + /* setup original ROM BIOS Area (F000:xxxx) */ + const char *date = "06/23/99"; + for (i = 0; date[i]; i++) + MEM_WB(0xffff5 + i, date[i]); + /* set up eisa ident string */ + const char *ident = "PCI_ISA"; + for (i = 0; ident[i]; i++) + MEM_WB(0xfffd9 + i, ident[i]); - for (i = 0; i < sizeof(VideoParms); i++) - MEM_WB(i + (0x1000 - sizeof(VideoParms)), VideoParms[i]); - MEM_WW(0x1d << 2, 0x1000 - sizeof(VideoParms)); - MEM_WW((0x1d << 2) + 2, 0); - - printk(BIOS_DEBUG,"SETUP INT\n"); - MEM_WW(0x10 << 2, 0xf065); - MEM_WW((0x10 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x42 << 2, 0xf065); - MEM_WW((0x42 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x6D << 2, 0xf065); - MEM_WW((0x6D << 2) + 2, SYS_BIOS >> 4); + // write system model id for IBM-AT + // according to "Ralf Browns Interrupt List" Int15 AH=C0 Table 515, + // model FC is the original AT and also used in all DOSEMU Versions. + MEM_WB(0xFFFFE, 0xfc); } -#endif +#define BIOSEMU_MEM_BASE 0x00000000 +#define BIOSEMU_MEM_SIZE 0x00100000 void run_bios(struct device * dev, unsigned long addr) { -#if 1 int i; - unsigned short initialcs = (addr & 0xF0000) >> 4; - unsigned short initialip = (addr + 3) & 0xFFFF; - unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; - + u16 initialcs = (addr & 0xF0000) >> 4; + u16 initialip = (addr + 3) & 0xFFFF; + u16 devfn = (dev->bus->secondary << 8) | dev->path.pci.devfn; X86EMU_intrFuncs intFuncs[256]; - X86EMU_setMemBase(0, 0x100000); - X86EMU_setupPioFuncs(&myfuncs); + X86EMU_setMemBase(BIOSEMU_MEM_BASE, BIOSEMU_MEM_SIZE); + X86EMU_setupPioFuncs(&biosemu_piofuncs); for (i = 0; i < 256; i++) intFuncs[i] = do_int; X86EMU_setupIntrFuncs(intFuncs); - { - char *date = "01/01/99"; - for (i = 0; date[i]; i++) - wrb(0xffff5 + i, date[i]); - wrb(0xffff7, '/'); - wrb(0xffffa, '/'); - } + setup_system_bios(); - { - /* FixME: move PIT init to its own file */ - outb(0x36, 0x43); - outb(0x00, 0x40); - outb(0x00, 0x40); - } - //setup_int_vect(); - /* cpu setup */ X86_AX = devfn ? devfn : 0xff; X86_DX = 0x80; @@ -374,26 +553,37 @@ X86_CS = initialcs; /* Initialize stack and data segment */ - X86_SS = initialcs; - X86_SP = 0xfffe; - X86_DS = 0x0040; - X86_ES = 0x0000; + X86_SS = STACK_SEGMENT; + X86_SP = STACK_START_OFFSET;; + X86_DS = DATA_SEGMENT; /* We need a sane way to return from bios * execution. A hlt instruction and a pointer * to it, both kept on the stack, will do. */ - pushw(0xf4f4); /* hlt; hlt */ - pushw(X86_SS); - pushw(X86_SP + 2); + push_word(0xf4f4); /* hlt; hlt */ + push_word(X86_SS); + push_word(X86_SP + 2); #ifdef CONFIG_DEBUG //X86EMU_trace_on(); #endif - printk("entering emulator\n"); + printk("Executing Initialization Vector...\n"); X86EMU_exec(); - printk("exited emulator\n"); + printk("Option ROM Exit Status: %04x\n", X86_AX); -#endif + /* Check whether the stack is "clean" i.e. containing the HLT + * instruction we pushed before executing and pointing to the original + * stack address... indicating that the initialization probably was + * successful + */ + if ((pop_word() == 0xf4f4) && (X86_SS == STACK_SEGMENT) + && (X86_SP == STACK_START_OFFSET)) { + printk("Stack is clean, initialization successfull!\n"); + } else { + printk("Stack unclean, initialization probably NOT COMPLETE!!\n"); + printk("SS:SP = %04x:%04x, expected: %04x:%04x\n", + X86_SS, X86_SP, STACK_SEGMENT, STACK_START_OFFSET); + } }

1 0

[PATCH] cleanup x86emu without yabel
by Stefan Reinauer 05 Nov '09

05 Nov '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 biosemu (non-yabel) cleanup * Drop pcbios folder that only exists for a single function * include int1a handler in biosemu.c * Wipe a lot of dead code, and set up F segment correctly * include return value check from yabel. On the long run we should teach yabel to be able to run with a reduced feature set, ie. no emulation of (almost) all system hardware. Then we could drop the non-yabel x86emu. But for now this patch cleans up the non-yabel biosemu.c to a state where it's not all that ugly anymore.. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: util/x86emu/pcbios/Config.lb =================================================================== --- util/x86emu/pcbios/Config.lb (revision 4909) +++ util/x86emu/pcbios/Config.lb (working copy) @@ -1 +0,0 @@ -object pcibios.o \ No newline at end of file Index: util/x86emu/pcbios/Makefile.inc =================================================================== --- util/x86emu/pcbios/Makefile.inc (revision 4909) +++ util/x86emu/pcbios/Makefile.inc (working copy) @@ -1 +0,0 @@ -obj-y += pcibios.o Index: util/x86emu/pcbios/pcibios.c =================================================================== --- util/x86emu/pcbios/pcibios.c (revision 4909) +++ util/x86emu/pcbios/pcibios.c (working copy) @@ -1,185 +0,0 @@ -/* - * This software and ancillary information (herein called SOFTWARE ) - * called LinuxBIOS is made available under the terms described - * here. The SOFTWARE has been approved for release with associated - * LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has - * been authored by an employee or employees of the University of - * California, operator of the Los Alamos National Laboratory under - * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The - * U.S. Government has rights to use, reproduce, and distribute this - * SOFTWARE. The public may copy, distribute, prepare derivative works - * and publicly display this SOFTWARE without charge, provided that this - * Notice and any statement of authorship are reproduced on all copies. - * Neither the Government nor the University makes any warranty, express - * or implied, or assumes any liability or responsibility for the use of - * this SOFTWARE. If SOFTWARE is modified to produce derivative works, - * such modified SOFTWARE should be clearly marked, so as not to confuse - * it with the version available from LANL. - */ - /* - * This file is part of the coreboot project. - * - * (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#ifdef CONFIG_COREBOOT_V2 -#include <console/console.h> -#else -#include <console.h> -#endif -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <x86emu/x86emu.h> - -#include "pcibios.h" - -int pcibios_handler(void) -{ - int ret = 0; - struct device *dev = 0; - - switch (X86_AX) { - case PCI_BIOS_PRESENT: - X86_AH = 0x00; /* no config space/special cycle support */ - X86_AL = 0x01; /* config mechanism 1 */ - X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24; - X86_EBX = 0x0210; /* Version 2.10 */ - X86_ECX = 0xFF00; /* FixME: Max bus number */ - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - break; - case FIND_PCI_DEVICE: - /* FixME: support SI != 0 */ -#ifdef CONFIG_COREBOOT_V2 - dev = dev_find_device(X86_DX, X86_CX, dev); -#else - dev = dev_find_pci_device(X86_DX, X86_CX, dev); -#endif - if (dev != 0) { - X86_BH = dev->bus->secondary; - X86_BL = dev->path.pci.devfn; - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case FIND_PCI_CLASS_CODE: - /* FixME: support SI != 0 */ - dev = dev_find_class(X86_ECX, dev); - if (dev != 0) { - X86_BH = dev->bus->secondary; - X86_BL = dev->path.pci.devfn; - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case READ_CONFIG_BYTE: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - X86_CL = pci_read_config8(dev, X86_DI); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case READ_CONFIG_WORD: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - X86_CX = pci_read_config16(dev, X86_DI); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case READ_CONFIG_DWORD: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - X86_ECX = pci_read_config32(dev, X86_DI); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case WRITE_CONFIG_BYTE: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - pci_write_config8(dev, X86_DI, X86_CL); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case WRITE_CONFIG_WORD: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - pci_write_config16(dev, X86_DI, X86_CX); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - case WRITE_CONFIG_DWORD: - dev = dev_find_slot(X86_BH, X86_BL); - if (dev != 0) { - pci_write_config16(dev, X86_DI, X86_ECX); - X86_AH = SUCCESSFUL; - X86_EFLAGS &= ~FB_CF; /* clear carry flag */ - ret = 1; - } else { - X86_AH = DEVICE_NOT_FOUND; - X86_EFLAGS |= FB_CF; /* set carry flag */ - ret = 0; - } - break; - default: - X86_AH = FUNC_NOT_SUPPORTED; - X86_EFLAGS |= FB_CF; - break; - } - - return ret; -} Index: util/x86emu/pcbios/pcibios.h =================================================================== --- util/x86emu/pcbios/pcibios.h (revision 4909) +++ util/x86emu/pcbios/pcibios.h (working copy) @@ -1,70 +0,0 @@ -/* - * This software and ancillary information (herein called SOFTWARE ) - * called LinuxBIOS is made available under the terms described - * here. The SOFTWARE has been approved for release with associated - * LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has - * been authored by an employee or employees of the University of - * California, operator of the Los Alamos National Laboratory under - * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The - * U.S. Government has rights to use, reproduce, and distribute this - * SOFTWARE. The public may copy, distribute, prepare derivative works - * and publicly display this SOFTWARE without charge, provided that this - * Notice and any statement of authorship are reproduced on all copies. - * Neither the Government nor the University makes any warranty, express - * or implied, or assumes any liability or responsibility for the use of - * this SOFTWARE. If SOFTWARE is modified to produce derivative works, - * such modified SOFTWARE should be clearly marked, so as not to confuse - * it with the version available from LANL. - */ - /* - * This file is part of the coreboot project. - * - * (c) Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef PCI_BIOS_H -#define PCI_BIOS_H - -enum { - PCI_BIOS_PRESENT = 0xB101, - FIND_PCI_DEVICE = 0xB102, - FIND_PCI_CLASS_CODE = 0xB103, - GENERATE_SPECIAL_CYCLE = 0xB106, - READ_CONFIG_BYTE = 0xB108, - READ_CONFIG_WORD = 0xB109, - READ_CONFIG_DWORD = 0xB10A, - WRITE_CONFIG_BYTE = 0xB10B, - WRITE_CONFIG_WORD = 0xB10C, - WRITE_CONFIG_DWORD = 0xB10D, - GET_IRQ_ROUTING_OPTIONS = 0xB10E, - SET_PCI_IRQ = 0xB10F -}; - -enum { - SUCCESSFUL = 0x00, - FUNC_NOT_SUPPORTED = 0x81, - BAD_VENDOR_ID = 0x83, - DEVICE_NOT_FOUND = 0x86, - BAD_REGISTER_NUMBER = 0x87, - SET_FAILED = 0x88, - BUFFER_TOO_SMALL = 0x89 -}; - -int pcibios_handler(void); - -#endif /* PCI_BIOS_H */ - Index: util/x86emu/Config.lb =================================================================== --- util/x86emu/Config.lb (revision 4909) +++ util/x86emu/Config.lb (working copy) @@ -11,7 +11,6 @@ object x86_asm.S else object biosemu.o - dir pcbios dir x86emu end end Index: util/x86emu/biosemu.c =================================================================== --- util/x86emu/biosemu.c (revision 4909) +++ util/x86emu/biosemu.c (working copy) @@ -36,6 +36,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <string.h> #ifdef CONFIG_COREBOOT_V2 #include <arch/io.h> #include <console/console.h> @@ -47,11 +48,40 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <x86emu/x86emu.h> +#include "x86emu/prim_ops.h" -#include "pcbios/pcibios.h" +#define DATA_SEGMENT 0x2000 +#define STACK_SEGMENT 0x1000 //1000:xxxx +#define STACK_START_OFFSET 0xfffe +#define INITIAL_EBDA_SEGMENT 0xF600 // segment of the Extended BIOS Data Area +#define INITIAL_EBDA_SIZE 0x400 // size of the EBDA (at least 1KB!! since size is stored in KB!) +enum { + PCI_BIOS_PRESENT = 0xB101, + FIND_PCI_DEVICE = 0xB102, + FIND_PCI_CLASS_CODE = 0xB103, + GENERATE_SPECIAL_CYCLE = 0xB106, + READ_CONFIG_BYTE = 0xB108, + READ_CONFIG_WORD = 0xB109, + READ_CONFIG_DWORD = 0xB10A, + WRITE_CONFIG_BYTE = 0xB10B, + WRITE_CONFIG_WORD = 0xB10C, + WRITE_CONFIG_DWORD = 0xB10D, + GET_IRQ_ROUTING_OPTIONS = 0xB10E, + SET_PCI_IRQ = 0xB10F +}; + +enum { + SUCCESSFUL = 0x00, + FUNC_NOT_SUPPORTED = 0x81, + BAD_VENDOR_ID = 0x83, + DEVICE_NOT_FOUND = 0x86, + BAD_REGISTER_NUMBER = 0x87, + SET_FAILED = 0x88, + BUFFER_TOO_SMALL = 0x89 +}; + #define MEM_WB(where, what) wrb(where, what) #define MEM_WW(where, what) wrw(where, what) #define MEM_WL(where, what) wrl(where, what) @@ -60,45 +90,8 @@ #define MEM_RW(where) rdw(where) #define MEM_RL(where) rdl(where) -u8 x_inb(u16 port); -u16 x_inw(u16 port); -void x_outb(u16 port, u8 val); -void x_outw(u16 port, u16 val); -u32 x_inl(u16 port); -void x_outl(u16 port, u32 val); - -// -void X86EMU_setMemBase(void *base, size_t size); - -/* general software interrupt handler */ -u32 getIntVect(int num) +static u8 biosemu_inb(u16 port) { - return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4); -} - -/* FIXME: There is already a push_word() in the emulator */ -void pushw(u16 val) -{ - X86_ESP -= 2; - MEM_WW(((u32) X86_SS << 4) + X86_SP, val); -} - -int run_bios_int(int num) -{ - u32 eflags; - - eflags = X86_EFLAGS; - pushw(eflags); - pushw(X86_CS); - pushw(X86_IP); - X86_CS = MEM_RW((num << 2) + 2); - X86_IP = MEM_RW(num << 2); - - return 1; -} - -u8 x_inb(u16 port) -{ u8 val; val = inb(port); @@ -110,7 +103,7 @@ return val; } -u16 x_inw(u16 port) +static u16 biosemu_inw(u16 port) { u16 val; @@ -122,7 +115,7 @@ return val; } -u32 x_inl(u16 port) +static u32 biosemu_inl(u16 port) { u32 val; @@ -134,7 +127,7 @@ return val; } -void x_outb(u16 port, u8 val) +static void biosemu_outb(u16 port, u8 val) { #ifdef CONFIG_DEBUG if (port != 0x43) @@ -143,7 +136,7 @@ outb(val, port); } -void x_outw(u16 port, u16 val) +static void biosemu_outw(u16 port, u16 val) { #ifdef CONFIG_DEBUG printk("outw(0x%04x, 0x%04x)\n", val, port); @@ -151,7 +144,7 @@ outw(val, port); } -void x_outl(u16 port, u32 val) +static void biosemu_outl(u16 port, u32 val) { #ifdef CONFIG_DEBUG printk("outl(0x%08x, 0x%04x)\n", val, port); @@ -159,23 +152,178 @@ outl(val, port); } -X86EMU_pioFuncs myfuncs = { - x_inb, x_inw, x_inl, - x_outb, x_outw, x_outl +static X86EMU_pioFuncs biosemu_piofuncs = { + biosemu_inb, biosemu_inw, biosemu_inl, + biosemu_outb, biosemu_outw, biosemu_outl }; +/* Interrupt Handlers */ +static int int1a_handler(void) +{ + int ret = 0; + struct device *dev = 0; + switch (X86_AX) { + case PCI_BIOS_PRESENT: + X86_AH = 0x00; /* no config space/special cycle support */ + X86_AL = 0x01; /* config mechanism 1 */ + X86_EDX = 'P' | 'C' << 8 | 'I' << 16 | ' ' << 24; + X86_EBX = 0x0210; /* Version 2.10 */ + X86_ECX = 0xFF00; /* FIXME: Max bus number */ + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + break; + case FIND_PCI_DEVICE: + /* FIXME: support SI != 0 */ +#ifdef CONFIG_COREBOOT_V2 + dev = dev_find_device(X86_DX, X86_CX, dev); +#else + dev = dev_find_pci_device(X86_DX, X86_CX, dev); +#endif + if (dev != 0) { + X86_BH = dev->bus->secondary; + X86_BL = dev->path.pci.devfn; + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case FIND_PCI_CLASS_CODE: + /* FixME: support SI != 0 */ + dev = dev_find_class(X86_ECX, dev); + if (dev != 0) { + X86_BH = dev->bus->secondary; + X86_BL = dev->path.pci.devfn; + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_BYTE: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_CL = pci_read_config8(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_WORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_CX = pci_read_config16(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case READ_CONFIG_DWORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + X86_ECX = pci_read_config32(dev, X86_DI); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_BYTE: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config8(dev, X86_DI, X86_CL); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_WORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config16(dev, X86_DI, X86_CX); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + case WRITE_CONFIG_DWORD: + dev = dev_find_slot(X86_BH, X86_BL); + if (dev != 0) { + pci_write_config16(dev, X86_DI, X86_ECX); + X86_AH = SUCCESSFUL; + X86_EFLAGS &= ~FB_CF; /* clear carry flag */ + ret = 1; + } else { + X86_AH = DEVICE_NOT_FOUND; + X86_EFLAGS |= FB_CF; /* set carry flag */ + ret = 0; + } + break; + default: + X86_AH = FUNC_NOT_SUPPORTED; + X86_EFLAGS |= FB_CF; + break; + } + + return ret; +} + /* Interrupt multiplexer */ -void do_int(int num) +/* Find base address of interrupt handler */ +static u32 getIntVect(int num) { + return MEM_RW(num << 2) + (MEM_RW((num << 2) + 2) << 4); +} + +static int run_bios_int(int num) +{ + u32 eflags; + + eflags = X86_EFLAGS; + push_word(eflags); + push_word(X86_CS); + push_word(X86_IP); + X86_CS = MEM_RW((num << 2) + 2); + X86_IP = MEM_RW(num << 2); + + return 1; +} + +static void do_int(int num) +{ int ret = 0; - printk("int%x vector at %x\n", num, getIntVect(num)); + printk("int%x (AX=%04x) vector at %x\n", num, X86_AX, getIntVect(num)); switch (num) { -#ifndef _PC case 0x10: case 0x42: case 0x6D: @@ -188,7 +336,6 @@ ret = 1; } break; -#endif case 0x15: //ret = int15_handler(); ret = 1; @@ -198,7 +345,7 @@ ret = 0; break; case 0x1A: - ret = pcibios_handler(); + ret = int1a_handler(); ret = 1; break; case 0xe6: @@ -214,159 +361,124 @@ } -#if 0 -#define SYS_BIOS 0xf0000 /* * here we are really paranoid about faking a "real" * BIOS. Most of this information was pulled from * dosemu. */ -#if 0 -void setup_int_vect(void) +static void setup_system_bios(void) { int i; - /* let the int vects point to the SYS_BIOS seg */ - for (i = 0; i < 0x80; i++) { - MEM_WW(i << 2, 0); - MEM_WW((i << 2) + 2, SYS_BIOS >> 4); - } + /* Set up Interrupt Vectors. The IVT starts at 0x0000:0x0000 + * Additionally, we put some stub code into the F segment for + * those pesky little buggers that jmp to the hard coded addresses + * instead of calling int XX. This stub code looks like this + * + * CD XX int 0xXX + * C3 ret + * F4 hlt + */ - reset_int_vect(); - - /* font tables default location (int 1F) */ - MEM_WW(0x1f << 2, 0xfa6e); + /* int 05 default location (Bound Exceeded) */ + MEM_WL(0x05 << 2, 0xf000ff54); + MEM_WL(0xfff54, 0xf4c305cd); + /* int 08 default location (Double Fault) */ + MEM_WL(0x08 << 2, 0xf000fea5); + MEM_WL(0xffea5, 0xf4c308cd); + /* int 0E default location (Page Fault) */ + MEM_WL(0x0e << 2, 0xf000ef57); + MEM_WL(0xfef57, 0xf4c30ecd); + /* int 10 default location */ + MEM_WL(0x10 << 2, 0xf000f065); + MEM_WL(0xff065, 0xf4c310cd); /* int 11 default location (Get Equipment Configuration) */ - MEM_WW(0x11 << 2, 0xf84d); + MEM_WL(0x11 << 2, 0xf000f84d); + MEM_WL(0xff84d, 0xf4c311cd); /* int 12 default location (Get Conventional Memory Size) */ - MEM_WW(0x12 << 2, 0xf841); + MEM_WL(0x12 << 2, 0xf000f841); + MEM_WL(0xff841, 0xf4c312cd); + /* int 13 default location (Disk) */ + MEM_WL(0x13 << 2, 0xf000ec59); + MEM_WL(0xfec59, 0xf4c313cd); + /* int 14 default location (Disk) */ + MEM_WL(0x14 << 2, 0xf000e739); + MEM_WL(0xfe739, 0xf4c314cd); /* int 15 default location (I/O System Extensions) */ - MEM_WW(0x15 << 2, 0xf859); + MEM_WL(0x15 << 2, 0xf000f859); + MEM_WL(0xf859, 0xf4c315cd); + /* int 16 default location */ + MEM_WL(0x16 << 2, 0xf000e82e); + MEM_WL(0xfe82e, 0xf4c316cd); + /* int 17 default location (Parallel Port) */ + MEM_WL(0x17 << 2, 0xf000efd2); + MEM_WL(0xfefd2, 0xf4c317cd); /* int 1A default location (RTC, PCI and others) */ - MEM_WW(0x1a << 2, 0xff6e); - /* int 05 default location (Bound Exceeded) */ - MEM_WW(0x05 << 2, 0xff54); - /* int 08 default location (Double Fault) */ - MEM_WW(0x08 << 2, 0xfea5); - /* int 13 default location (Disk) */ - MEM_WW(0x13 << 2, 0xec59); - /* int 0E default location (Page Fault) */ - MEM_WW(0x0e << 2, 0xef57); - /* int 17 default location (Parallel Port) */ - MEM_WW(0x17 << 2, 0xefd2); - /* fdd table default location (int 1e) */ - MEM_WW(0x1e << 2, 0xefc7); + MEM_WL(0x1a << 2, 0xf000fe6e); + MEM_WL(0xffe6e, 0xf4c31acd); + /* int 1E default location (FDD table) */ + MEM_WL(0x1e << 2, 0xf000efc7); + MEM_WL(0xfefc7, 0xf4c31ecd); + /* font tables default location (int 1F) */ + MEM_WL(0x1f << 2, 0xf000fa6e); + MEM_WL(0xffa6e, 0xf4c31fcd); + /* int 42 default location */ + MEM_WL(0x42 << 2, 0xf000f065); + /* int 6D default location */ + MEM_WL(0x6D << 2, 0xf000f065); - /* Set Equipment flag to VGA */ - i = MEM_RB(0x0410) & 0xCF; - MEM_WB(0x0410, i); - /* XXX Perhaps setup more of the BDA here. See also int42(0x00). */ -} + /* Clear EBDA */ + for (i=(INITIAL_EBDA_SEGMENT << 4); + i<(INITIAL_EBDA_SEGMENT << 4) + INITIAL_EBDA_SIZE; i++) + MEM_WB(i, 0); + /* at offset 0h in EBDA is the size of the EBDA in KB */ + MEM_WW((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024); -int setup_system_bios(void *base_addr) -{ - char *base = (char *) base_addr; + /* Clear BDA */ + for (i=0x400; i<0x500; i+=4) + MEM_WL(i, 0); - /* - * we trap the "industry standard entry points" to the BIOS - * and all other locations by filling them with "hlt" - * TODO: implement hlt-handler for these - */ - memset(base, 0xf4, 0x10000); + /* Set up EBDA */ + MEM_WW(0x40e, INITIAL_EBDA_SEGMENT); - /* set bios date */ - //strcpy(base + 0x0FFF5, "06/11/99"); - /* set up eisa ident string */ - //strcpy(base + 0x0FFD9, "PCI_ISA"); - /* write system model id for IBM-AT */ - //*((unsigned char *) (base + 0x0FFFE)) = 0xfc; + /* Set RAM size to 16MB (fake) */ + MEM_WW(0x413, 16384); - return 1; -} -#endif + // TODO Set up more of BDA here -void reset_int_vect(void) -{ - /* - * This table is normally located at 0xF000:0xF0A4. However, int 0x42, - * function 0 (Mode Set) expects it (or a copy) somewhere in the bottom - * 64kB. Note that because this data doesn't survive POST, int 0x42 should - * only be used during EGA/VGA BIOS initialisation. - */ - static const u8 VideoParms[] = { - /* Timing for modes 0x00 & 0x01 */ - 0x38, 0x28, 0x2d, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x02 & 0x03 */ - 0x71, 0x50, 0x5a, 0x0a, 0x1f, 0x06, 0x19, 0x1c, - 0x02, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for modes 0x04, 0x05 & 0x06 */ - 0x38, 0x28, 0x2d, 0x0a, 0x7f, 0x06, 0x64, 0x70, - 0x02, 0x01, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, - /* Timing for mode 0x07 */ - 0x61, 0x50, 0x52, 0x0f, 0x19, 0x06, 0x19, 0x19, - 0x02, 0x0d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00, - /* Display page lengths in little endian order */ - 0x00, 0x08, /* Modes 0x00 and 0x01 */ - 0x00, 0x10, /* Modes 0x02 and 0x03 */ - 0x00, 0x40, /* Modes 0x04 and 0x05 */ - 0x00, 0x40, /* Modes 0x06 and 0x07 */ - /* Number of columns for each mode */ - 40, 40, 80, 80, 40, 40, 80, 80, - /* CGA Mode register value for each mode */ - 0x2c, 0x28, 0x2d, 0x29, 0x2a, 0x2e, 0x1e, 0x29, - /* Padding */ - 0x00, 0x00, 0x00, 0x00 - }; - int i; + /* setup original ROM BIOS Area (F000:xxxx) */ + const char *date = "06/23/99"; + for (i = 0; date[i]; i++) + MEM_WB(0xffff5 + i, date[i]); + /* set up eisa ident string */ + const char *ident = "PCI_ISA"; + for (i = 0; ident[i]; i++) + MEM_WB(0xfffd9 + i, ident[i]); - for (i = 0; i < sizeof(VideoParms); i++) - MEM_WB(i + (0x1000 - sizeof(VideoParms)), VideoParms[i]); - MEM_WW(0x1d << 2, 0x1000 - sizeof(VideoParms)); - MEM_WW((0x1d << 2) + 2, 0); - - printk(BIOS_DEBUG,"SETUP INT\n"); - MEM_WW(0x10 << 2, 0xf065); - MEM_WW((0x10 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x42 << 2, 0xf065); - MEM_WW((0x42 << 2) + 2, SYS_BIOS >> 4); - MEM_WW(0x6D << 2, 0xf065); - MEM_WW((0x6D << 2) + 2, SYS_BIOS >> 4); + // write system model id for IBM-AT + // according to "Ralf Browns Interrupt List" Int15 AH=C0 Table 515, + // model FC is the original AT and also used in all DOSEMU Versions. + MEM_WB(0xFFFFE, 0xfc); } -#endif +#define BIOSEMU_MEM_BASE 0x00000000 +#define BIOSEMU_MEM_SIZE 0x00100000 void run_bios(struct device * dev, unsigned long addr) { -#if 1 int i; - unsigned short initialcs = (addr & 0xF0000) >> 4; - unsigned short initialip = (addr + 3) & 0xFFFF; - unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; - + u16 initialcs = (addr & 0xF0000) >> 4; + u16 initialip = (addr + 3) & 0xFFFF; + u16 devfn = (dev->bus->secondary << 8) | dev->path.pci.devfn; X86EMU_intrFuncs intFuncs[256]; - X86EMU_setMemBase(0, 0x100000); - X86EMU_setupPioFuncs(&myfuncs); + X86EMU_setMemBase(BIOSEMU_MEM_BASE, BIOSEMU_MEM_SIZE); + X86EMU_setupPioFuncs(&biosemu_piofuncs); for (i = 0; i < 256; i++) intFuncs[i] = do_int; X86EMU_setupIntrFuncs(intFuncs); - { - char *date = "01/01/99"; - for (i = 0; date[i]; i++) - wrb(0xffff5 + i, date[i]); - wrb(0xffff7, '/'); - wrb(0xffffa, '/'); - } + setup_system_bios(); - { - /* FixME: move PIT init to its own file */ - outb(0x36, 0x43); - outb(0x00, 0x40); - outb(0x00, 0x40); - } - //setup_int_vect(); - /* cpu setup */ X86_AX = devfn ? devfn : 0xff; X86_DX = 0x80; @@ -374,26 +486,37 @@ X86_CS = initialcs; /* Initialize stack and data segment */ - X86_SS = initialcs; - X86_SP = 0xfffe; - X86_DS = 0x0040; - X86_ES = 0x0000; + X86_SS = STACK_SEGMENT; + X86_SP = STACK_START_OFFSET;; + X86_DS = DATA_SEGMENT; /* We need a sane way to return from bios * execution. A hlt instruction and a pointer * to it, both kept on the stack, will do. */ - pushw(0xf4f4); /* hlt; hlt */ - pushw(X86_SS); - pushw(X86_SP + 2); + push_word(0xf4f4); /* hlt; hlt */ + push_word(X86_SS); + push_word(X86_SP + 2); #ifdef CONFIG_DEBUG //X86EMU_trace_on(); #endif - printk("entering emulator\n"); + printk("Executing Initialization Vector...\n"); X86EMU_exec(); - printk("exited emulator\n"); + printk("Option ROM Exit Status: %04x\n", X86_AX); -#endif + /* Check whether the stack is "clean" i.e. containing the HLT + * instruction we pushed before executing and pointing to the original + * stack address... indicating that the initialization probably was + * successful + */ + if ((pop_word() == 0xf4f4) && (X86_SS == STACK_SEGMENT) + && (X86_SP == STACK_START_OFFSET)) { + printk("Stack is clean, initialization successfull!\n"); + } else { + printk("Stack unclean, initialization probably NOT COMPLETE!!\n"); + printk("SS:SP = %04x:%04x, expected: %04x:%04x\n", + X86_SS, X86_SP, STACK_SEGMENT, STACK_START_OFFSET); + } } Index: util/x86emu/Makefile.inc =================================================================== --- util/x86emu/Makefile.inc (revision 4909) +++ util/x86emu/Makefile.inc (working copy) @@ -20,7 +20,6 @@ subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += x86emu obj-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += biosemu.o -subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += pcbios obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86.o obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86_asm.o Index: util/x86emu/Makefile =================================================================== --- util/x86emu/Makefile (revision 4909) +++ util/x86emu/Makefile (working copy) @@ -22,7 +22,7 @@ X86EMU_SRC = debug.c decode.c fpu.c ops.c ops2.c prim_ops.c sys.c ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) -BIOSEMU_SRC = biosemu.c pcbios/pcibios.c +BIOSEMU_SRC = biosemu.c endif ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL),y)

2 3

CPU Frequency setting
by Peter Joanes 05 Nov '09

05 Nov '09

I would like to ask whether it might be possible to modify the S2882 Coreboot config so that it includes a way to set the processor frequency. I have recently attempted to upgrade my S2882 based system, but encountered stability problems which (after much experimenting) seem simply to be a case of the board not being able to handle the 2.8Ghz Opteron 254's I have put in it (which are shown as supported on http://www.tyan.com/support_download_cpu2.aspx?socketid=9 ). If the machine completes booting, I can set the frequency to 2.6Ghz, and then all is fine, so I would like to exclude the 2.8Ghz frequency earlier in the process (perhaps using Coreboot or maybe a slightly-modified bootloader). Thanks, - Peter. _________________________________________________________________ New Windows 7: Simplify what you do everyday. Find the right PC for you. http://www.microsoft.com/uk/windows/buy/

2 1

[RFC] network console for coreboot and ethernet support for SerialICE
by Rudolf Marek 05 Nov '09

05 Nov '09

Hello all, You may ask what is it all about? Well, for SerialICE we have no RAM, therefore sending through network adapter is not quite easy - you can't even place a descriptors for DMA in RAM ;) For coreboot we have CAR but same problem, DMA wants a working memory. Remember those old days with Novell Netware? Packwars? Netwars? This time is connected with a NE2000 cards. To reduce a cost it is nearly an reference design of the NS8390 chip. No external DMA, insane registers ;) The Novell needed very cheap Ethernet adapters - because their business was to license of Nowell Netware per node. They simple needed to make the ethernet adapters affordable. As the consequence of this NE2000 chips survived even to PCI era. The Realtek made some chip called RTL8029AS. This chip is still quite wide spread. I bet you have some 10Mbit/s ethernet cards around (twisted pair) most likely with this chip... End of story? No! The sweet features of this chip: * insane registers * no DMA, only PIO * 8bit/16 IO bit access * 10Mbit/Full duplex ;) * Nice hardware bugs ;) ? * 16KB SRAM for TX/RX buffers Now you know ;) The idea is to create the packets in the card SRAM, construct some UDP packets with destination eth address as broadcasts. This will ensure we need no ARP. Packets can be also received, parsing of packets is like reading a very long FIFO byte to byte or word by word. Therefore I think one could have this card plugged to some PCI slot in the system and use it for quite fast IO. The K8 HT chain most likely works to SB so the PCI adpaters are accessible early too. The only way which needs to be set is the IO resource and enable decoding of this resource in PCI_CMD. I think problems will only arise if the bus for PCI slot is not the primary. For the coreboot, I think we can use pci_find_device to "dynamically" read the current IO port from PCI BAR. What do you think? I and agaran (aka Maciej) started to hack this together. We used GPXE as code base for this, now we are able to send/receive data in linux userspace application. The usage idea is to have 8029 card as the "console" similar way as linux netconsole for coreboot. The SerialICE could be changed to use the network instead of slow serial. Any clue what might cause that this does not work? Rudolf

2 1

[PATCH 2/9] Only add the first logical CPU in each physical CPU to the MPS tables.
by Magnus Christensson 05 Nov '09

05 Nov '09

--- src/mptable.c | 28 ++++++++++++++++++++++++---- 1 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/mptable.c b/src/mptable.c index 805fe1b..0c07cfb 100644 --- a/src/mptable.c +++ b/src/mptable.c @@ -10,6 +10,15 @@ #include "mptable.h" // MPTABLE_SIGNATURE #include "paravirt.h" +static inline unsigned long +fls(unsigned long word) +{ + asm("bsr %1,%0" + : "=r" (word) + : "rm" (word)); + return word + 1; +} + void mptable_init(void) { @@ -44,16 +53,25 @@ mptable_init(void) config->spec = 4; memcpy(config->oemid, CONFIG_CPUNAME8, sizeof(config->oemid)); memcpy(config->productid, "0.1 ", sizeof(config->productid)); - config->entrycount = MaxCountCPUs + 2 + 16; config->lapic = BUILD_APIC_ADDR; // CPU definitions. u32 cpuid_signature, ebx, ecx, cpuid_features; cpuid(1, &cpuid_signature, &ebx, &ecx, &cpuid_features); struct mpt_cpu *cpus = (void*)&config[1]; - int i; - for (i = 0; i < MaxCountCPUs; i++) { + int i, actual_cpu_count; + for (i = 0, actual_cpu_count = 0; i < MaxCountCPUs; i++) { struct mpt_cpu *cpu = &cpus[i]; + int log_cpus = (ebx >> 16) & 0xff; + log_cpus = 1UL << fls(log_cpus - 1); /* round up to power of 2 */ + + /* Only populate the MPS tables with the first logical CPU in each + package */ + if ((cpuid_features & (1 << 28)) && (i & (log_cpus - 1)) != 0) + continue; + + actual_cpu_count++; + memset(cpu, 0, sizeof(*cpu)); cpu->type = MPT_TYPE_CPU; cpu->apicid = i; @@ -72,8 +90,10 @@ mptable_init(void) } } + config->entrycount = actual_cpu_count + 2 + 16; + /* isa bus */ - struct mpt_bus *bus = (void*)&cpus[MaxCountCPUs]; + struct mpt_bus *bus = (void*)&cpus[actual_cpu_count]; memset(bus, 0, sizeof(*bus)); bus->type = MPT_TYPE_BUS; memcpy(bus->bustype, "ISA ", sizeof(bus->bustype)); -- 1.6.2.5 --------------020508030901070003090208 Content-Type: text/x-patch; name="0003-Remove-device-access-from-loop-to-make-it-faster-whe.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="0003-Remove-device-access-from-loop-to-make-it-faster-whe.pa"; filename*1="tch"

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coreboot November 2009