coreboot November 2009

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[v2] r4925 - in trunk/src: devices drivers include/device mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/arima/hdama mainboard/artecgroup/dbe61/realmode mainboard/asi/mb_5blmp mainboard/asus/mew-vm mainboard/broadcom/blast mainboard/digitallogic/msm586seg mainboard/emulation/qemu-x86 mainboard/gigabyte/ga_2761gxdk mainboard/hp/dl145_g3 mainboard/hp/e_vectra_p2706t mainboard/ibm/e326 mainboard/intel/d945gclf mainboard/intel/xe7501devkit mainboard/iwill/dk8_htx mainboard/kontron/986lcd-m m
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009) New Revision: 4925 Removed: trunk/src/drivers/pci/ Modified: trunk/src/devices/pci_device.c trunk/src/devices/pci_rom.c trunk/src/drivers/Makefile.inc trunk/src/include/device/device.h trunk/src/mainboard/amd/dbm690t/Config.lb trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/pistachio/Config.lb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/arima/hdama/Config.lb trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c trunk/src/mainboard/asi/mb_5blmp/Config.lb trunk/src/mainboard/asi/mb_5blmp/devicetree.cb trunk/src/mainboard/asus/mew-vm/Config.lb trunk/src/mainboard/asus/mew-vm/devicetree.cb trunk/src/mainboard/broadcom/blast/Config.lb trunk/src/mainboard/broadcom/blast/devicetree.cb trunk/src/mainboard/digitallogic/msm586seg/Config.lb trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb trunk/src/mainboard/emulation/qemu-x86/mainboard.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb trunk/src/mainboard/hp/dl145_g3/Config.lb trunk/src/mainboard/hp/dl145_g3/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/ibm/e326/Config.lb trunk/src/mainboard/ibm/e326/devicetree.cb trunk/src/mainboard/intel/d945gclf/Config.lb trunk/src/mainboard/intel/d945gclf/devicetree.cb trunk/src/mainboard/intel/xe7501devkit/Config.lb trunk/src/mainboard/intel/xe7501devkit/devicetree.cb trunk/src/mainboard/iwill/dk8_htx/Config.lb trunk/src/mainboard/iwill/dk8_htx/devicetree.cb trunk/src/mainboard/kontron/986lcd-m/Config.lb trunk/src/mainboard/kontron/986lcd-m/devicetree.cb trunk/src/mainboard/kontron/kt690/Config.lb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/mitac/6513wu/Config.lb trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/msi/ms6178/Config.lb trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms9185/Config.lb trunk/src/mainboard/msi/ms9185/devicetree.cb trunk/src/mainboard/msi/ms9282/Config.lb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/nec/powermate2000/Config.lb trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/newisys/khepri/Config.lb trunk/src/mainboard/rca/rm4100/Config.lb trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/sunw/ultra40/Config.lb trunk/src/mainboard/sunw/ultra40/devicetree.cb trunk/src/mainboard/supermicro/h8dme/Config.lb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/Config.lb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/technexion/tim5690/Config.lb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/Config.lb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/mainboard/technologic/ts5300/Config.lb trunk/src/mainboard/technologic/ts5300/devicetree.cb trunk/src/mainboard/thomson/ip1000/Config.lb trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/tyan/s2735/Config.lb trunk/src/mainboard/tyan/s2735/devicetree.cb trunk/src/mainboard/tyan/s2850/Config.lb trunk/src/mainboard/tyan/s2850/devicetree.cb trunk/src/mainboard/tyan/s2875/Config.lb trunk/src/mainboard/tyan/s2875/devicetree.cb trunk/src/mainboard/tyan/s2880/Config.lb trunk/src/mainboard/tyan/s2880/devicetree.cb trunk/src/mainboard/tyan/s2881/Config.lb trunk/src/mainboard/tyan/s2881/devicetree.cb trunk/src/mainboard/tyan/s2882/Config.lb trunk/src/mainboard/tyan/s2882/devicetree.cb trunk/src/mainboard/tyan/s2885/Config.lb trunk/src/mainboard/tyan/s2885/devicetree.cb trunk/src/mainboard/tyan/s2891/devicetree.cb trunk/src/mainboard/tyan/s2892/devicetree.cb trunk/src/mainboard/tyan/s2895/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/Config.lb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb trunk/src/mainboard/tyan/s4880/Config.lb trunk/src/mainboard/tyan/s4880/devicetree.cb trunk/src/mainboard/tyan/s4882/Config.lb trunk/src/mainboard/tyan/s4882/devicetree.cb trunk/src/mainboard/via/epia/Config.lb trunk/src/mainboard/via/epia/devicetree.cb trunk/src/mainboard/via/vt8454c/Config.lb trunk/src/mainboard/via/vt8454c/devicetree.cb trunk/src/northbridge/via/cn400/vga.c trunk/src/northbridge/via/cn700/vga.c trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/vga.c trunk/src/southbridge/nvidia/ck804/chip.h trunk/src/southbridge/nvidia/ck804/ck804.c Log: Remove drivers/pci/onboard. The only purpose was for option ROMs, which are now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/pci_device.c =================================================================== --- trunk/src/devices/pci_device.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_device.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -285,11 +285,6 @@ unsigned long value; resource_t moving; - if ((dev->on_mainboard) && (dev->rom_address == 0)) { - /* Skip it if rom_address is not set in the MB Config.lb. */ - return; - } - /* Initialize the resources to nothing. */ resource = new_resource(dev, index); @@ -326,18 +321,6 @@ } resource->flags = 0; } - - /* For on board device with embedded ROM image, the ROM image is at - * fixed address specified in the Config.lb, the dev->rom_address is - * inited by driver_pci_onboard_ops::enable_dev() */ - if ((dev->on_mainboard) && (dev->rom_address != 0)) { - resource->base = dev->rom_address; - /* The resource allocator needs the size to be non-zero. */ - resource->size = 0x100; - resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - compact_resources(dev); } Modified: trunk/src/devices/pci_rom.c =================================================================== --- trunk/src/devices/pci_rom.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_rom.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -31,42 +31,37 @@ struct rom_header * pci_rom_probe(struct device *dev) { - unsigned long rom_address = 0; struct rom_header *rom_header; struct pci_data *rom_data; - void *v; - /* if it's in FLASH, then it's as if dev->on_mainboard was true */ - v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - printk_debug("In cbfs, rom address for %s = %p\n", - dev_path(dev), v); - if (v) { - dev->rom_address = (u32)v; - dev->on_mainboard = 1; - } + /* If it's in FLASH, then don't check device for ROM. */ + rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - if (dev->on_mainboard) { - // in case some device PCI_ROM_ADDRESS can not be set or readonly - rom_address = dev->rom_address; - printk_debug("On mainboard, rom address for %s = %lx\n", - dev_path(dev), rom_address); + if (rom_header) { + printk_debug("In cbfs, rom address for %s = %p\n", + dev_path(dev), rom_header); } else { + unsigned long rom_address; + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - printk_debug("On card, rom address for %s = %lx\n", - dev_path(dev), rom_address); - } - if (rom_address == 0x00000000 || rom_address == 0xffffffff) { - return NULL; - } + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + #if CONFIG_BOARD_EMULATION_QEMU_X86 + rom_address = 0xc0000; + #else + return NULL; + #endif + } else { + /* enable expansion ROM address decoding */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); + } - if(!dev->on_mainboard) { - /* enable expansion ROM address decoding */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); + printk_debug("On card, rom address for %s = %lx\n", + dev_path(dev), rom_address); + rom_header = (struct rom_header *)rom_address; } - rom_header = (struct rom_header *)rom_address; printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), rom_header->size * 512, le32_to_cpu(rom_header->data)); @@ -76,11 +71,12 @@ return NULL; } - rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data)); + rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { - printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", + printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n", rom_data->vendor, rom_data->device); return NULL; } @@ -90,7 +86,8 @@ rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { printk_debug("Class Code mismatch ROM %08x, dev %08x\n", - (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); + (rom_data->class_hi << 8) | rom_data->class_lo, + dev->class); //return NULL; } Modified: trunk/src/drivers/Makefile.inc =================================================================== --- trunk/src/drivers/Makefile.inc 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/drivers/Makefile.inc 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,3 +1,2 @@ -subdirs-y += pci subdirs-y += generic/debug subdirs-y += ati/ragexl Modified: trunk/src/include/device/device.h =================================================================== --- trunk/src/include/device/device.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/include/device/device.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -70,7 +70,6 @@ unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int on_mainboard : 1; - unsigned long rom_address; u8 command; Modified: trunk/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -156,9 +156,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -177,9 +177,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on Modified: trunk/src/mainboard/arima/hdama/devicetree.cb =================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,9 +73,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,10 +1,6 @@ #ifndef PCI_REALMODE_H #define PCI_REALMODE_H -struct drivers_pci_realmode_config -{ - unsigned long rom_address; -}; //struct chip_operations; extern struct chip_operations drivers_pci_realmode_ops; Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -74,36 +74,6 @@ emulator to successfully run this bios. */ - - - -/* - Modified to be an universal driver for loading VGA ROMs. - Aug 2006, anti.sullin(a)artecdesign.ee, Artec Design - - USAGE: - define in your motherboard Config.lb file in device hierarchy - around the VGA pci device realmode chip and define its rom address. - Rom address is read from Config.lb, this rom is then copied to 0xC000 and then excecuted - - chip drivers/pci/realmode - device pci 1.1 on end # VGA - register "rom_address" = "0xfffc0000" # at the beginning of 256k - end - - then, chip enable is called at this list first traversal, and this sets - up device's init callback. Device init is called during last list traversal and - so, other hw should be already initialized to run vga bios successfully. -*/ - - - - - - - - - /* Declare a temporary global descriptor table - necessary because the Core part of the bios no longer sets up any 16 bit segments */ __asm__ ( @@ -918,8 +888,6 @@ // code to make vga init go through the emulator - as of yet this does not workfor the epia-m dev->on_mainboard=1; - dev->rom_address = (void *)cfg->rom_address; - pci_dev_init(dev); // code to make vga init run in real mode - does work but against the current coreboot philosophy Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -135,11 +135,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -37,11 +37,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,18 +97,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb =================================================================== --- trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,18 +2,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,21 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0 device pci 18.0 on end Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb =================================================================== --- trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,21 +105,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0 device pci 18.0 on end Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -102,13 +102,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,13 +1,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c =================================================================== --- trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -16,7 +16,6 @@ * force coreboot to use it. */ dev->on_mainboard = 1; - dev->rom_address = 0xc0000; /* Now do the usual initialization */ pci_dev_init(dev); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -178,9 +178,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,9 +11,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -195,15 +195,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -72,15 +72,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -76,9 +76,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,9 +7,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -125,9 +125,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 Modified: trunk/src/mainboard/ibm/e326/devicetree.cb =================================================================== --- trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 Modified: trunk/src/mainboard/intel/d945gclf/Config.lb =================================================================== --- trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -150,9 +150,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -28,9 +28,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -127,9 +127,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -25,9 +25,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -232,9 +232,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -24,9 +24,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -153,9 +153,7 @@ device pci 00.0 on end # host bridge # autodetect 0:1.0 because it might or might not be there. # device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -9,9 +9,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/kontron/kt690/Config.lb =================================================================== --- trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/mitac/6513wu/Config.lb =================================================================== --- trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -80,9 +80,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb =================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" Modified: trunk/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,29 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,29 +73,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end Modified: trunk/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -278,27 +278,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -137,27 +137,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot Modified: trunk/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,11 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb =================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,11 +6,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -98,8 +98,6 @@ config chip.h -# FIXME: ROM for onboard VGA - chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_940 Modified: trunk/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb =================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -210,8 +210,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -243,7 +241,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb =================================================================== --- trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -106,8 +106,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -139,7 +137,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -254,9 +254,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -92,9 +92,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -276,9 +276,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -280,9 +280,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,9 +114,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,12 +104,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb =================================================================== --- trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,12 +2,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb =================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -100,10 +100,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -117,12 +115,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,10 +6,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -23,12 +21,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -119,9 +119,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,9 +17,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -123,9 +123,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -113,10 +113,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -135,12 +133,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,10 +11,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -33,12 +31,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -115,14 +115,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -136,12 +132,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -13,14 +13,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -34,12 +30,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,14 +114,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -135,16 +131,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,14 +12,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -33,16 +29,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -137,9 +135,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,9 +19,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -35,9 +33,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,9 +104,7 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 7.0 on end - end + device pci 7.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -127,10 +125,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,12 +105,9 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end - end + device pci 6.0 on end + # end + device pci 8.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -131,10 +128,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -111,10 +111,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 6.0 on end # lsi scsi - device pci 6.1 on end - end + device pci 6.0 on end # lsi scsi + device pci 6.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -279,9 +279,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -116,10 +116,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -133,9 +131,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,10 +19,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -36,9 +34,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,10 +114,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -132,12 +130,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,10 +17,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -35,12 +33,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/src/mainboard/via/epia/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -96,10 +96,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0" Modified: trunk/src/mainboard/via/epia/devicetree.cb =================================================================== --- trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,10 +2,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0" Modified: trunk/src/mainboard/via/vt8454c/Config.lb =================================================================== --- trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb =================================================================== --- trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,9 +12,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE Modified: trunk/src/northbridge/via/cn400/vga.c =================================================================== --- trunk/src/northbridge/via/cn400/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn400/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,15 +121,8 @@ #endif } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/cn700/vga.c =================================================================== --- trunk/src/northbridge/via/cn700/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn700/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -101,15 +101,8 @@ memset(0xf0000, 0, 0x10000); } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/cx700/cx700_vga.c =================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,15 +97,8 @@ outb(reg8, SR_DATA); } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -124,9 +124,6 @@ #if 0 /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */ - dev->on_mainboard=1; - dev->rom_address = (void *)0xfffc0000; - pci_dev_init(dev); call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); @@ -167,17 +164,8 @@ #endif } -static void vga_read_resources(device_t dev) -{ - - dev->rom_address = (void *)0xfffc0000; - dev->on_mainboard=1; - pci_dev_read_resources(dev); - -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/vx800/vga.c =================================================================== --- trunk/src/northbridge/via/vx800/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vx800/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -126,15 +126,8 @@ } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1); - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/southbridge/nvidia/ck804/chip.h =================================================================== --- trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,8 +7,6 @@ unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned long nic_rom_address; - unsigned long raid_rom_address; unsigned int mac_eeprom_smbus; unsigned int mac_eeprom_addr; }; Modified: trunk/src/southbridge/nvidia/ck804/ck804.c =================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -77,12 +77,10 @@ case PCI_DEVICE_ID_NVIDIA_CK804_NIC: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_ACI: devfn -= (3 << 3); @@ -95,7 +93,6 @@ case PCI_DEVICE_ID_NVIDIA_CK804_IDE: devfn -= (5 << 3); index = 14; - dev->rom_address = conf->raid_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: devfn -= (6 << 3);

1 0

rev 5000 is coming!
by ron minnich 06 Nov '09

06 Nov '09

Wow! what special event should be there for rev 5000? ron

3 2

[PATCH] Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb
by Uwe Hermann 06 Nov '09

06 Nov '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

5 9

[PATCH] __ROMCC__ ifdefs
by Myles Watson 06 Nov '09

06 Nov '09

I think it's time to separate the two meanings of __ROMCC__. Right now it is used for: 1. Use simple functions and data types since we don't have RAM 2. Don't use prototypes, romcc doesn't support them. Right now the patch creates __PRE_RAMINIT__ The name is not the most important part of the patch, and can easily be changed. Here are some of the suggestions so far: __PRE_RAM__ __NO_RAM_YET__ __DURING_RAMINIT__ __USE_NO_RAM__ Unless it was obvious to me which meaning was the correct one for a file, I added both for now. Abuild tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 3

[PATCH] Various x86emu fixes
by Mark Marshall 06 Nov '09

06 Nov '09

Below are three small patches, they all seemed useful while I have been working with VGA option ROMs. Thanks for the great work. MM

6 7

Defined but not used warnings
by Myles Watson 06 Nov '09

06 Nov '09

There are a lot of "defined but not used" warnings. I'd like to build without them, but I can't figure out the correct switch without disabling other warnings that I want. Does anyone know which flag to use? Thanks, Myles

1 0

build service results for r4922
by coreboot information 06 Nov '09

06 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4922 to the coreboot repository. This caused the following changes: Change Log: Revert the deletion of drivers/pci/onboard that snuck in ahead of its time. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Configuration of amd:dbm690t has been fixed Configuration of amd:pistachio has been fixed Configuration of arima:hdama has been fixed Configuration of broadcom:blast has been fixed Configuration of digitallogic:msm586seg has been fixed Configuration of gigabyte:ga_2761gxdk has been fixed Configuration of hp:e_vectra_p2706t has been fixed Configuration of ibm:e326 has been fixed Configuration of intel:d945gclf has been fixed Configuration of intel:xe7501devkit has been fixed Configuration of kontron:986lcd-m has been fixed Configuration of kontron:kt690 has been fixed Configuration of mitac:6513wu has been fixed Configuration of msi:ms6178 has been fixed Configuration of msi:ms9185 has been fixed Configuration of msi:ms9282 has been fixed Configuration of rca:rm4100 has been fixed Configuration of supermicro:h8dme has been fixed Configuration of supermicro:h8dmr has been fixed Configuration of supermicro:h8dmr_fam10 has been fixed Configuration of technexion:tim5690 has been fixed Configuration of technexion:tim8690 has been fixed Configuration of thomson:ip1000 has been fixed Configuration of tyan:s2735 has been fixed Configuration of tyan:s2850 has been fixed Configuration of tyan:s2875 has been fixed Configuration of tyan:s2880 has been fixed Configuration of tyan:s2881 has been fixed Configuration of tyan:s2882 has been fixed Configuration of tyan:s2885 has been fixed Configuration of tyan:s2891 has been fixed Configuration of tyan:s2892 has been fixed Configuration of tyan:s2895 has been fixed Configuration of tyan:s2912_fam10 has been fixed Configuration of tyan:s4880 has been fixed Configuration of tyan:s4882 has been fixed Configuration of via:vt8454c has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4924 - in trunk/src/mainboard: amd/dbm690t amd/pistachio gigabyte/m57sli technexion/tim8690
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 17:32:32 +0000 (Fri, 06 Nov 2009) New Revision: 4924 Modified: trunk/src/mainboard/amd/dbm690t/Config.lb trunk/src/mainboard/amd/pistachio/Config.lb trunk/src/mainboard/gigabyte/m57sli/Config.lb trunk/src/mainboard/gigabyte/m57sli/devicetree.cb trunk/src/mainboard/technexion/tim8690/Config.lb Log: Remove some white space and comment differences from devicetree.cb and Config.lb files. These boards have non-trivial differences: gigabyte/m57sli kontron/986lcd-m dell/s1850 via/epia-m700 Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) +++ trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) @@ -136,7 +136,7 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support Modified: trunk/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) +++ trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) @@ -136,7 +136,7 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support Modified: trunk/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) +++ trunk/src/mainboard/gigabyte/m57sli/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) @@ -1,29 +1,29 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb -arch i386 end +arch i386 end ## ## Build the objects we have code for in this directory. @@ -36,28 +36,28 @@ if CONFIG_GENERATE_MP_TABLE object mptable.o end if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - if CONFIG_USE_INIT + if CONFIG_USE_INIT makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" + action "perl -e 's/\.rodata/.rom.data/g' -pi $@" + action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR - makerule ./apc_auto.o - depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" - end - ldscript /arch/i386/init/ldscript_apc.lb + makerule ./apc_auto.o + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" + end + ldscript /arch/i386/init/ldscript_apc.lb end end @@ -79,32 +79,32 @@ mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end ## ## Build our reset vector (This is where coreboot is entered) ## if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end end @@ -118,12 +118,12 @@ ## ROMSTRAP table for MCP55 ## if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE + if CONFIG_USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end else - if CONFIG_USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit southbridge/nvidia/mcp55/romstrap.inc ldscript /southbridge/nvidia/mcp55/romstrap.lds end @@ -135,7 +135,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc ### -### This is the early phase of coreboot startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### @@ -176,209 +176,187 @@ end ## -## Include the secondary Configuration files +## Include the secondary Configuration files ## config chip.h chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f - # Floppy and any LDN - device pnp 2e.0 on - # Watchdog from CLKIN, CLKIN = 24 MHz - irq 0x23 = 0x11 + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end +end +device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f + # Floppy and any LDN + device pnp 2e.0 on + # Watchdog from CLKIN, CLKIN = 24 MHz + irq 0x23 = 0x11 # Serial Flash (SPI only) - #0x24 = 0x1a - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO, SPI flash - # pin 84 is not GP10 - irq 0x25 = 0x0 - # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 - irq 0x26 = 0x43 - # pin 13 is GP35 - irq 0x27 = 0x20 - # pin 70 is not GP46 - #irq 0x28 = 0x0 - # pin 6,3,128,127,126 is GP63,64,65,66,67 - irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V - #irq 0x2c = 0x1f - # Simple I/O base - io 0x62 = 0x800 - # Serial Flash I/O (SPI only) - io 0x64 = 0x820 - # watch dog force timeout (parallel flash only) - #irq 0x71 = 0x1 - # No WDT interrupt - irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup - irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup - irq 0xbc = 0x01 - # SIO pin set 1 alternate function - #irq 0xc0 = 0x0 - # SIO pin set 2 mixed function - irq 0xc1 = 0x43 - # SIO pin set 3 mixed function - irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - #irq 0xc3 = 0x0 - # SIO pin set 1 input mode - #irq 0xc8 = 0x0 - # SIO pin set 2 input mode - irq 0xc9 = 0x0 - # SIO pin set 4 input mode - #irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - #irq 0xf0 = 0x10 - # SMI# level trigger - #irq 0xf1 = 0x40 - # HWMON alert beep pin location - irq 0xf6 = 0x28 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR + #0x24 = 0x1a + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO, SPI flash + # pin 84 is not GP10 + irq 0x25 = 0x0 + # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # pin 13 is GP35 + irq 0x27 = 0x20 + # pin 70 is not GP46 + #irq 0x28 = 0x0 + # pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + #irq 0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + io 0x64 = 0x820 + # watch dog force timeout (parallel flash only) + #irq 0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + #irq 0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + #irq 0xc3 = 0x0 + # SIO pin set 1 input mode + #irq 0xc8 = 0x0 + # SIO pin set 2 input mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + #irq 0xcb = 0x0 + # Generate SMI# on EC IRQ + #irq 0xf0 = 0x10 + # SMI# level trigger + #irq 0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM #WTF?!? We already have device pci 1.1 in the section above - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + device pci 1.1 on # SM 1 + chip drivers/generic/generic #MAC EEPROM + device i2c 51 on end + end + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end #device pci 18.0 device pci 18.0 on end # Link 1 device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end end #root_complex Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) +++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) @@ -5,11 +5,11 @@ end end device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on - chip southbridge/nvidia/mcp55 - device pci 0.0 on end - device pci 1.0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 + device pci 0.0 on end # HT + device pci 1.0 on # LPC chip superio/ite/it8716f # Floppy and any LDN device pnp 2e.0 on @@ -52,7 +52,7 @@ # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 irq 0x26 = 0x43 # pin 13 is GP35 - irq 0x27 = 0x20 + irq 0x27 = 0x20 # pin 70 is not GP46 #irq 0x28 = 0x0 # pin 6,3,128,127,126 is GP63,64,65,66,67 @@ -66,7 +66,7 @@ # watch dog force timeout (parallel flash only) #irq 0x71 = 0x1 # No WDT interrupt - irq 0x72 = 0x0 + irq 0x72 = 0x0 # GPIO pin set 1 disable internal pullup irq 0xb8 = 0x0 # GPIO pin set 5 enable internal pullup @@ -99,11 +99,10 @@ device pnp 2e.9 off # GAME io 0x60 = 0x220 end - device pnp 2e.a off # CIR - end + device pnp 2e.a off end # CIR end end - device pci 1.1 on + device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end @@ -129,22 +128,22 @@ device i2c 57 on end end end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AUDIO - device pci 8.0 on end # NIC - device pci 9.0 off end # N/A - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AUDIO + device pci 8.0 on end # NIC + device pci 9.0 off end # N/A + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" @@ -153,13 +152,14 @@ end end #device pci 18.0 device pci 18.0 on end # Link 1 + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 end # PCI domain -# chip drivers/generic/debug +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem @@ -170,6 +170,5 @@ # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io -# end - +# end end #root_complex Modified: trunk/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) +++ trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) @@ -136,7 +136,7 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support

1 0

build service results for r4921
by coreboot information 06 Nov '09

06 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4921 to the coreboot repository. This caused the following changes: Change Log: Split the two usages of __ROMCC__: __ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Configuration of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=dbm690t&vendor… Configuration of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=pistachio&vend… Configuration of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=hdama&vendor=a… Configuration of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=blast&vendor=b… Configuration of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=msm586seg&vend… Configuration of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ga_2761gxdk&ve… Configuration of hp:e_vectra_p2706t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=e_vectra_p2706… Configuration of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=e326&vendor=ib… Configuration of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=d945gclf&vendo… Configuration of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=xe7501devkit&v… Configuration of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=986lcd-m&vendo… Configuration of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=kt690&vendor=k… Configuration of mitac:6513wu has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=6513wu&vendor=… Configuration of msi:ms6178 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms6178&vendor=… Configuration of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms9185&vendor=… Configuration of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ms9282&vendor=… Configuration of rca:rm4100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=rm4100&vendor=… Configuration of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dme&vendor=s… Configuration of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dmr&vendor=s… Configuration of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=h8dmr_fam10&ve… Configuration of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=tim5690&vendor… Configuration of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=tim8690&vendor… Configuration of thomson:ip1000 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=ip1000&vendor=… Configuration of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2735&vendor=t… Configuration of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2850&vendor=t… Configuration of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2875&vendor=t… Configuration of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2880&vendor=t… Configuration of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2881&vendor=t… Configuration of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2882&vendor=t… Configuration of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2885&vendor=t… Configuration of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2891&vendor=t… Configuration of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2892&vendor=t… Configuration of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2895&vendor=t… Configuration of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s2912_fam10&ve… Configuration of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s4880&vendor=t… Configuration of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=s4882&vendor=t… Configuration of via:vt8454c has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4921&device=vt8454c&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4923 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/arima/hdama mainboard/asi/mb_5blmp mainboard/asus/mew-vm mainboard/broadcom/blast mainboard/digitallogic/msm586seg mainboard/gigabyte/ga_2761gxdk mainboard/hp/e_vectra_p2706t mainboard/ibm/e326 mainboard/intel/d945gclf mainboard/iwill/dk8_htx mainboard/kontron/986lcd-m mainboard/kontron/kt690 mainboard/mitac/6513wu mainboard/msi/ms6178 mainboard/msi/ms9185 mainboard/msi/ms9282 mainboard/nec/powermate2000 mainboard/
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 17:11:05 +0000 (Fri, 06 Nov 2009) New Revision: 4923 Modified: trunk/src/mainboard/amd/dbm690t/Config.lb trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/pistachio/Config.lb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/arima/hdama/Config.lb trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/asi/mb_5blmp/Config.lb trunk/src/mainboard/asi/mb_5blmp/devicetree.cb trunk/src/mainboard/asus/mew-vm/Config.lb trunk/src/mainboard/asus/mew-vm/devicetree.cb trunk/src/mainboard/broadcom/blast/Config.lb trunk/src/mainboard/broadcom/blast/devicetree.cb trunk/src/mainboard/digitallogic/msm586seg/Config.lb trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/ibm/e326/Config.lb trunk/src/mainboard/ibm/e326/devicetree.cb trunk/src/mainboard/intel/d945gclf/Config.lb trunk/src/mainboard/intel/d945gclf/devicetree.cb trunk/src/mainboard/iwill/dk8_htx/Config.lb trunk/src/mainboard/iwill/dk8_htx/devicetree.cb trunk/src/mainboard/kontron/986lcd-m/Config.lb trunk/src/mainboard/kontron/986lcd-m/devicetree.cb trunk/src/mainboard/kontron/kt690/Config.lb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/mitac/6513wu/Config.lb trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/msi/ms6178/Config.lb trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms9185/Config.lb trunk/src/mainboard/msi/ms9185/devicetree.cb trunk/src/mainboard/msi/ms9282/Config.lb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/nec/powermate2000/Config.lb trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/rca/rm4100/Config.lb trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/supermicro/h8dme/Config.lb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/Config.lb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/technexion/tim5690/Config.lb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/Config.lb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/mainboard/technologic/ts5300/Config.lb trunk/src/mainboard/technologic/ts5300/devicetree.cb trunk/src/mainboard/thomson/ip1000/Config.lb trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/tyan/s2850/Config.lb trunk/src/mainboard/tyan/s2850/devicetree.cb trunk/src/mainboard/tyan/s2875/Config.lb trunk/src/mainboard/tyan/s2875/devicetree.cb trunk/src/mainboard/tyan/s2880/Config.lb trunk/src/mainboard/tyan/s2880/devicetree.cb trunk/src/mainboard/tyan/s2881/Config.lb trunk/src/mainboard/tyan/s2881/devicetree.cb trunk/src/mainboard/tyan/s2882/Config.lb trunk/src/mainboard/tyan/s2882/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/Config.lb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb trunk/src/mainboard/tyan/s4880/Config.lb trunk/src/mainboard/tyan/s4880/devicetree.cb trunk/src/mainboard/tyan/s4882/Config.lb trunk/src/mainboard/tyan/s4882/devicetree.cb trunk/src/mainboard/via/vt8454c/Config.lb trunk/src/mainboard/via/vt8454c/devicetree.cb trunk/src/southbridge/amd/rs690/chip.h Log: Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb. Since we have CBFS setting rom_address in board files is no longer necessary. Also, drop vga_rom_address from RS690 completely, it was never used in the code. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -157,7 +157,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -22,7 +22,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 Modified: trunk/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -158,7 +158,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -23,7 +23,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 Modified: trunk/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -179,7 +179,6 @@ device pci 1.0 off end # LAN chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end ## PCI Slot 5 (correct?) #chip drivers/generic/generic Modified: trunk/src/mainboard/arima/hdama/devicetree.cb =================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -75,7 +75,6 @@ device pci 1.0 off end # LAN chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end ## PCI Slot 5 (correct?) #chip drivers/generic/generic Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -138,9 +138,6 @@ # device pci 12.4 on # VGA (onboard) # chip drivers/pci/onboard # device pci 12.4 on end - # register "rom_address" = "0xfffc0000" # 256 KB image - # # register "rom_address" = "0xfff80000" # 512 KB image - # # register "rom_address" = "0xfff00000" # 1 MB image # end # end device pci 13.0 on end # USB Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -40,9 +40,6 @@ # device pci 12.4 on # VGA (onboard) # chip drivers/pci/onboard # device pci 12.4 on end - # register "rom_address" = "0xfffc0000" # 256 KB image - # # register "rom_address" = "0xfff80000" # 512 KB image - # # register "rom_address" = "0xfff00000" # 1 MB image # end # end device pci 13.0 on end # USB Modified: trunk/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -99,7 +99,6 @@ device pci 1.0 on # Onboard Video #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end chip southbridge/intel/i82801xx # Southbridge @@ -109,7 +108,6 @@ device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1f.0 on # ISA/LPC? Bridge Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb =================================================================== --- trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -4,7 +4,6 @@ device pci 1.0 on # Onboard Video #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end chip southbridge/intel/i82801xx # Southbridge @@ -14,7 +13,6 @@ device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1f.0 on # ISA/LPC? Bridge Modified: trunk/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -211,7 +211,6 @@ chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - register "rom_address" = "0xfff80000" end end #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) @@ -220,7 +219,6 @@ # end # chip drivers/pci/onboard # device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb =================================================================== --- trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -109,7 +109,6 @@ chip drivers/pci/onboard device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - register "rom_address" = "0xfff80000" end end #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) @@ -118,7 +117,6 @@ # end # chip drivers/pci/onboard # device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -108,7 +108,6 @@ end chip drivers/pci/onboard device pci 14.0 on end # 69000 - register "rom_address" = "0x2000000" end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -7,7 +7,6 @@ end chip drivers/pci/onboard device pci 14.0 on end # 69000 - register "rom_address" = "0x2000000" end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -180,7 +180,6 @@ device pci 1.0 on # AGP bridge chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - register "rom_address" = "0xfff80000" end end device pci 2.0 on # LPC Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -13,7 +13,6 @@ device pci 1.0 on # AGP bridge chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - register "rom_address" = "0xfff80000" end end device pci 2.0 on # LPC Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -78,7 +78,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -9,7 +9,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" Modified: trunk/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -127,7 +127,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/ibm/e326/devicetree.cb =================================================================== --- trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -23,7 +23,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/intel/d945gclf/Config.lb =================================================================== --- trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -152,9 +152,6 @@ device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - # register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -30,9 +30,6 @@ device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - # register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -234,7 +234,6 @@ device pci 1.0 off end #chip drivers/pci/onboard # device pci 6.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1.0 on Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -26,7 +26,6 @@ device pci 1.0 off end #chip drivers/pci/onboard # device pci 6.0 on end - # register "rom_address" = "0xfff80000" #end end device pci 1.0 on Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -155,9 +155,6 @@ # device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -11,9 +11,6 @@ device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller Modified: trunk/src/mainboard/kontron/kt690/Config.lb =================================================================== --- trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -134,7 +134,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,7 +157,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -168,7 +166,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/mitac/6513wu/Config.lb =================================================================== --- trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -82,7 +82,6 @@ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) chip drivers/pci/onboard device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb =================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -28,7 +28,6 @@ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) chip drivers/pci/onboard device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" Modified: trunk/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -77,7 +77,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -28,7 +28,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" Modified: trunk/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -211,7 +211,6 @@ chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - register "rom_address" = "0xfff80000" end #bx_a013+ start #chip drivers/pci/onboard #SATA2 @@ -229,7 +228,6 @@ # end # chip drivers/pci/onboard # device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end end # device pci 18.0 Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -77,7 +77,6 @@ chip drivers/pci/onboard device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - register "rom_address" = "0xfff80000" end #bx_a013+ start #chip drivers/pci/onboard #SATA2 @@ -95,7 +94,6 @@ # end # chip drivers/pci/onboard # device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# register "rom_address" = "0xfff80000" # end end # device pci 18.0 Modified: trunk/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -280,7 +280,6 @@ device pci 6.0 on #P2P chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff80000" end end # P2P device pci 7.0 on end # reserve Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -139,7 +139,6 @@ device pci 6.0 on #P2P chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff80000" end end # P2P device pci 7.0 on end # reserve Modified: trunk/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -78,7 +78,6 @@ device pci 1.0 off # Onboard video # chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" # end end chip southbridge/intel/i82801xx # Southbridge Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb =================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -9,7 +9,6 @@ device pci 1.0 off # Onboard video # chip drivers/pci/onboard # device pci 1.0 on end - # register "rom_address" = "0xfff80000" # end end chip southbridge/intel/i82801xx # Southbridge Modified: trunk/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -77,7 +77,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb =================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -3,7 +3,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -256,8 +256,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -94,8 +94,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -278,8 +278,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -114,8 +114,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -282,8 +282,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -116,8 +116,6 @@ device pci 6.0 on # PCI chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" #for 1M -# register "rom_address" = "0xfff80000" #for 512K end end device pci 6.1 on end # AZA Modified: trunk/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -134,7 +134,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,10 +157,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -171,10 +166,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,10 +22,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -36,10 +31,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -134,7 +134,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,7 +157,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -168,7 +166,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -109,7 +109,6 @@ # end # chip drivers/pci/onboard # device pci 14.0 on end # 69000 -# register "rom_address" = "0x2000000" # end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb =================================================================== --- trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -7,7 +7,6 @@ # end # chip drivers/pci/onboard # device pci 14.0 on end # 69000 -# register "rom_address" = "0x2000000" # end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" Modified: trunk/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -77,7 +77,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb =================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -3,7 +3,6 @@ device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" Modified: trunk/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -121,7 +121,6 @@ #chip drivers/ati/ragexl chip drivers/pci/onboard device pci b.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -19,7 +19,6 @@ #chip drivers/ati/ragexl chip drivers/pci/onboard device pci b.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -125,7 +125,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -23,7 +23,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 5.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -140,7 +140,6 @@ end chip drivers/pci/onboard device pci 6.0 on end #adti - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -38,7 +38,6 @@ end chip drivers/pci/onboard device pci 6.0 on end #adti - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -141,7 +141,6 @@ end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -39,7 +39,6 @@ end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -141,7 +141,6 @@ # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" end chip drivers/pci/onboard device pci 8.0 on end #intel 10/100 Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -39,7 +39,6 @@ # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff00000" end chip drivers/pci/onboard device pci 8.0 on end #intel 10/100 Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -281,7 +281,6 @@ device pci 6.0 on chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff00000" end end # PCI device pci 6.1 off end # AZA Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -114,7 +114,6 @@ device pci 6.0 on chip drivers/pci/onboard device pci 4.0 on end - register "rom_address" = "0xfff00000" end end # PCI device pci 6.1 off end # AZA Modified: trunk/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -135,7 +135,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -38,7 +38,6 @@ device pci 1.0 off end chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end end device pci 1.0 on Modified: trunk/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -134,7 +134,6 @@ #chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 5.0 on end #SiI Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -37,7 +37,6 @@ #chip drivers/ati/ragexl chip drivers/pci/onboard device pci 6.0 on end - register "rom_address" = "0xfff80000" end chip drivers/pci/onboard device pci 5.0 on end #SiI Modified: trunk/src/mainboard/via/vt8454c/Config.lb =================================================================== --- trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 17:11:05 UTC (rev 4923) @@ -123,9 +123,6 @@ device pci 1.0 on # PCI Bridge chip drivers/pci/onboard device pci 0.0 on end - #register "rom_address" = "0xfffc0000" #256k image - register "rom_address" = "0xfff80000" #512k image - #register "rom_address" = "0xfff00000" #1024k image end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb =================================================================== --- trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 17:11:05 UTC (rev 4923) @@ -14,9 +14,6 @@ device pci 1.0 on # PCI Bridge chip drivers/pci/onboard device pci 0.0 on end - #register "rom_address" = "0xfffc0000" #256k image - register "rom_address" = "0xfff80000" #512k image - #register "rom_address" = "0xfff00000" #1024k image end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA Modified: trunk/src/southbridge/amd/rs690/chip.h =================================================================== --- trunk/src/southbridge/amd/rs690/chip.h 2009-11-06 17:09:11 UTC (rev 4922) +++ trunk/src/southbridge/amd/rs690/chip.h 2009-11-06 17:11:05 UTC (rev 4923) @@ -23,7 +23,6 @@ /* Member variables are defined in Config.lb. */ struct southbridge_amd_rs690_config { - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */

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coreboot November 2009