coreboot November 2009

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[v2] r4922 - in trunk/src/drivers: . pci pci/onboard
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 17:09:11 +0000 (Fri, 06 Nov 2009) New Revision: 4922 Added: trunk/src/drivers/pci/ trunk/src/drivers/pci/Makefile.inc trunk/src/drivers/pci/onboard/ trunk/src/drivers/pci/onboard/Config.lb trunk/src/drivers/pci/onboard/Makefile.inc trunk/src/drivers/pci/onboard/chip.h trunk/src/drivers/pci/onboard/onboard.c Log: Revert the deletion of drivers/pci/onboard that snuck in ahead of its time. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/src/drivers/pci/Makefile.inc =================================================================== --- trunk/src/drivers/pci/Makefile.inc (rev 0) +++ trunk/src/drivers/pci/Makefile.inc 2009-11-06 17:09:11 UTC (rev 4922) @@ -0,0 +1 @@ +subdirs-y += onboard Added: trunk/src/drivers/pci/onboard/Config.lb =================================================================== --- trunk/src/drivers/pci/onboard/Config.lb (rev 0) +++ trunk/src/drivers/pci/onboard/Config.lb 2009-11-06 17:09:11 UTC (rev 4922) @@ -0,0 +1,4 @@ +config chip.h + +object onboard.o + Added: trunk/src/drivers/pci/onboard/Makefile.inc =================================================================== --- trunk/src/drivers/pci/onboard/Makefile.inc (rev 0) +++ trunk/src/drivers/pci/onboard/Makefile.inc 2009-11-06 17:09:11 UTC (rev 4922) @@ -0,0 +1 @@ +obj-y += onboard.o Added: trunk/src/drivers/pci/onboard/chip.h =================================================================== --- trunk/src/drivers/pci/onboard/chip.h (rev 0) +++ trunk/src/drivers/pci/onboard/chip.h 2009-11-06 17:09:11 UTC (rev 4922) @@ -0,0 +1,11 @@ +#ifndef PCI_ONBOARD_H +#define PCI_ONBOARD_H + +struct drivers_pci_onboard_config +{ + unsigned long rom_address; +}; +struct chip_operations; +extern struct chip_operations drivers_pci_onboard_ops; + +#endif Added: trunk/src/drivers/pci/onboard/onboard.c =================================================================== --- trunk/src/drivers/pci/onboard/onboard.c (rev 0) +++ trunk/src/drivers/pci/onboard/onboard.c 2009-11-06 17:09:11 UTC (rev 4922) @@ -0,0 +1,78 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu(a)tyan.com + */ + +#include <console/console.h> + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +/* + * How to use the onboard device driver for option rom execution: + * + * 1. You need to add the driver to your mainboard Config.lb: + * + * chip drivers/pci/onboard + * device pci x.0 on end + * register "rom_address" = "0xfff80000" + * end + * 2. Reduce the size of your normal (or fallback) image, by adding the + * following lines to your target Config.lb, after romimage "normal" + * # 48K for SCSI FW or ATI ROM + * option CONFIG_ROM_SIZE = 512*1024-48*1024 + * 3. Create your vgabios.bin, for example using awardeco and put it in the + * directory of your target Config.lb. You can also read an option rom from + * a running system, but this is unreliable, as some option roms are changed + * during execution: + * # dd if=/dev/mem of=atix.rom skip=1536 count=96 + * 4. After you built coreboot.rom, attach the option rom to your coreboot + * image: + * # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom + * + * Alternatively you can use the following script "nsxv" to build your image + * Usage: + * # ./nsxv s2850 + * + * #!/bin/bash + * MBVENDOR=tyan + * MBMODEL=$1 + * LBROOT=/home/yhlu/xx/xx + * + * echo $1 + * date + * + * cd "$LBROOT/freebios2/targets" + * rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL" + * ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt" + * cd "$MBVENDOR/$MBMODEL/$MBMODEL" + * #make clean + * eval make &> "$LBROOT/x_m.txt" + * if [ $? -eq 0 ]; then + * echo "ok." + * else + * echo "FAILED! Log excerpt:" + * tail -n 15 "$LBROOT/x_m.txt" + * exit + * fi + * cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom" + * cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/ + * + * date + * + */ + +static void onboard_enable(device_t dev) +{ + struct drivers_pci_onboard_config *conf; + conf = dev->chip_info; + dev->rom_address = conf->rom_address; +} + +struct chip_operations drivers_pci_onboard_ops = { + CHIP_NAME("Onboard PCI") + .enable_dev = onboard_enable, +};

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[v2] r4921 - in trunk/src: arch/i386/include/arch arch/i386/lib cpu/amd/dualcore cpu/amd/microcode cpu/amd/model_10xxx cpu/amd/quadcore cpu/x86/smm drivers include include/cpu/amd include/cpu/x86 lib mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama mainboard/asus/a8n_e mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/broadcom/blast mainboard/dell/s1850 mainboard/gigabyte/ga_2761gxdk mainboard/gigaby
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 17:02:51 +0000 (Fri, 06 Nov 2009) New Revision: 4921 Removed: trunk/src/drivers/pci/ Modified: trunk/src/arch/i386/include/arch/cpu.h trunk/src/arch/i386/include/arch/hlt.h trunk/src/arch/i386/include/arch/io.h trunk/src/arch/i386/lib/console_print.c trunk/src/cpu/amd/dualcore/dualcore_id.c trunk/src/cpu/amd/microcode/microcode.c trunk/src/cpu/amd/model_10xxx/apic_timer.c trunk/src/cpu/amd/model_10xxx/update_microcode.c trunk/src/cpu/amd/quadcore/quadcore_id.c trunk/src/cpu/x86/smm/smmrelocate.S trunk/src/include/assert.h trunk/src/include/cpu/amd/dualcore.h trunk/src/include/cpu/amd/model_fxx_rev.h trunk/src/include/cpu/amd/mtrr.h trunk/src/include/cpu/amd/quadcore.h trunk/src/include/cpu/x86/cache.h trunk/src/include/cpu/x86/lapic.h trunk/src/include/cpu/x86/msr.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/cpu/x86/tsc.h trunk/src/include/stdlib.h trunk/src/include/string.h trunk/src/lib/cbmem.c trunk/src/lib/usbdebug_direct.c trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c trunk/src/mainboard/dell/s1850/reset.c trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c trunk/src/mainboard/gigabyte/m57sli/apc_auto.c trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c trunk/src/mainboard/intel/d945gclf/auto.c trunk/src/mainboard/intel/eagleheights/auto.c trunk/src/mainboard/intel/eagleheights/reset.c trunk/src/mainboard/intel/jarrell/reset.c trunk/src/mainboard/intel/xe7501devkit/auto.c trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c trunk/src/mainboard/kontron/986lcd-m/auto.c trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c trunk/src/mainboard/msi/ms7260/apc_auto.c trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dme/apc_auto.c trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dmr/apc_auto.c trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c trunk/src/mainboard/supermicro/x6dai_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g/reset.c trunk/src/mainboard/supermicro/x6dhe_g2/reset.c trunk/src/mainboard/supermicro/x6dhr_ig/reset.c trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2895/failover.c trunk/src/mainboard/tyan/s2912/apc_auto.c trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/via/cn700/cn700.h trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c trunk/src/southbridge/amd/cs5530/cs5530.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82801ca/i82801ca.h trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801xx/i82801xx.h Log: Split the two usages of __ROMCC__: __ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/arch/i386/include/arch/cpu.h =================================================================== --- trunk/src/arch/i386/include/arch/cpu.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/cpu.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -104,7 +104,7 @@ #define X86_VENDOR_SIS 10 #define X86_VENDOR_UNKNOWN 0xff -#if !defined( __ROMCC__ ) && defined( __GNUC__) +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) && defined( __GNUC__) #include <device/device.h> Modified: trunk/src/arch/i386/include/arch/hlt.h =================================================================== --- trunk/src/arch/i386/include/arch/hlt.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/hlt.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef ARCH_HLT_H #define ARCH_HLT_H -#if defined( __ROMCC__) && !defined(__GNUC__) +#if defined( __ROMCC__) && !defined(__PRE_RAM__) && !defined(__GNUC__) static void hlt(void) { __builtin_hlt(); Modified: trunk/src/arch/i386/include/arch/io.h =================================================================== --- trunk/src/arch/i386/include/arch/io.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/include/arch/io.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -9,7 +9,7 @@ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" * versions of the single-IO instructions (inb_p/inw_p/..). */ -#if defined( __ROMCC__ ) && !defined (__GNUC__) +#if defined( __ROMCC__ ) && !defined (__GNUC__) static inline void outb(uint8_t value, uint16_t port) { __builtin_outb(value, port); Modified: trunk/src/arch/i386/lib/console_print.c =================================================================== --- trunk/src/arch/i386/lib/console_print.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/arch/i386/lib/console_print.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -66,7 +66,7 @@ * set in some auto.c files to trigger the simple device_t version to be used. * So __GNUCC__ does the right thing here. */ -#if defined (__GNUCC__) +#if defined (__ROMCC__) #define STATIC #else #define STATIC static Modified: trunk/src/cpu/amd/dualcore/dualcore_id.c =================================================================== --- trunk/src/cpu/amd/dualcore/dualcore_id.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/dualcore/dualcore_id.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -2,7 +2,7 @@ #include <arch/cpu.h> #include <cpu/amd/dualcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_fxx_msr.h> #endif Modified: trunk/src/cpu/amd/microcode/microcode.c =================================================================== --- trunk/src/cpu/amd/microcode/microcode.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/microcode/microcode.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <stdint.h> #include <console/console.h> Modified: trunk/src/cpu/amd/model_10xxx/apic_timer.c =================================================================== --- trunk/src/cpu/amd/model_10xxx/apic_timer.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/model_10xxx/apic_timer.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,8 +23,8 @@ #include <cpu/x86/lapic.h> /* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected - * to udelay_tsc(). + * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is + * redirected to udelay_tsc(). */ Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/src/cpu/amd/model_10xxx/update_microcode.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/model_10xxx/update_microcode.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,7 +29,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors Modified: trunk/src/cpu/amd/quadcore/quadcore_id.c =================================================================== --- trunk/src/cpu/amd/quadcore/quadcore_id.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/amd/quadcore/quadcore_id.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ #include <arch/cpu.h> #include <cpu/amd/quadcore.h> -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #include <cpu/amd/model_10xxx_msr.h> #endif Modified: trunk/src/cpu/x86/smm/smmrelocate.S =================================================================== --- trunk/src/cpu/x86/smm/smmrelocate.S 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/cpu/x86/smm/smmrelocate.S 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ #include <arch/asm.h> // Make sure no stage 2 code is included: -#define __ROMCC__ +#define __PRE_RAM__ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? Modified: trunk/src/include/assert.h =================================================================== --- trunk/src/include/assert.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/assert.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -24,7 +24,7 @@ // ROMCC doesn't support __FILE__ or __LINE__ :^{ #if CONFIG_DEBUG -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } #else #define ASSERT(x) { \ @@ -39,7 +39,7 @@ #define ASSERT(x) { } #endif -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #define BUG() { die("BUG encountered: system halted\r\n"); } #else #define BUG() { \ Modified: trunk/src/include/cpu/amd/dualcore.h =================================================================== --- trunk/src/include/cpu/amd/dualcore.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/dualcore.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -15,7 +15,7 @@ struct node_core_id get_node_core_id(unsigned int nb_cfg_54); #endif -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu); Modified: trunk/src/include/cpu/amd/model_fxx_rev.h =================================================================== --- trunk/src/include/cpu/amd/model_fxx_rev.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/model_fxx_rev.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -49,7 +49,7 @@ } -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -96,7 +96,7 @@ return (cpuid_eax(1) & 0xfff0f) < 0x40f02; } -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ //AMD_F0_SUPPORT static int is_cpu_f0_in_bsp(int nodeid) { Modified: trunk/src/include/cpu/amd/mtrr.h =================================================================== --- trunk/src/include/cpu/amd/mtrr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/mtrr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -31,7 +31,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) +#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) void amd_setup_mtrrs(void); #endif /* __ROMCC__ */ Modified: trunk/src/include/cpu/amd/quadcore.h =================================================================== --- trunk/src/include/cpu/amd/quadcore.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/amd/quadcore.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -34,7 +34,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54); #endif -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) struct device; u32 get_apicid_base(u32 ioapic_num); void amd_sibling_init(struct device *cpu); Modified: trunk/src/include/cpu/x86/cache.h =================================================================== --- trunk/src/include/cpu/x86/cache.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/cache.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -41,7 +41,7 @@ wbinvd(); } -#if !defined( __ROMCC__) && defined (__GNUC__) +#if !defined( __ROMCC__) && !defined(__PRE_RAM__) && defined (__GNUC__) void x86_enable_cache(void); #endif /* !__ROMCC__ */ Modified: trunk/src/include/cpu/x86/lapic.h =================================================================== --- trunk/src/include/cpu/x86/lapic.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/lapic.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -68,7 +68,7 @@ } #endif -#if ! defined (__ROMCC__) +#if ! defined (__ROMCC__) && !defined(__PRE_RAM__) #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) @@ -157,6 +157,6 @@ #endif /* CONFIG_SMP */ -#endif /* !__ROMCC__ */ +#endif /* !__ROMCC__ && !__PRE_RAM__ */ #endif /* CPU_X86_LAPIC_H */ Modified: trunk/src/include/cpu/x86/msr.h =================================================================== --- trunk/src/include/cpu/x86/msr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/msr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H -#if defined( __ROMCC__) && !defined (__GNUC__) +#if defined( __ROMCC__) typedef __builtin_msr_t msr_t; @@ -43,7 +43,7 @@ ); } -#endif /* ROMCC__ && !__GNUC__ */ +#endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */ Modified: trunk/src/include/cpu/x86/mtrr.h =================================================================== --- trunk/src/include/cpu/x86/mtrr.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/mtrr.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -32,7 +32,7 @@ #define MTRRfix4K_F8000_MSR 0x26f -#if !defined(__ROMCC__) && !defined (ASSEMBLY) +#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> Modified: trunk/src/include/cpu/x86/tsc.h =================================================================== --- trunk/src/include/cpu/x86/tsc.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/cpu/x86/tsc.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ return res; } -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined (__PRE_RAM__) static inline unsigned long long rdtscll(void) { unsigned long long val; Modified: trunk/src/include/stdlib.h =================================================================== --- trunk/src/include/stdlib.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/stdlib.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -11,7 +11,7 @@ #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) void *malloc(size_t size); void free(void *ptr); #endif Modified: trunk/src/include/string.h =================================================================== --- trunk/src/include/string.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/include/string.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -8,7 +8,7 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif @@ -41,7 +41,7 @@ return 0; } -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) static inline char *strdup(const char *s) { size_t sz = strlen(s) + 1; Modified: trunk/src/lib/cbmem.c =================================================================== --- trunk/src/lib/cbmem.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/lib/cbmem.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -45,7 +45,7 @@ u64 size; } __attribute__((packed)); -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ struct cbmem_entry *bss_cbmem_toc; #endif @@ -64,7 +64,7 @@ struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -91,7 +91,7 @@ cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -102,7 +102,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -158,7 +158,7 @@ { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; @@ -175,7 +175,7 @@ return (void *)NULL; } -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif @@ -199,12 +199,12 @@ cbmem_arch_init(); } -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ void cbmem_list(void) { struct cbmem_entry *cbmem_toc; int i; -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); #else cbmem_toc = bss_cbmem_toc; Modified: trunk/src/lib/usbdebug_direct.c =================================================================== --- trunk/src/lib/usbdebug_direct.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/lib/usbdebug_direct.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ /* * 2006.12.10 yhlu moved it to corbeoot and use struct instead */ -#ifndef __ROMCC__ +#if !defined(__ROMCC__) #include <console/console.h> #else #if CONFIG_USE_PRINTK_IN_CAR==0 Modified: trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 Modified: trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define SYSTEM_TYPE 0 /* SERVER */ //#define SYSTEM_TYPE 1 /* DESKTOP */ Modified: trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ /* Used by it8712f_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) Modified: trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/dell/s1850/reset.c =================================================================== --- trunk/src/mainboard/dell/s1850/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/dell/s1850/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -2,7 +2,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/pci.h> #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/gigabyte/m57sli/apc_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/m57sli/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -26,7 +26,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/intel/d945gclf/auto.c =================================================================== --- trunk/src/mainboard/intel/d945gclf/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/d945gclf/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__ #include <stdint.h> #include <string.h> @@ -220,10 +220,10 @@ #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" Modified: trunk/src/mainboard/intel/eagleheights/auto.c =================================================================== --- trunk/src/mainboard/intel/eagleheights/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/eagleheights/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ * MA 02110-1301 USA */ -#define __ROMCC__ +#define __PRE_RAM__ #include <delay.h> Modified: trunk/src/mainboard/intel/eagleheights/reset.c =================================================================== --- trunk/src/mainboard/intel/eagleheights/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/eagleheights/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -22,7 +22,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/intel/jarrell/reset.c =================================================================== --- trunk/src/mainboard/intel/jarrell/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/jarrell/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/intel/xe7501devkit/auto.c =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/intel/xe7501devkit/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,4 +1,5 @@ #define ASSEMBLY 1 +#define __PRE_RAM__ #include <stdint.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/kontron/986lcd-m/auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,8 +19,8 @@ * MA 02110-1301 USA */ -// __ROMCC__ means: use "unsigned" for device, not a struct. -#define __ROMCC__ +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__ #include <stdint.h> #include <string.h> @@ -359,10 +359,10 @@ #include <cbmem.h> // Now, this needs to be included because it relies on the symbol -// __ROMCC_ being set during CAR stage (in order to compile the +// __PRE_RAM__ being set during CAR stage (in order to compile the // BSS free versions of the functions). Either rewrite the code // to be always BSS free, or invent a flag that's better suited than -// __ROMCC__ to determine whether we're in ram init stage (stage 1) +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" Modified: trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/kontron/kt690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 Modified: trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1) Modified: trunk/src/mainboard/msi/ms7260/apc_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7260/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7260/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ // #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define DEBUG_SMBUS 1 Modified: trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -24,7 +24,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -4,7 +4,7 @@ * Additional (C) 2007 coresystems GmbH */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c =================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/nvidia/l1_2pvv/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define K8_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/supermicro/h8dme/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dme/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dme/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/supermicro/h8dmr/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/supermicro/x6dai_g/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dai_g/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/supermicro/x6dhe_g/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhe_g/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/supermicro/x6dhe_g2/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhe_g2/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/supermicro/x6dhr_ig/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhr_ig/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/reset.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 Modified: trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 Modified: trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ //used by raminit #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define K8_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/tyan/s2895/failover.c =================================================================== --- trunk/src/mainboard/tyan/s2895/failover.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2895/failover.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s2912/apc_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912_fam10/apc_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -20,7 +20,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 Modified: trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,5 +1,5 @@ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -23,7 +23,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h =================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -956,7 +956,7 @@ #include "amdfam10_nums.h" -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ #if NODE_NUMS==64 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else @@ -1086,7 +1086,7 @@ #if CONFIG_AMDMCT == 0 -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #endif static void wait_all_core0_mem_trained(struct sys_info *sysinfo) @@ -1131,7 +1131,7 @@ } for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -1148,7 +1148,7 @@ } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\n"); soft_reset(); #else Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c =================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) typedef struct sys_info sys_info_conf_t; #else typedef struct amdfam10_sysconf_t sys_info_conf_t; @@ -32,7 +32,7 @@ { device_t dev; struct dram_base_mask_t d; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); #else dev = __f1_dev[0]; @@ -88,7 +88,7 @@ #endif for(i=0;i<nodes;i++) { -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -108,7 +108,7 @@ #endif } -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -122,7 +122,7 @@ static void set_DctSelBaseAddr(u32 i, u32 sel_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -139,7 +139,7 @@ static u32 get_DctSelBaseAddr(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -156,7 +156,7 @@ static void set_DctSelHiEn(u32 i, u32 val) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -172,7 +172,7 @@ static u32 get_DctSelHiEn(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -187,7 +187,7 @@ static void set_DctSelBaseOffset(u32 i, u32 sel_off_m) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -203,7 +203,7 @@ static u32 get_DctSelBaseOffset(u32 i) { device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 2); #else dev = __f2_dev[i]; @@ -264,7 +264,7 @@ d = get_dram_base_mask(i); d.mask += (carry_over>>9); set_dram_base_mask(i,d, nodes); -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -330,7 +330,7 @@ index_max = busn_max>>2; dest_max = busn_max - (index_max<<2); // three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(nodeid, 1); #else dev = __f1_dev[nodeid]; @@ -393,7 +393,7 @@ #endif tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -433,7 +433,7 @@ if(ht_c_index<4) { #endif for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -480,7 +480,7 @@ } #endif -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { @@ -494,7 +494,7 @@ /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -503,7 +503,7 @@ } tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -546,7 +546,7 @@ #endif /* io range allocation */ for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -584,7 +584,7 @@ for(ht_c_index=1;ht_c_index<4; ht_c_index++) { u32 i; for(i=0; i<nodes; i++) { - #if defined(__ROMCC__) + #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); #else dev = __f1_dev[i]; @@ -664,7 +664,7 @@ u32 dword; device_t dev; -#if defined(__ROMCC__) +#if defined(__PRE_RAM__) dev = NODE_PCI(node, 0); #else dev = __f0_dev[node]; @@ -677,7 +677,7 @@ #endif } -#if !defined(__ROMCC__) +#if !defined(__PRE_RAM__) static u32 get_io_addr_index(u32 nodeid, u32 linkn) { u32 index; Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h =================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -518,7 +518,7 @@ uint32_t sbbusn; } __attribute__((packed)); -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ static void soft_reset(void); #else void hard_reset(void); @@ -562,7 +562,7 @@ } for(i=0; i<sysinfo->nodes; i++) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); #else printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); @@ -579,7 +579,7 @@ } } if(needs_reset) { -#ifdef __ROMCC__ +#ifdef __PRE_RAM__ print_debug("mem trained failed\r\n"); soft_reset(); #else Modified: trunk/src/northbridge/via/cn700/cn700.h =================================================================== --- trunk/src/northbridge/via/cn700/cn700.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/via/cn700/cn700.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __ROMCC__ +#if !defined (__ROMCC__) && !defined (__PRE_RAM__) static void cn700_noop() { } Modified: trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c =================================================================== --- trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/northbridge/via/vx800/examples/cache_as_ram_auto.c 2009-11-06 17:02:51 UTC (rev 4921) @@ -19,7 +19,7 @@ */ #define ASSEMBLY 1 -#define __ROMCC__ +#define __PRE_RAM__ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 Modified: trunk/src/southbridge/amd/cs5530/cs5530.h =================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/amd/cs5530/cs5530.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H #define SOUTHBRIDGE_AMD_CS5530_CS5530_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void cs5530_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); Modified: trunk/src/southbridge/intel/i82801ca/i82801ca.h =================================================================== --- trunk/src/southbridge/intel/i82801ca/i82801ca.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801ca/i82801ca.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -1,7 +1,7 @@ #ifndef I82801CA_H #define I82801CA_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801ca_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -41,7 +41,7 @@ /* __ROMCC__ is set by auto.c to make sure * none of the stage2 data structures are included. */ -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i82801xx/i82801xx.h =================================================================== --- trunk/src/southbridge/intel/i82801xx/i82801xx.h 2009-11-06 15:31:49 UTC (rev 4920) +++ trunk/src/southbridge/intel/i82801xx/i82801xx.h 2009-11-06 17:02:51 UTC (rev 4921) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H #define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H -#ifndef __ROMCC__ +#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) #include "chip.h" extern void i82801xx_enable(device_t dev); #endif

1 0

[PATCH] fix arima/hdama mptable.c
by Myles Watson 06 Nov '09

06 Nov '09

Fix hard-coded paths and some warnings. This patch enables Hugh to boot successfully every time with gcc 3.4, and most of the time (~29/30) with gcc 4.4. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[v2] r4920 - trunk/src/mainboard/arima/hdama
by svn＠coreboot.org 06 Nov '09

06 Nov '09

Author: myles Date: 2009-11-06 15:31:49 +0000 (Fri, 06 Nov 2009) New Revision: 4920 Modified: trunk/src/mainboard/arima/hdama/mptable.c Log: Remove hard coded bus numbers from arima/hdama mptable code and fix warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/arima/hdama/mptable.c =================================================================== --- trunk/src/mainboard/arima/hdama/mptable.c 2009-11-05 21:02:35 UTC (rev 4919) +++ trunk/src/mainboard/arima/hdama/mptable.c 2009-11-06 15:31:49 UTC (rev 4920) @@ -17,7 +17,7 @@ * Having the proper apicid's in the table so the non-bootstrap * processors can be woken up should be enough. Linux-2.6.11 work-around. */ -void smp_write_processors_inorder(struct mp_config_table *mc) +static void smp_write_processors_inorder(struct mp_config_table *mc) { int boot_apic_id; int order_id; @@ -65,7 +65,7 @@ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); if (!dev) { - return 0; + return 0xff; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { uint32_t config_map; @@ -89,25 +89,25 @@ return bus_base; } } - return 0; + return 0xff; } -unsigned max_apicid(void) +static unsigned max_apicid(void) { - unsigned max_apicid; + unsigned max; device_t dev; - max_apicid = 0; + max = 0; for(dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_APIC) continue; - if (dev->path.apic.apic_id > max_apicid) { - max_apicid = dev->path.apic.apic_id; + if (dev->path.apic.apic_id > max) { + max = dev->path.apic.apic_id; } } - return max_apicid; + return max; } -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; @@ -152,9 +152,9 @@ /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { + if (bus_chain_0 == 0xff) { printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; + bus_chain_0 = 0; } /* 8111 */ @@ -165,7 +165,7 @@ bus_isa++; } else { - printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n"); + printk_debug("ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0); bus_8111_1 = 4; bus_isa = 5; @@ -177,7 +177,7 @@ } else { - printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n"); + printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0); bus_8131_1 = 2; } @@ -188,7 +188,7 @@ } else { - printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n"); + printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0); bus_8131_2 = 3; } @@ -318,29 +318,38 @@ return smp_next_mpe_entry(mc); } -void reboot_if_hotswap(void) +static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ device_t dev; uint32_t data; unsigned long htic; int reset; - int i; + unsigned bus_chain_0 = node_link_to_bus(0, 0); + reset = 0; printk_debug("Looking for bad PCIX MHz input\n"); - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); - data = pci_read_config32(dev, 0xa0); - if(!(((data>>16)&0x03)==0x03)) { - reset=1; - printk_debug("Bad PCIX MHz - Reset\n"); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (!dev) + printk_debug("Couldn't find %02x:02.0 \n", bus_chain_0); + else { + data = pci_read_config32(dev, 0xa0); + if(!(((data>>16)&0x03)==0x03)) { + reset=1; + printk_debug("Bad PCIX MHz - Reset\n"); + } } printk_debug("Looking for bad Hot Swap Enable\n"); - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); - data = pci_read_config32(dev, 0x48); - if(data & 0x0c) { - reset=1; - printk_debug("Bad Hot Swap start - Reset\n"); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (!dev) + printk_debug("Couldn't find %02x:01.0 \n", bus_chain_0); + else { + data = pci_read_config32(dev, 0x48); + if(data & 0x0c) { + reset=1; + printk_debug("Bad Hot Swap start - Reset\n"); + } } if(reset) { /* enable cf9 */

1 0

PX10000G aka Pico ITX
by elkton gen 06 Nov '09

06 Nov '09

Hi, I'm doing a project for my car and would like to have a very quick booting system, therefore coreboot would be ideally suited. http://en.wikipedia.org/wiki/Pico-ITX#PX10000G is the device I'm targeting but you don't seem to support this, I would like to add this device, it has: VIA VX700 Chipset (you only support VX800 or CX700) VIA C7-M Processor. VIA VT6106S VIA VT1708A By the looks of it only the CPU is support. So a bit of work to be done... If anybody can point me to any datasheets for these parts and/or a contact at VIA who might be helpful in getting access to the information I require this, would be great. Elkton.

2 1

The filo crashes if the filo and coreboot overlap.
by Zheng Bao 06 Nov '09

06 Nov '09

The filo crashes if the filo and coreboot overlap. Since the CBFS is the must-have feature, my family 10 board crashes when it jumps to filo. I am trying to find out why. I need help. Based on current code, the AMD Family 10 will cause the filo and coreboot overlap in RAM. The overlaps_coreboot() in selfboot.c will return 1. But I am not sure if it will make the system crashes. If anybody explains briefly what happens if they overlap. The coreboot information: CONFIG_RAMBASE=0x00200000 Thie filo information #realelf -l filo.elf Elf file type is EXEC (Executable file) Entry point 0x10008c There are 5 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x0000e0 0x00100000 0x00100000 0x14700 0x39be50 RWE 0x20 LOAD 0x0147e0 0x0049be50 0x0049be50 0x00048 0x00048 RW 0x4 NOTE 0x0000e0 0x00100000 0x00100000 0x0008c 0x0008c R 0x4 NOTE 0x013280 0x001131a0 0x001131a0 0x00030 0x00030 R 0x4 GNU_STACK 0x000000 0x00000000 0x00000000 0x00000 0x00000 RWE 0x4 Section to Segment mapping: Segment Sections... 00 .note .boot .text .rodata .note.pinfo .eh_frame .data .bss 01 .initctx 02 .note 03 .note.pinfo 04 _________________________________________________________________ Windows Live: Friends get your Flickr, Yelp, and Digg updates when they e-mail you. http://www.microsoft.com/middleeast/windows/windowslive/see-it-in-action/so…

5 10

Ubiquiti embedded boards and Atheros chipset
by shane chao 06 Nov '09

06 Nov '09

Hello, Does coreboot have any plans to support Ubiquiti embedded boards such as the Ministation or Litestation2/5? Those board are based on Atheros MIPS processors. Thanks, Shane

2 1

Re: [coreboot] [v2] r4912 - trunk/src/boot
by Peter Stuge 06 Nov '09

06 Nov '09

svn(a)coreboot.org wrote: > If the coreboot and filo overlap, Thank you for fixing this! > Some trailing whitespaces were deleted. Please make whitespace changes in separate commits, so that it is easier to find the actual code changes. If there are both code and whitespace changes on the same line I think that is fine, because the point is to only change the lines where code is changed. Whitespace fixes are trivial and do not need an ack, so they can always be made directly, before or after other changes. Thanks again! :) //Peter

1 0

The Linux report ACPI error since r4915.
by Bao, Zheng 06 Nov '09

06 Nov '09

Does it happen on your board. Output is attached. Zheng ------------- coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov 6 18:42:14 CST 2009 starting... BSP Family_Model: 00100f22 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1022, current patch id = 0x00000000 microcode: patch id to apply = 0x01000095 microcode: updated to patch id = 0x01000095 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03001815 F3xDC: 00005128 Wait all core0s started Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 started ap apicid: cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000231 NNNOOODDDEE EIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000321}}} --------- AmPmmiii scccrtrrooaocccrtooodeddeede:::: 0eeeq1qquuuAiPiivv vaaastllleaeennrntttt edrrre:eevv v 0iii2Addd P ===st a 000xrxx11t1000ed2222:22,, , 0ccc3uuur rrrrrreseenn7nttt8 0_pppaeaattatcccrhhhly _iiidsdd e ===tu p000x(xx00)0000 000000g00e0000t_0000c00p u_rev mmEmAiiicXccrr=rooo0cccx1oood0ddee0e:::f2 p2ppaa.attt ccchhhC PUiiid dd R ttteooov iaaapspppp plllK8yyy _ ==1= 0.000xxx00 0111r00000s000078000909955_5p ormmmi_iiciccrrnroooitcccooodd deee::: uuupppdddaaattteeeddd tttooo pppaaatttccchhh iiiddd === 000xxx000111000000000000999555 sssuuuccccccee essssss sb 7 0cccpp0puuu_SSSeaeeetrttAAlAMMMy_DDDMsMMSSeSRRtR up() ddd ooosbnnne7ee0 0_iiidnnnieiittvt___icfffieiiddsdvvv_iiipoddd_r__aa_apppin(((sissttttaa( aggg)eee1 11))s)b aa7appp00iii_cccidiidded:::vi 000c32e1s_ FpFFIIoIDDDr_VVVIiIIDnDD i ooot(nnn ) AA:APPP S::: M 0B0032u1s Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28ae00c1 0x30015047 FIDVID on BSP, APIC_id: 00 BSP fid = 10500 Wait for AP stage 1: ap_apicid = 1 readback = 1010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 2 readback = 2010501 common_fid(packed) = 10500 Wait for AP stage 1: ap_apicid = 3 readback = 3010501 common_fid(packed) = 10500 common_fid = 10500 FID Change Node:00, F3xD4: c8810f25 End FIDVIDMSR 0xc0010071 0x28ae00c1 0x30015047 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode ...WARM RESET... coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov 6 18:42:14 CST 2009 starting... BSP Family_Model: 00100f22 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1022, current patch id = 0x00000000 microcode: patch id to apply = 0x01000095 microcode: updated to patch id = 0x01000095 success cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 00 00 Exit amd_ht_init() cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c8810f25 F3xD8: 03001815 F3xDC: 00005128 Wait all core0s started Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 started ap apicid: cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000123 NNNOOODDDEE EIIIDDD === 000000 CCCOOORRREEEIIIDDD === 000213}}} --------- APmmmiii cscctrrrooaorcccoootdeddeeed:::: ee0eq1qquuuAiiiPv vvsaaalltlaeeennnrtttt errdr:eeevv v 0 iii2dAdd P s=== t 0 a00xxxr1t11e00022d22:22,,, 0 3cccuuu rrrrrrreese7nnnttt8 0 ppp_aaeaatttccrchlhh y_iiiddds e ===t u p000xx(x0)0000000 0000ge00000t00_00000cpu _rev mEmmiiiAccXc=rrroo0ocxccooo1d0ddeee0::f:2 ppp2a.aattt ccchhhC P Uiiidd d R tttevooo aiaapppsp ppKlllyy8y_ ==1= 0 000.xxx 000111r000s0000070800099905_55p o rmmmiii_ciccrrrnooiotcccoood ddeee::: uuupppdddaaattteeeddd tttooo pppaaatttccchhh iiiddd === 000xxx000111000000000000999555 sssuuucccccceee ssssss s b 7cccppp0uu0u_SSSeeeetattAAArMMlMyDDDMM_MSsSSRRRe t up( ) dddo oonnnseebe7 0 0iiin_nniiidtettv___ffifciiidddevsvv_iiiddpdo___sssrt_ttaaaiggngieee22t2 ( aaa)pppiii ccsciibi7ddd:::0 0 000_13d2e v ices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-18-0 sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x28ae00c1 0x30013047 End FIDVIDMSR 0xc0010071 0x28ae00c1 0x30003007 rs780_htinit cpu_ht_freq=a. rs780_htinit: HT3 mode fill_mem_ctrl() raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=00000003 DIMMPresence: DIMMPresent=00000003 DIMMPresence: RegDIMMPresent=00000000 DIMMPresence: DimmECCPresent=00000000 DIMMPresence: DimmPARPresent=00000000 DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=00000003 DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=00000003 DIMMPresence: DimmDRPresent=00000000 DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000001 DIMMPresence: MAload[0]=00000008 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000001 DIMMPresence: MAload[1]=00000008 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001000 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001000 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000004 SPDGetTCL_D: DIMMAutoSpeed 00000004 SPDGetTCL_D: Status 00001000 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 007dfb35 AutoCycTiming: DramTimingHi 00220300 AutoCycTiming: Status 00001000 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001000 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00004003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00004000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 003fffff StitchMemory: Status 00001000 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001000 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000002 DramTimingLo: val=00000000 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: 5d7dfb35 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00010010 AutoConfig_D: DramConfigHi: 7f48800b AutoConfig: Status 00001000 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000004 4 CH_ODC_CTL: 20113222 4 CH_ADDR_TMG: 00202520 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001000 SPDCalcWidth: ErrStatus 00000090 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 007dfb35 AutoCycTiming: DramTimingHi 00220300 AutoCycTiming: Status 00001000 AutoCycTiming: ErrStatus 00000090 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001000 SPDSetBanks: ErrStatus 00000090 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007ffffe StitchMemory: Status 00001000 StitchMemory: ErrStatus 00000090 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Status 00001000 InterleaveBanks_D: ErrStatus 00000090 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000002 DramTimingLo: val=00000000 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: 5d7dfb35 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 00010010 AutoConfig_D: DramConfigHi: 7f48800b AutoConfig: Status 00001000 AutoConfig: ErrStatus 00000090 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000004 4 CH_ODC_CTL: 20113222 4 CH_ADDR_TMG: 00202520 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 7fffff BottomIO: e00000 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00800000 CPUMemTyping: Bottom32bIO:00800000 CPUMemTyping: Bottom40bIO:00000000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001000 TrainRcvrEn: ErrStatus 00000090 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001200 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001200 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001200 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001200 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000090 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001200 InterleaveNodes_D: ErrStatus 00000090 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001200 InterleaveChannels_D: ErrStatus 00000090 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECCInit 1 ECCInit 2 ECCInit 3 mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf98 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1024000 bytes), entry @ 0x200000 Stage: done loading. Jumping to image. coreboot-2.0.0-r4915M_mahogany_fam10_Fallback Fri Nov 6 18:42:14 CST 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:03.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 0, 0 resources PCI: 00:06.0: enabled 0, 0 resources PCI: 00:07.0: enabled 0, 0 resources PCI: 00:08.0: enabled 0, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PCI: 00:12.0: enabled 1, 0 resources PCI: 00:12.1: enabled 1, 0 resources PCI: 00:12.2: enabled 1, 0 resources PCI: 00:13.0: enabled 1, 0 resources PCI: 00:13.1: enabled 1, 0 resources PCI: 00:13.2: enabled 1, 0 resources PCI: 00:14.5: enabled 1, 0 resources PCI: 00:14.0: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources PCI: 00:14.1: enabled 1, 0 resources PCI: 00:14.2: enabled 1, 0 resources PCI: 00:14.3: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 1, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 1, 3 resources PNP: 002e.6: enabled 1, 1 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:14.4: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:03.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 0, 0 resources PCI: 00:06.0: enabled 0, 0 resources PCI: 00:07.0: enabled 0, 0 resources PCI: 00:08.0: enabled 0, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:11.0: enabled 1, 0 resources PCI: 00:12.0: enabled 1, 0 resources PCI: 00:12.1: enabled 1, 0 resources PCI: 00:12.2: enabled 1, 0 resources PCI: 00:13.0: enabled 1, 0 resources PCI: 00:13.1: enabled 1, 0 resources PCI: 00:13.2: enabled 1, 0 resources PCI: 00:14.5: enabled 1, 0 resources PCI: 00:14.0: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources PCI: 00:14.1: enabled 1, 0 resources PCI: 00:14.2: enabled 1, 0 resources PCI: 00:14.3: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 1, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 1, 3 resources PNP: 002e.6: enabled 1, 1 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:14.4: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Mainboard MAHOGANY Enable. dev=0x00223470 mahogany_enable, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000 mahogany_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000 mahogany_enable: uma size 0x10000000, memory start 0x70000000 PCI: Using configuration type 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled malloc Enter, size 1100, free_mem_ptr 0023a000 malloc 0023a000 CPU: APIC: 01 enabled malloc Enter, size 1100, free_mem_ptr 0023a44c malloc 0023a44c CPU: APIC: 02 enabled malloc Enter, size 1100, free_mem_ptr 0023a898 malloc 0023a898 CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] bus ops PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] ops PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:18.5, bad id 0xffffffff PCI: 00:18.6, bad id 0xffffffff PCI: 00:18.7, bad id 0xffffffff PCI: 00:19.0, bad id 0xffffffff PCI: 00:1a.0, bad id 0xffffffff PCI: 00:1b.0, bad id 0xffffffff PCI: 00:1c.0, bad id 0xffffffff PCI: 00:1d.0, bad id 0xffffffff PCI: 00:1e.0, bad id 0xffffffff PCI: 00:1f.0, bad id 0xffffffff rs780_enable: dev=00225b30, VID_DID=0x96001022 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() addr=e0000000,bus=0,devfn=40 gpp_sb_init nb_dev=0x00225b30, dev=0x00227d90, port=0x00000008 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1022/9600] ops PCI: 00:00.0 [1022/9600] enabled Capability: type 0x08 @ 0xc4 flags: 0x0180 PCI: 00:00.0 count: 000c static_count: 0015 PCI: 00:00.0 [1022/9600] enabled next_unitid: 0015 PCI: 00:14.0 PCI: 00:14.1 PCI: 00:14.2 PCI: 00:14.3 PCI: 00:14.4 HT: Left over static devices. Check your Config.lb PCI: pci_scan_bus for bus 00 rs780_enable: dev=00225b30, VID_DID=0x96001022 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x00225b30, dev=0x00227d90, port=0x00000008 NB_PCI_REG04 = 6. NB_PCI_REG84 = 3000095. NB_PCI_REG4C = 52042. PCI: 00:00.0 [1022/9600] enabled rs780_enable: dev=00225f7c, VID_DID=0x96021022 Bus-0, Dev-1, Fun-0. GC is accessible from now on. Capability: type 0x08 @ 0x44 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0x44 Capability: type 0x08 @ 0x44 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0x44 Capability: type 0x0d @ 0xb0 PCI: 00:01.0 [1022/9602] enabled rs780_enable: dev=002263c8, VID_DID=0x96031022 Bus-0, Dev-2,3, Fun-0. enable=1 rs780_gfx_init, nb_dev=0x00225b30, dev=0x002263c8, port=0x2. rs780_gfx_init step1. rs780_gfx_init step2. misc 28 = 541 rs780_gfx_init step5.9.12.1. rs780_gfx_init step5.9.12.3. rs780_gfx_init step5.9.12.9. PcieLinkTraining port=2:lc current state=4000102 Disabling static device: PCI: 00:02.0 PCI: 00:02.1, bad id 0xffffffff PCI: 00:02.2, bad id 0xffffffff PCI: 00:02.3, bad id 0xffffffff PCI: 00:02.4, bad id 0xffffffff PCI: 00:02.5, bad id 0xffffffff PCI: 00:02.6, bad id 0xffffffff PCI: 00:02.7, bad id 0xffffffff rs780_enable: dev=00226814, VID_DID=0x960b1022 Bus-0, Dev-2,3, Fun-0. enable=1 rs780_gfx_init, nb_dev=0x00225b30, dev=0x00226814, port=0x3. rs780_gfx_init step1. rs780_gfx_init step2. misc 28 = 541 rs780_gfx_init step5.9.12.1. rs780_gfx_init step5.9.12.3. rs780_gfx_init step5.9.12.9. PcieLinkTraining port=3:lc current state=4000102 Disabling static device: PCI: 00:03.0 PCI: 00:03.1, bad id 0xffffffff PCI: 00:03.2, bad id 0xffffffff PCI: 00:03.3, bad id 0xffffffff PCI: 00:03.4, bad id 0xffffffff PCI: 00:03.5, bad id 0xffffffff PCI: 00:03.6, bad id 0xffffffff PCI: 00:03.7, bad id 0xffffffff rs780_enable: dev=00226c60, VID_DID=0x96041022 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x00225b30, dev=0x00226c60, port=0x00000004 PcieLinkTraining port=4:lc current state=10203 PcieTrainPort port=0x4 result=0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:04.0 subordinate bus PCI Express PCI: 00:04.0 [1022/9604] enabled rs780_enable: dev=002270ac, VID_DID=0x96051022 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 PCI: 00:05.1, bad id 0xffffffff PCI: 00:05.2, bad id 0xffffffff PCI: 00:05.3, bad id 0xffffffff PCI: 00:05.4, bad id 0xffffffff PCI: 00:05.5, bad id 0xffffffff PCI: 00:05.6, bad id 0xffffffff PCI: 00:05.7, bad id 0xffffffff rs780_enable: dev=002274f8, VID_DID=0x96061022 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 PCI: 00:06.1, bad id 0xffffffff PCI: 00:06.2, bad id 0xffffffff PCI: 00:06.3, bad id 0xffffffff PCI: 00:06.4, bad id 0xffffffff PCI: 00:06.5, bad id 0xffffffff PCI: 00:06.6, bad id 0xffffffff PCI: 00:06.7, bad id 0xffffffff rs780_enable: dev=00227944, VID_DID=0x96071022 Bus-0, Dev-4,5,6,7, Fun-0. enable=0 PCI: 00:07.1, bad id 0xffffffff PCI: 00:07.2, bad id 0xffffffff PCI: 00:07.3, bad id 0xffffffff PCI: 00:07.4, bad id 0xffffffff PCI: 00:07.5, bad id 0xffffffff PCI: 00:07.6, bad id 0xffffffff PCI: 00:07.7, bad id 0xffffffff rs780_enable: dev=00227d90, VID_DID=0xffffffff Bus-0, Dev-8, Fun-0. enable=0 disable_pcie_bar3() PCI: 00:08.1, bad id 0xffffffff PCI: 00:08.2, bad id 0xffffffff PCI: 00:08.3, bad id 0xffffffff PCI: 00:08.4, bad id 0xffffffff PCI: 00:08.5, bad id 0xffffffff PCI: 00:08.6, bad id 0xffffffff PCI: 00:08.7, bad id 0xffffffff rs780_enable: dev=002281dc, VID_DID=0x96081022 Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3() gpp_sb_init nb_dev=0x00225b30, dev=0x002281dc, port=0x00000009 PcieLinkTraining port=9:lc current state=a0b0f10 addr=e0000000,bus=0,devfn=48 PcieTrainPort reg=0x10000 PcieTrainPort port=0x9 result=1 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:09.0 subordinate bus PCI Express PCI: 00:09.0 [1022/9608] enabled rs780_enable: dev=00228628, VID_DID=0x96091022 Bus-0, Dev-9, 10, Fun-0. enable=1 enable_pcie_bar3() gpp_sb_init nb_dev=0x00225b30, dev=0x00228628, port=0x0000000a PcieLinkTraining port=a:lc current state=10203 PcieTrainPort port=0xa result=0 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xb0 Capability: type 0x08 @ 0xb8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:0a.0 subordinate bus PCI Express PCI: 00:0a.0 [1022/9609] enabled PCI: 00:0b.0, bad id 0xffffffff PCI: 00:0c.0, bad id 0xffffffff PCI: 00:0d.0, bad id 0xffffffff PCI: 00:0e.0, bad id 0xffffffff PCI: 00:0f.0, bad id 0xffffffff PCI: 00:10.0, bad id 0xffffffff sb700_enable() PCI: 00:11.0 [1002/4390] ops PCI: 00:11.0 [1002/4390] enabled sb700_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb700_enable() PCI: 00:12.1 [1002/4398] ops PCI: 00:12.1 [1002/4398] enabled sb700_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled PCI: 00:12.3, bad id 0xffffffff PCI: 00:12.4, bad id 0xffffffff PCI: 00:12.5, bad id 0xffffffff PCI: 00:12.6, bad id 0xffffffff PCI: 00:12.7, bad id 0xffffffff sb700_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb700_enable() PCI: 00:13.1 [1002/4398] ops PCI: 00:13.1 [1002/4398] enabled sb700_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled PCI: 00:13.3, bad id 0xffffffff PCI: 00:13.4, bad id 0xffffffff PCI: 00:13.5, bad id 0xffffffff PCI: 00:13.6, bad id 0xffffffff PCI: 00:13.7, bad id 0xffffffff sb700_enable() PCI: 00:14.0 [1002/4385] bus ops PCI: 00:14.0 [1002/4385] enabled sb700_enable() PCI: 00:14.1 [1002/439c] ops PCI: 00:14.1 [1002/439c] enabled sb700_enable() PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled sb700_enable() PCI: 00:14.3 [1002/439d] bus ops PCI: 00:14.3 [1002/439d] enabled sb700_enable() PCI: 00:14.4 [1002/4384] bus ops PCI: 00:14.4 [1002/4384] enabled sb700_enable() PCI: 00:14.5 [1002/4399] ops PCI: 00:14.5 [1002/4399] enabled PCI: 00:14.6, bad id 0xffffffff PCI: 00:14.7, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0, bad id 0xffffffff PCI: 01:01.0, bad id 0xffffffff PCI: 01:02.0, bad id 0xffffffff PCI: 01:03.0, bad id 0xffffffff PCI: 01:04.0, bad id 0xffffffff PCI: 01:05.0 [1002/9615] ops rs780_internal_gfx_enable dev = 0x00228a78, nb_dev = 0x00225b30. sysmem = 0_80000000 PCI: 01:05.0 [1002/9615] enabled PCI: 01:06.0, bad id 0xffffffff PCI: 01:07.0, bad id 0xffffffff PCI: 01:08.0, bad id 0xffffffff PCI: 01:09.0, bad id 0xffffffff PCI: 01:0a.0, bad id 0xffffffff PCI: 01:0b.0, bad id 0xffffffff PCI: 01:0c.0, bad id 0xffffffff PCI: 01:0d.0, bad id 0xffffffff PCI: 01:0e.0, bad id 0xffffffff PCI: 01:0f.0, bad id 0xffffffff PCI: 01:10.0, bad id 0xffffffff PCI: 01:11.0, bad id 0xffffffff PCI: 01:12.0, bad id 0xffffffff PCI: 01:13.0, bad id 0xffffffff PCI: 01:14.0, bad id 0xffffffff PCI: 01:15.0, bad id 0xffffffff PCI: 01:16.0, bad id 0xffffffff PCI: 01:17.0, bad id 0xffffffff PCI: 01:18.0, bad id 0xffffffff PCI: 01:19.0, bad id 0xffffffff PCI: 01:1a.0, bad id 0xffffffff PCI: 01:1b.0, bad id 0xffffffff PCI: 01:1c.0, bad id 0xffffffff PCI: 01:1d.0, bad id 0xffffffff PCI: 01:1e.0, bad id 0xffffffff PCI: 01:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 02 PCI: 02:00.0, bad id 0xffffffff PCI: 02:01.0, bad id 0xffffffff PCI: 02:02.0, bad id 0xffffffff PCI: 02:03.0, bad id 0xffffffff PCI: 02:04.0, bad id 0xffffffff PCI: 02:05.0, bad id 0xffffffff PCI: 02:06.0, bad id 0xffffffff PCI: 02:07.0, bad id 0xffffffff PCI: 02:08.0, bad id 0xffffffff PCI: 02:09.0, bad id 0xffffffff PCI: 02:0a.0, bad id 0xffffffff PCI: 02:0b.0, bad id 0xffffffff PCI: 02:0c.0, bad id 0xffffffff PCI: 02:0d.0, bad id 0xffffffff PCI: 02:0e.0, bad id 0xffffffff PCI: 02:0f.0, bad id 0xffffffff PCI: 02:10.0, bad id 0xffffffff PCI: 02:11.0, bad id 0xffffffff PCI: 02:12.0, bad id 0xffffffff PCI: 02:13.0, bad id 0xffffffff PCI: 02:14.0, bad id 0xffffffff PCI: 02:15.0, bad id 0xffffffff PCI: 02:16.0, bad id 0xffffffff PCI: 02:17.0, bad id 0xffffffff PCI: 02:18.0, bad id 0xffffffff PCI: 02:19.0, bad id 0xffffffff PCI: 02:1a.0, bad id 0xffffffff PCI: 02:1b.0, bad id 0xffffffff PCI: 02:1c.0, bad id 0xffffffff PCI: 02:1d.0, bad id 0xffffffff PCI: 02:1e.0, bad id 0xffffffff PCI: 02:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 03 malloc Enter, size 1100, free_mem_ptr 0023ace4 malloc 0023ace4 PCI: 03:00.0 [10ec/8168] enabled PCI: 03:01.0, bad id 0xffffffff PCI: 03:02.0, bad id 0xffffffff PCI: 03:03.0, bad id 0xffffffff PCI: 03:04.0, bad id 0xffffffff PCI: 03:05.0, bad id 0xffffffff PCI: 03:06.0, bad id 0xffffffff PCI: 03:07.0, bad id 0xffffffff PCI: 03:08.0, bad id 0xffffffff PCI: 03:09.0, bad id 0xffffffff PCI: 03:0a.0, bad id 0xffffffff PCI: 03:0b.0, bad id 0xffffffff PCI: 03:0c.0, bad id 0xffffffff PCI: 03:0d.0, bad id 0xffffffff PCI: 03:0e.0, bad id 0xffffffff PCI: 03:0f.0, bad id 0xffffffff PCI: 03:10.0, bad id 0xffffffff PCI: 03:11.0, bad id 0xffffffff PCI: 03:12.0, bad id 0xffffffff PCI: 03:13.0, bad id 0xffffffff PCI: 03:14.0, bad id 0xffffffff PCI: 03:15.0, bad id 0xffffffff PCI: 03:16.0, bad id 0xffffffff PCI: 03:17.0, bad id 0xffffffff PCI: 03:18.0, bad id 0xffffffff PCI: 03:19.0, bad id 0xffffffff PCI: 03:1a.0, bad id 0xffffffff PCI: 03:1b.0, bad id 0xffffffff PCI: 03:1c.0, bad id 0xffffffff PCI: 03:1d.0, bad id 0xffffffff PCI: 03:1e.0, bad id 0xffffffff PCI: 03:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 04 PCI: 04:00.0, bad id 0xffffffff PCI: 04:01.0, bad id 0xffffffff PCI: 04:02.0, bad id 0xffffffff PCI: 04:03.0, bad id 0xffffffff PCI: 04:04.0, bad id 0xffffffff PCI: 04:05.0, bad id 0xffffffff PCI: 04:06.0, bad id 0xffffffff PCI: 04:07.0, bad id 0xffffffff PCI: 04:08.0, bad id 0xffffffff PCI: 04:09.0, bad id 0xffffffff PCI: 04:0a.0, bad id 0xffffffff PCI: 04:0b.0, bad id 0xffffffff PCI: 04:0c.0, bad id 0xffffffff PCI: 04:0d.0, bad id 0xffffffff PCI: 04:0e.0, bad id 0xffffffff PCI: 04:0f.0, bad id 0xffffffff PCI: 04:10.0, bad id 0xffffffff PCI: 04:11.0, bad id 0xffffffff PCI: 04:12.0, bad id 0xffffffff PCI: 04:13.0, bad id 0xffffffff PCI: 04:14.0, bad id 0xffffffff PCI: 04:15.0, bad id 0xffffffff PCI: 04:16.0, bad id 0xffffffff PCI: 04:17.0, bad id 0xffffffff PCI: 04:18.0, bad id 0xffffffff PCI: 04:19.0, bad id 0xffffffff PCI: 04:1a.0, bad id 0xffffffff PCI: 04:1b.0, bad id 0xffffffff PCI: 04:1c.0, bad id 0xffffffff PCI: 04:1d.0, bad id 0xffffffff PCI: 04:1e.0, bad id 0xffffffff PCI: 04:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 scan_static_bus for PCI: 00:14.0 smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled scan_static_bus for PCI: 00:14.0 done scan_static_bus for PCI: 00:14.3 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 disabled PNP: 002e.4 disabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:14.3 done do_pci_scan_bridge for PCI: 00:14.4 PCI: pci_scan_bus for bus 05 PCI: 05:00.0, bad id 0xffffffff PCI: 05:01.0, bad id 0xffffffff PCI: 05:02.0, bad id 0xffffffff PCI: 05:03.0, bad id 0xffffffff PCI: 05:04.0, bad id 0xffffffff PCI: 05:05.0, bad id 0xffffffff PCI: 05:06.0, bad id 0xffffffff PCI: 05:07.0, bad id 0xffffffff PCI: 05:08.0, bad id 0xffffffff PCI: 05:09.0, bad id 0xffffffff PCI: 05:0a.0, bad id 0xffffffff PCI: 05:0b.0, bad id 0xffffffff PCI: 05:0c.0, bad id 0xffffffff PCI: 05:0d.0, bad id 0xffffffff PCI: 05:0e.0, bad id 0xffffffff PCI: 05:0f.0, bad id 0xffffffff PCI: 05:10.0, bad id 0xffffffff PCI: 05:11.0, bad id 0xffffffff PCI: 05:12.0, bad id 0xffffffff PCI: 05:13.0, bad id 0xffffffff PCI: 05:14.0, bad id 0xffffffff PCI: 05:15.0, bad id 0xffffffff PCI: 05:16.0, bad id 0xffffffff PCI: 05:17.0, bad id 0xffffffff PCI: 05:18.0, bad id 0xffffffff PCI: 05:19.0, bad id 0xffffffff PCI: 05:1a.0, bad id 0xffffffff PCI: 05:1b.0, bad id 0xffffffff PCI: 05:1c.0, bad id 0xffffffff PCI: 05:1d.0, bad id 0xffffffff PCI: 05:1e.0, bad id 0xffffffff PCI: 05:1f.0, bad id 0xffffffff PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:05.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC: 02 missing read_resources APIC: 03 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 rs780_gfx_read_resources. PCI: 01:05.0 register 24(ffffffff), read-only ignoring it PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 2 link: 0 PCI: 00:04.0 read_resources bus 2 link: 0 done PCI: 00:09.0 read_resources bus 3 link: 0 PCI: 00:09.0 read_resources bus 3 link: 0 done PCI: 00:0a.0 read_resources bus 4 link: 0 PCI: 00:0a.0 read_resources bus 4 link: 0 done PCI: 00:14.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:14.0 read_resources bus 1 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PNP: 002e.6 missing read_resources PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:14.4 read_resources bus 5 link: 0 PCI: 00:14.4 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI: 00:18.0 read_resources bus 0 link: 3 PCI: 00:18.0 read_resources bus 0 link: 3 done PCI: 00:18.0 read_resources bus 0 link: 4 PCI: 00:18.0 read_resources bus 0 link: 4 done PCI: 00:18.0 read_resources bus 0 link: 5 PCI: 00:18.0 read_resources bus 0 link: 5 done PCI: 00:18.0 read_resources bus 0 link: 6 PCI: 00:18.0 read_resources bus 0 link: 6 done PCI: 00:18.0 read_resources bus 0 link: 7 PCI: 00:18.0 read_resources bus 0 link: 7 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL APIC: 02 links 0 child on link 0 NULL APIC: 03 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 links 8 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b8 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 201 index 1c PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18 PCI: 01:05.0 resource base fff00000 size 100 align 0 gran 0 limit 0 flags c0002200 index 30 PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:04.0 links 1 child on link 0 NULL PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:05.0 links 0 child on link 0 NULL PCI: 00:06.0 links 0 child on link 0 NULL PCI: 00:07.0 links 0 child on link 0 NULL PCI: 00:08.0 links 0 child on link 0 NULL PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 links 0 child on link 0 NULL PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 links 1 child on link 0 NULL PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:11.0 links 0 child on link 0 NULL PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 PCI: 00:12.0 links 0 child on link 0 NULL PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.1 links 0 child on link 0 NULL PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:12.2 links 0 child on link 0 NULL PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:13.0 links 0 child on link 0 NULL PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.1 links 0 child on link 0 NULL PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:13.2 links 0 child on link 0 NULL PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 links 1 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000200 index 74 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 90 I2C: 01:50 links 0 child on link 0 NULL I2C: 01:51 links 0 child on link 0 NULL I2C: 01:52 links 0 child on link 0 NULL I2C: 01:53 links 0 child on link 0 NULL PCI: 00:14.1 links 0 child on link 0 NULL PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:14.2 links 0 child on link 0 NULL PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.4 links 0 child on link 0 NULL PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a links 0 child on link 0 NULL PCI: 00:14.4 links 1 child on link 0 NULL PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 links 0 child on link 0 NULL PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI: 00:18.4 links 0 child on link 0 NULL PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff PCI: 01:05.0 14 * [0x0 - 0xff] io PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0xff] io PCI: 00:09.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 1c * [0x0 - 0xfff] io PCI: 00:09.0 1c * [0x1000 - 0x1fff] io PCI: 00:11.0 20 * [0x2000 - 0x200f] io PCI: 00:14.1 20 * [0x2010 - 0x201f] io PCI: 00:11.0 10 * [0x2020 - 0x2027] io PCI: 00:11.0 18 * [0x2028 - 0x202f] io PCI: 00:14.1 10 * [0x2030 - 0x2037] io PCI: 00:14.1 18 * [0x2038 - 0x203f] io PCI: 00:11.0 14 * [0x2040 - 0x2043] io PCI: 00:11.0 1c * [0x2044 - 0x2047] io PCI: 00:14.1 14 * [0x2048 - 0x204b] io PCI: 00:14.1 1c * [0x204c - 0x204f] io PCI: 00:18.0 compute_resources_io: base: 2050 size: 3000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 10d8 * [0x0 - 0x2fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 01:05.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 03:00.0 20 * [0x0 - 0xffff] prefmem PCI: 00:09.0 compute_resources_prefmem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 24 * [0x0 - 0xfffffff] prefmem PCI: 00:09.0 24 * [0x10000000 - 0x100fffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 10100000 size: 10100000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:05.0 18 * [0x0 - 0xffff] mem PCI: 00:01.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0x1ffff] mem PCI: 03:00.0 18 * [0x20000 - 0x20fff] mem PCI: 00:09.0 compute_resources_mem: base: 21000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 1c * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x100fffff] mem PCI: 00:09.0 20 * [0x10100000 - 0x101fffff] mem PCI: 00:14.2 10 * [0x10200000 - 0x10203fff] mem PCI: 00:12.0 10 * [0x10204000 - 0x10204fff] mem PCI: 00:12.1 10 * [0x10205000 - 0x10205fff] mem PCI: 00:13.0 10 * [0x10206000 - 0x10206fff] mem PCI: 00:13.1 10 * [0x10207000 - 0x10207fff] mem PCI: 00:14.5 10 * [0x10208000 - 0x10208fff] mem PCI: 00:11.0 24 * [0x10209000 - 0x102093ff] mem PCI: 00:12.2 10 * [0x10209400 - 0x102094ff] mem PCI: 00:13.2 10 * [0x10209500 - 0x102095ff] mem PCI: 00:14.3 a0 * [0x10209600 - 0x10209600] mem PCI: 00:18.0 compute_resources_mem: base: 10209601 size: 10300000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 10b8 * [0x0 - 0x102fffff] mem PCI: 00:18.0 10b0 * [0x20000000 - 0x300fffff] prefmem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:05.0 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:11.0 constrain_resources: PCI: 00:12.0 constrain_resources: PCI: 00:12.1 constrain_resources: PCI: 00:12.2 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:13.2 constrain_resources: PCI: 00:14.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PCI: 00:14.1 constrain_resources: PCI: 00:14.2 constrain_resources: PCI: 00:14.3 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.6 skipping PNP: 002e.6@70 fixed resource, size=0! constrain_resources: PCI: 00:14.4 constrain_resources: PCI: 00:14.5 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 constrain_resources: PCI: 00:18.4 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:3000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 10d8 * [0x1000 - 0x3fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 4000 size: 3000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:3000 align:12 gran:12 limit:ffff Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:09.0 1c * [0x2000 - 0x2fff] io Assigned: PCI: 00:11.0 20 * [0x3000 - 0x300f] io Assigned: PCI: 00:14.1 20 * [0x3010 - 0x301f] io Assigned: PCI: 00:11.0 10 * [0x3020 - 0x3027] io Assigned: PCI: 00:11.0 18 * [0x3028 - 0x302f] io Assigned: PCI: 00:14.1 10 * [0x3030 - 0x3037] io Assigned: PCI: 00:14.1 18 * [0x3038 - 0x303f] io Assigned: PCI: 00:11.0 14 * [0x3040 - 0x3043] io Assigned: PCI: 00:11.0 1c * [0x3044 - 0x3047] io Assigned: PCI: 00:14.1 14 * [0x3048 - 0x304b] io Assigned: PCI: 00:14.1 1c * [0x304c - 0x304f] io PCI: 00:18.0 allocate_resources_io: next_base: 3050 size: 3000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 01:05.0 14 * [0x1000 - 0x10ff] io PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:04.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:04.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:09.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 10 * [0x2000 - 0x20ff] io PCI: 00:09.0 allocate_resources_io: next_base: 2100 size: 1000 align: 12 gran: 12 done PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xd02fffff] mem Assigned: PCI: 00:18.0 10b0 * [0xe0000000 - 0xf00fffff] prefmem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:e0000000 size:10100000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:01.0 24 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:09.0 24 * [0xf0000000 - 0xf00fffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: f0100000 size: 10100000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:e0000000 size:10000000 align:28 gran:20 limit:febfffff Assigned: PCI: 01:05.0 10 * [0xe0000000 - 0xefffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: f0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:04.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:04.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 20 * [0xf0000000 - 0xf000ffff] prefmem PCI: 00:09.0 allocate_resources_prefmem: next_base: f0010000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:c0000000 size:10300000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.0 1c * [0xc0000000 - 0xcfffffff] mem Assigned: PCI: 00:01.0 20 * [0xd0000000 - 0xd00fffff] mem Assigned: PCI: 00:09.0 20 * [0xd0100000 - 0xd01fffff] mem Assigned: PCI: 00:14.2 10 * [0xd0200000 - 0xd0203fff] mem Assigned: PCI: 00:12.0 10 * [0xd0204000 - 0xd0204fff] mem Assigned: PCI: 00:12.1 10 * [0xd0205000 - 0xd0205fff] mem Assigned: PCI: 00:13.0 10 * [0xd0206000 - 0xd0206fff] mem Assigned: PCI: 00:13.1 10 * [0xd0207000 - 0xd0207fff] mem Assigned: PCI: 00:14.5 10 * [0xd0208000 - 0xd0208fff] mem Assigned: PCI: 00:11.0 24 * [0xd0209000 - 0xd02093ff] mem Assigned: PCI: 00:12.2 10 * [0xd0209400 - 0xd02094ff] mem Assigned: PCI: 00:13.2 10 * [0xd0209500 - 0xd02095ff] mem Assigned: PCI: 00:14.3 a0 * [0xd0209600 - 0xd0209600] mem PCI: 00:18.0 allocate_resources_mem: next_base: d0209601 size: 10300000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:d0000000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 01:05.0 18 * [0xd0000000 - 0xd000ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: d0010000 size: 100000 align: 20 gran: 20 done PCI: 00:04.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:04.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:09.0 allocate_resources_mem: base:d0100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 30 * [0xd0100000 - 0xd011ffff] mem Assigned: PCI: 03:00.0 18 * [0xd0120000 - 0xd0120fff] mem PCI: 00:09.0 allocate_resources_mem: next_base: d0121000 size: 100000 align: 20 gran: 20 done PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=00300000, basek=00000300, limitk=00000000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 10b0 <- [0x00e0000000 - 0x00f00fffff] size 0x10100000 gran 0x14 prefmem <node 00 link 00> PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00d02fffff] size 0x10300000 gran 0x14 mem <node 00 link 00> PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 00 link 00> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 1c <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c mem64 PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00d0000000 - 0x00d00fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:05.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:05.0 18 <- [0x00d0000000 - 0x00d000ffff] size 0x00010000 gran 0x10 mem PCI: 01:05.0 30 <- [0x00fff00000 - 0x00fff000ff] size 0x00000100 gran 0x00 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:04.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:04.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:09.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:09.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 prefmem PCI: 00:09.0 20 <- [0x00d0100000 - 0x00d01fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 03:00.0 18 <- [0x00d0120000 - 0x00d0120fff] size 0x00001000 gran 0x0c mem64 PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f000ffff] size 0x00010000 gran 0x10 prefmem64 PCI: 03:00.0 30 <- [0x00d0100000 - 0x00d011ffff] size 0x00020000 gran 0x11 romem PCI: 00:09.0 assign_resources, bus 3 link: 0 PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:11.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00d0209000 - 0x00d02093ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00d0204000 - 0x00d0204fff] size 0x00001000 gran 0x0c mem PCI: 00:12.1 10 <- [0x00d0205000 - 0x00d0205fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00d0209400 - 0x00d02094ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00d0206000 - 0x00d0206fff] size 0x00001000 gran 0x0c mem PCI: 00:13.1 10 <- [0x00d0207000 - 0x00d0207fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00d0209500 - 0x00d02095ff] size 0x00000100 gran 0x08 mem ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned ERROR: PCI: 00:14.0 90 io size: 0x0000000010 not assigned PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.0 assign_resources, bus 1 link: 0 PCI: 00:14.1 10 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io PCI: 00:14.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io PCI: 00:14.1 18 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io PCI: 00:14.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io PCI: 00:14.2 10 <- [0x00d0200000 - 0x00d0203fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 a0 <- [0x00d0209600 - 0x00d0209600] size 0x00000001 gran 0x00 mem PCI: 00:14.3 03 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x00 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000067] size 0x00000008 gran 0x03 io PNP: 002e.5 62 <- [0x0000000064 - 0x000000006b] size 0x00000008 gran 0x03 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.6 missing set_resources PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:14.5 10 <- [0x00d0208000 - 0x00d0208fff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 links 1 child on link 0 APIC: 00 APIC: 00 links 0 child on link 0 NULL APIC: 01 links 0 child on link 0 NULL APIC: 02 links 0 child on link 0 NULL APIC: 03 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI: 00:18.0 links 8 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base e0000000 size 10100000 align 28 gran 20 limit febfffff flags 60081200 index 10b0 PCI: 00:18.0 resource base c0000000 size 10300000 align 28 gran 20 limit febfffff flags 60080200 index 10b8 PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit ffff flags 60080100 index 10d8 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags 60000201 index 1c PCI: 00:01.0 links 1 child on link 0 PCI: 01:05.0 PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base d0000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:05.0 links 0 child on link 0 NULL PCI: 01:05.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 01:05.0 resource base d0000000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 18 PCI: 01:05.0 resource base fff00000 size 100 align 0 gran 0 limit 0 flags e0002200 index 30 PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:04.0 links 1 child on link 0 NULL PCI: 00:04.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:05.0 links 0 child on link 0 NULL PCI: 00:06.0 links 0 child on link 0 NULL PCI: 00:07.0 links 0 child on link 0 NULL PCI: 00:08.0 links 0 child on link 0 NULL PCI: 00:09.0 links 1 child on link 0 PCI: 03:00.0 PCI: 00:09.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:09.0 resource base f0000000 size 100000 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:09.0 resource base d0100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 links 0 child on link 0 NULL PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 03:00.0 resource base d0120000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18 PCI: 03:00.0 resource base f0000000 size 10000 align 16 gran 16 limit febfffff flags 60001201 index 20 PCI: 03:00.0 resource base d0100000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 00:0a.0 links 1 child on link 0 NULL PCI: 00:0a.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:0a.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:11.0 links 0 child on link 0 NULL PCI: 00:11.0 resource base 3020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:11.0 resource base 3040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:11.0 resource base 3028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:11.0 resource base 3044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:11.0 resource base 3000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:11.0 resource base d0209000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24 PCI: 00:12.0 links 0 child on link 0 NULL PCI: 00:12.0 resource base d0204000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:12.1 links 0 child on link 0 NULL PCI: 00:12.1 resource base d0205000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:12.2 links 0 child on link 0 NULL PCI: 00:12.2 resource base d0209400 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:13.0 links 0 child on link 0 NULL PCI: 00:13.0 resource base d0206000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:13.1 links 0 child on link 0 NULL PCI: 00:13.1 resource base d0207000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:13.2 links 0 child on link 0 NULL PCI: 00:13.2 resource base d0209500 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:14.0 links 1 child on link 0 I2C: 01:50 PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags 80000200 index 74 PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags 80000100 index 90 I2C: 01:50 links 0 child on link 0 NULL I2C: 01:51 links 0 child on link 0 NULL I2C: 01:52 links 0 child on link 0 NULL I2C: 01:53 links 0 child on link 0 NULL PCI: 00:14.1 links 0 child on link 0 NULL PCI: 00:14.1 resource base 3030 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:14.1 resource base 3048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:14.1 resource base 3038 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:14.1 resource base 304c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:14.1 resource base 3010 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:14.2 links 0 child on link 0 NULL PCI: 00:14.2 resource base d0200000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10 PCI: 00:14.3 links 1 child on link 0 PNP: 002e.0 PCI: 00:14.3 resource base d0209600 size 1 align 0 gran 0 limit febfffff flags 60000200 index a0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags e0000200 index 3 PNP: 002e.0 links 0 child on link 0 NULL PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 links 0 child on link 0 NULL PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.2 links 0 child on link 0 NULL PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 PNP: 002e.3 links 0 child on link 0 NULL PNP: 002e.3 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.3 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.4 links 0 child on link 0 NULL PNP: 002e.5 links 0 child on link 0 NULL PNP: 002e.5 resource base 60 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.6 links 0 child on link 0 NULL PNP: 002e.6 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.7 links 0 child on link 0 NULL PNP: 002e.8 links 0 child on link 0 NULL PNP: 002e.8 resource base 300 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.8 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 links 0 child on link 0 NULL PNP: 002e.9 resource base 220 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 PNP: 002e.a links 0 child on link 0 NULL PCI: 00:14.4 links 1 child on link 0 NULL PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:14.5 links 0 child on link 0 NULL PCI: 00:14.5 resource base d0208000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10 PCI: 00:18.1 links 0 child on link 0 NULL PCI: 00:18.2 links 0 child on link 0 NULL PCI: 00:18.3 links 0 child on link 0 NULL PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 PCI: 00:18.4 links 0 child on link 0 NULL Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:00.0 subsystem <- 1022/2b80 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 01:05.0 subsystem <- 1022/2b80 PCI: 01:05.0 cmd <- 03 PCI: 00:04.0 bridge ctrl <- 0003 PCI: 00:04.0 cmd <- 00 PCI: 00:09.0 bridge ctrl <- 0003 PCI: 00:09.0 cmd <- 07 PCI: 03:00.0 cmd <- 03 PCI: 00:0a.0 bridge ctrl <- 0003 PCI: 00:0a.0 cmd <- 00 PCI: 00:11.0 cmd <- 03 PCI: 00:12.0 subsystem <- 1022/2b80 PCI: 00:12.0 cmd <- 02 PCI: 00:12.1 subsystem <- 1022/2b80 PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 subsystem <- 1022/2b80 PCI: 00:12.2 cmd <- 02 PCI: 00:13.0 subsystem <- 1022/2b80 PCI: 00:13.0 cmd <- 02 PCI: 00:13.1 subsystem <- 1022/2b80 PCI: 00:13.1 cmd <- 02 PCI: 00:13.2 subsystem <- 1022/2b80 PCI: 00:13.2 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/2b80 PCI: 00:14.0 cmd <- 403 PCI: 00:14.1 subsystem <- 1022/2b80 PCI: 00:14.1 cmd <- 01 PCI: 00:14.2 subsystem <- 1022/2b80 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 1022/2b80 PCI: 00:14.3 cmd <- 0f sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000067 sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x0000006b PNP: 002e.6 missing enable_resources PCI: 00:14.4 bridge ctrl <- 0003 PCI: 00:14.4 cmd <- 01 PCI: 00:14.5 subsystem <- 1022/2b80 PCI: 00:14.5 cmd <- 02 PCI: 00:18.1 subsystem <- 1022/2b80 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/2b80 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/2b80 PCI: 00:18.4 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000d000, offset=0x00200000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 100f22 CPU: family 10, model 02, stepping 02 nodeid = 00, coreid = 00 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 2048MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 2, base: 1792MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local apic... apic_id: 0x00 done. CPU model: AMD Phenom(tm)9600 Quad-Core Processor siblings = 03, CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Initializing CPU #1 Startup point 1. Waiting for send to finish... +CPU: vendor AMD device 100f22 Sending STARTUP #2 to 1. After apic_write. CPU: family 10, model 02, stepping 02 Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 01 After Startup. Enabling cache Asserting INIT. Setting fixed MTRRs(0-88) type: UC Waiting for send to finish... +Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Deasserting INIT. Waiting for send to finish... +DONE fixed MTRRs #startup loops: 2. Sending STARTUP #1 to 2. After apic_write. Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Startup point 1. Waiting for send to finish... +ADDRESS_MASK_HIGH=0xffff Sending STARTUP #2 to 2. After apic_write. Setting variable MTRR 1, base: 2048MB, range: 256MB, type WB Initializing CPU #2 ADDRESS_MASK_HIGH=0xffff Startup point 1. Waiting for send to finish... +Setting variable MTRR 2, base: 1792MB, range: 256MB, type UC CPU: vendor AMD device 100f22 After Startup. ADDRESS_MASK_HIGH=0xffff Asserting INIT. DONE variable MTRRs Clear out the extra MTRR's Waiting for send to finish... +call enable_var_mtrr() Leave x86_setup_var_mtrrs CPU: family 10, model 02, stepping 02 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Deasserting INIT. Setting up local apic...Waiting for send to finish... + apic_id: 0x01 done. #startup loops: 2. Sending STARTUP #1 to 3. After apic_write. CPU model: AMD Phenom(tm)9600 Quad-Core Processor Startup point 1. Waiting for send to finish... +siblings = 03, Sending STARTUP #2 to 3. After apic_write. CPU #1 initialized Startup point 1. Waiting for send to finish... +nodeid = 00, coreid = 02 After Startup. Waiting for 2 CPUS to stop Enabling cache Initializing CPU #3 Setting fixed MTRRs(0-88) type: UC CPU: vendor AMD device 100f22 CPU: family 10, model 02, stepping 02 Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM nodeid = 00, coreid = 03 Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Enabling cache Setting fixed MTRRs(0-88) type: UC DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM ADDRESS_MASK_HIGH=0xffff Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM Setting variable MTRR 1, base: 2048MB, range: 256MB, type WB DONE fixed MTRRs ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 2, base: 1792MB, range: 256MB, type UC ADDRESS_MASK_HIGH=0xffff ADDRESS_MASK_HIGH=0xffff Setting variable MTRR 1, base: 2048MB, range: 256MB, type WB DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xffff call enable_var_mtrr() Setting variable MTRR 2, base: 1792MB, range: 256MB, type UC Leave x86_setup_var_mtrrs ADDRESS_MASK_HIGH=0xffff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled DONE variable MTRRs Clear out the extra MTRR's Setting up local apic...call enable_var_mtrr() apic_id: 0x02 done. Leave x86_setup_var_mtrrs CPU model: AMD Phenom(tm)9600 Quad-Core Processor MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled siblings = 03, Setting up local apic...CPU #2 initialized apic_id: 0x03 done. Waiting for 1 CPUS to stop CPU model: AMD Phenom(tm)9600 Quad-Core Processor siblings = 03, CPU #3 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:00.0 init pcie_init in rs780_ht.c PCI: 01:05.0 init internal_gfx_pci_dev_init device=9615, vendor=1002. MEMCLK = 3 NB HT speed = 1c750a60. CPU HT speed = 87f50a60. HT width = 11110020. Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom In cbfs, rom address for PCI: 01:05.0 = fff4db78 On mainboard, rom address for PCI: 01:05.0 = fff4db78 PCI Expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c0 PCI ROM Image, Vendor 1002, Device 9615, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff4db78 to 0xc0000, 0xec00 bytes Executing Initialization Vector... Option ROM Exit Status: 0128 Stack is clean, initialization successfull! PCI: 00:11.0 init sata_bar0=3020 sata_bar1=3040 sata_bar2=3028 sata_bar3=3044 sata_bar4=3000 sata_bar5=d0209000 SATA port 0 status = 13 drive detection done after 0 ms Primary Master device is ready after 1 tries SATA port 1 status = 0 No Primary Slave SATA drive on Slot1 SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 PCI: 00:12.0 init PCI: 00:12.1 init PCI: 00:12.2 init usb2_bar0=d0209400 PCI: 00:13.0 init PCI: 00:13.1 init PCI: 00:13.2 init usb2_bar0=d0209500 PCI: 00:14.5 init PCI: 00:14.0 init sm_init(). lapicid = 0000000000000000 set power on after power fail ++++++++++no set NMI+++++ RTC Init Invalid CMOS LB checksum sm_init() end PCI: 00:14.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780 Check CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000 CBFS: Could not find file pci1002,439c.rom In cbfs, rom address for PCI: 00:14.1 = 00000000 On mainboard, rom address for PCI: 00:14.1 = 0 PCI: 00:14.2 init base = d0200000 codec_mask = 01 codec viddid: 10ec0888 Dev=PCI: 00:14.2 Default viddid=10ec0882 Reading viddid=10ec0888 No verb! PCI: 00:14.3 init PNP: 002e.1 init PNP: 002e.5 init Keyboard init... Keyboard selftest failed ACK: 0xfe PCI: 00:14.4 init PCI: 00:18.1 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780 Check CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000 CBFS: Could not find file pci1022,1201.rom In cbfs, rom address for PCI: 00:18.1 = 00000000 On mainboard, rom address for PCI: 00:18.1 = 0 PCI: 00:18.2 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780 Check CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000 CBFS: Could not find file pci1022,1202.rom In cbfs, rom address for PCI: 00:18.2 = 00000000 On mainboard, rom address for PCI: 00:18.2 = 0 PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:18.4 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780 Check CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000 CBFS: Could not find file pci1022,1204.rom In cbfs, rom address for PCI: 00:18.4 = 00000000 On mainboard, rom address for PCI: 00:18.4 = 0 PCI: 03:00.0 init Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload CBFS: follow chain: fff00000 + 38 + 15a68 + align -> fff15ac0 Check fallback/coreboot_ram CBFS: follow chain: fff15ac0 + 38 + 3801c + align -> fff4db40 Check pci1002,9615.rom CBFS: follow chain: fff4db40 + 38 + ec00 + align -> fff5c780 Check CBFS: follow chain: fff5c780 + 28 + 22838 + align -> fff7f000 CBFS: Could not find file pci10ec,8168.rom In cbfs, rom address for PCI: 03:00.0 = 00000000 On card, rom address for PCI: 03:00.0 = d0100000 PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000 Incorrect Expansion ROM Header Signature 0000 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 4 resources PCI: 00:18.0: enabled 1, 3 resources PCI: 00:00.0: enabled 1, 1 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 01:05.0: enabled 1, 4 resources PCI: 00:02.0: enabled 0, 0 resources PCI: 00:03.0: enabled 0, 0 resources PCI: 00:04.0: enabled 1, 3 resources PCI: 00:05.0: enabled 0, 0 resources PCI: 00:06.0: enabled 0, 0 resources PCI: 00:07.0: enabled 0, 0 resources PCI: 00:08.0: enabled 0, 0 resources PCI: 00:09.0: enabled 1, 3 resources PCI: 00:0a.0: enabled 1, 3 resources PCI: 00:11.0: enabled 1, 6 resources PCI: 00:12.0: enabled 1, 1 resources PCI: 00:12.1: enabled 1, 1 resources PCI: 00:12.2: enabled 1, 1 resources PCI: 00:13.0: enabled 1, 1 resources PCI: 00:13.1: enabled 1, 1 resources PCI: 00:13.2: enabled 1, 1 resources PCI: 00:14.5: enabled 1, 1 resources PCI: 00:14.0: enabled 1, 2 resources I2C: 01:50: enabled 1, 0 resources I2C: 01:51: enabled 1, 0 resources I2C: 01:52: enabled 1, 0 resources I2C: 01:53: enabled 1, 0 resources PCI: 00:14.1: enabled 1, 5 resources PCI: 00:14.2: enabled 1, 1 resources PCI: 00:14.3: enabled 1, 4 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 1, 2 resources PNP: 002e.2: enabled 0, 4 resources PNP: 002e.3: enabled 0, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 1, 3 resources PNP: 002e.6: enabled 1, 1 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 2 resources PNP: 002e.9: enabled 0, 1 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:14.4: enabled 1, 3 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 1 resources PCI: 00:18.4: enabled 1, 0 resources APIC: 01: enabled 1, 0 resources APIC: 02: enabled 1, 0 resources APIC: 03: enabled 1, 0 resources PCI: 03:00.0: enabled 1, 4 resources Initializing CBMEM area to 0x7fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7fff0200...ok High Tables Base is 7fff0000. Writing IRQ routing tables to 0xf0000...done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0x7fff0400...done. PIRQ table: 48 bytes. Wrote the mp table end at: 000f0410 - 000f054c Adding CBMEM entry as no. 3 Wrote the mp table end at: 7fff1410 - 7fff154c MP table: 332 bytes. Adding CBMEM entry as no. 4 ACPI: Writing ACPI tables at 7fff2400... ACPI: * HPET at 7fff24e8 ACPI: added table 1/40 Length now 40 ACPI: * MADT at 7fff2520 ACPI: added table 2/40 Length now 44 ACPI: * SRAT at 7fff2590 SRAT: lapic cpu_index=00, node_id=00, apic_id=00 SRAT: lapic cpu_index=01, node_id=00, apic_id=01 SRAT: lapic cpu_index=02, node_id=00, apic_id=02 SRAT: lapic cpu_index=03, node_id=00, apic_id=03 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001ffd00 ACPI: added table 3/40 Length now 48 ACPI: * SLIT at 7fff2650 ACPI: added table 4/40 Length now 52 ACPI: * SSDT at 7fff2680 ACPI: added table 5/40 Length now 56 ACPI: * SSDT for PState at 7fff2cb5 ACPI: * DSDT at 7fff2cb8 ACPI: * DSDT @ 7fff2cb8 Length 298b ACPI: * FACS at 7fff5648 ACPI: * FADT at 7fff5688 pm_base: 0x0800 ACPI: added table 6/40 Length now 60 ACPI: done. ACPI tables: 13180 bytes. Multiboot Information structure has been written. Adding CBMEM entry as no. 5 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9fde New low_table_end: 0x00000518 Now going to write high coreboot table at 0x7fffe000 rom_table_end = 0x7fffe000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x7fffe000 to 0x80000000 Adding high table area uma_memory_start=0x70000000, uma_memory_size=0x0 Wrote coreboot table at: 7fffe000 - 7fffe8f0 checksum dfec coreboot table: 2288 bytes. 0. FREE SPACE 80000000 00000000 1. GDT 7fff0200 00000200 2. IRQ TABLE 7fff0400 00001000 3. SMP TABLE 7fff1400 00001000 4. ACPI 7fff2400 0000bc00 5. COREBOOT 7fffe000 00002000 Check CBFS header at fff7efe0 magic is 4f524243 Found CBFS header at fff7efe0 Check fallback/payload Got a payload Loading segment from rom address 0xfff00038 parameter section (skipped) Loading segment from rom address 0xfff00054 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023b130 malloc 0023b130 New segment dstaddr 0x100000 memsize 0x1650d0 srcaddr 0xfff000d8 filesize 0x15980 (cleaned up) New segment addr 0x100000 size 0x1650d0 offset 0xfff000d8 filesize 0x15980 Loading segment from rom address 0xfff00070 data (compression=0) malloc Enter, size 36, free_mem_ptr 0023b154 malloc 0023b154 New segment dstaddr 0x2650d0 memsize 0x48 srcaddr 0xfff15a58 filesize 0x48 (cleaned up) New segment addr 0x2650d0 size 0x48 offset 0xfff15a58 filesize 0x48 Loading segment from rom address 0xfff0008c Entry Point 0x0010008c Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000001650d0 filesz: 0x0000000000015980 lb: [0x0000000000200000, 0x00000000002fa000) segment: [0x0000000000100000, 0x0000000000115980, 0x00000000002650d0) malloc Enter, size 36, free_mem_ptr 0023b178 malloc 0023b178 early: [0x0000000000100000, 0x0000000000115980, 0x0000000000200000) bounce: [0x000000006fe0c000, 0x000000006fe0c000, 0x000000006fe710d0) Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000100000 filesz: 0x0000000000015980 lb: [0x0000000000200000, 0x00000000002fa000) Post relocation: addr: 0x0000000000100000 memsz: 0x0000000000100000 filesz: 0x0000000000015980 it's not compressed! [ 0x0000000000100000, 0000000000115980, 0x0000000000200000) <- 00000000fff000d8 Clearing Segment: addr: 0x0000000000115980 memsz: 0x00000000000ea680 dest 00100000, end 00200000, bouncebuffer 6fe0c000 Loading Segment: addr: 0x000000006fe0c000 memsz: 0x00000000000650d0 filesz: 0x0000000000000000 lb: [0x0000000000200000, 0x00000000002fa000) Post relocation: addr: 0x000000006fe0c000 memsz: 0x00000000000650d0 filesz: 0x0000000000000000 Loading Segment: addr: 0x00000000002650d0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 lb: [0x0000000000200000, 0x00000000002fa000) segment: [0x00000000002650d0, 0x0000000000265118, 0x0000000000265118) bounce: [0x000000006fe710d0, 0x000000006fe71118, 0x000000006fe71118) Post relocation: addr: 0x000000006fe710d0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 it's not compressed! [ 0x000000006fe710d0, 000000006fe71118, 0x000000006fe71118) <- 00000000fff15a58 dest 6fe710d0, end 6fe71118, bouncebuffer 6fe0c000 Loaded segments Jumping to boot code at 10008c entry = 0x0010008c lb_start = 0x00200000 lb_size = 0x000fa000 adjust = 0x6fd06000 buffer = 0x6fe0c000 elf_boot_notes = 0x0023174c adjusted_boot_notes = 0x6ff3774c FILO version 0.6.0 (baozheng(a)localhost.localdomain) Fri Oct 30 15:43:32 CST 2009 ERROR: No such CMOS option (boot_devices) menu: hda1:/etc/grub.conf IDE time outreset failed, but slave may existhda: LBA48 250GB: ST3250620NS File not found. FILO 0.6.0 lqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqkx xx xx xx xx xx xx xx xx xx xx xx xmqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq qqqj Use the ^ and v keys to select which entry is highlighted. Press enter to boot the selected OS, 'e' to edit the commands before booting, 'a' to modify the kernel arguments before booting, or 'c' for a command-line. Ubuntu 8.04, kernel 2.6.24-amd2-generic x Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial Ubuntu 8.04, kernel 2.6.27 Ubuntu 8.04, kernel 2.6.27-tilapia Ubuntu 8.04, kernel 2.6.24-amd2-generic (recovery mode) Ubuntu 8.04, memtest86+ The highlighted entry will be booted automatically in 3 seconds. The highlighted entry will be booted automatically in 2 seconds. The highlighted entry will be booted automatically in 1 seconds. Booting 'Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial' root (hd0,0)root arg=(hd0,0)kernel /boot/vmlinuz-2.6.24-amd2-generic root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro console=ttyS0,115200initrd /boot/initrd.img-2.6.24-amd2-generic Booting 'Ubuntu 8.04, kernel 2.6.24-amd2-generic-serial' root (hd0,0) root arg=(hd0,0) kernel /boot/vmlinuz-2.6.24-amd2-generic root=UUID=7bb9e8a5-cbc0-4104-92a3-628 f56924494 ro console=ttyS0,115200 initrd /boot/initrd.img-2.6.24-amd2-generic Booting 'hda1:/boot/vmlinuz-2.6.24-amd2-generic root=UUID=7bb9e8a5-cbc0-4104-92 a3-628f56924494 ro console=ttyS0,115200 initrd=hda1:/boot/initrd.img-2.6.24-amd 2-generic' Found Linux version 2.6.24-amd2-generic (root@forsteri) #1 SMP Tue Jul 15 22:02:29 UTC 2008 bzImage.Loading kernel... okLoading initrd... okJumping to entry point...[ 0.000000] Linux version 2.6.24-amd2-generic (root@forsteri) (gcc version 4.2.3 (Ubuntu 4.2.3-2ubuntu7)) #1 SMP Tue Jul 15 22: 02:29 UTC 2008 (Ubuntu 2.6.24-amd2.2-generic) [ 0.000000] Command line: root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro console=ttyS0,115200 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 0000000000001000 type 16 [ 0.000000] BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) [ 0.000000] BIOS-e820: 00000000000c0000 - 0000000070000000 (usable) [ 0.000000] BIOS-e820: 0000000070000000 - 0000000080000000 (reserved) [ 0.000000] end_pfn_map = 524288 [ 0.000000] DMI not present or invalid. [ 0.000000] ACPI: RSDP signature @ 0xFFFF8100000F0800 checksum 0 [ 0.000000] ACPI: RSDP 000F0800, 0014 (r0 CORE ) [ 0.000000] ACPI: RSDT 7FFF2424, 003C (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: HPET 7FFF24E8, 0038 (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: APIC 7FFF2520, 006C (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: SRAT 7FFF2590, 00C0 (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: SLIT 7FFF2650, 002D (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: SSDT 7FFF2680, 0635 (r1 AMD-FA AMD-ACPI 6040000 INTL 20061109) [ 0.000000] ACPI: FACP 7FFF5688, 00F4 (r1 CORE COREBOOT 0 CORE 0) [ 0.000000] ACPI: DSDT 7FFF2CB8, 298B (r2 AMD MAHOGANY 10001 INTL 20061109) [ 0.000000] ACPI: FACS 7FFF5648, 0040 [ 0.000000] SRAT: PXM 0 -> APIC 0 -> Node 0 [ 0.000000] SRAT: PXM 0 -> APIC 1 -> Node 0 [ 0.000000] SRAT: PXM 0 -> APIC 2 -> Node 0 [ 0.000000] SRAT: PXM 0 -> APIC 3 -> Node 0 [ 0.000000] SRAT: Node 0 PXM 0 0-a0000 [ 0.000000] SRAT: Node 0 PXM 0 0-80000000 [ 0.000000] Bootmem setup node 0 0000000000000000-0000000070000000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 1 -> 4096 [ 0.000000] DMA32 4096 -> 1048576 [ 0.000000] Normal 1048576 -> 1048576 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 1 -> 160 [ 0.000000] 0: 192 -> 458752 [ 0.000000] ATI board detected. Disabling timer routing over 8254. [ 0.000000] ACPI: PM-Timer IO Port: 0x818 [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [ 0.000000] Processor #0 (Bootup-CPU) [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) [ 0.000000] Processor #1 [ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) [ 0.000000] Processor #2 [ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] enabled) [ 0.000000] Processor #3 [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) [ 0.000000] IOAPIC[0]: apic_id 2, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.000000] Setting APIC routing to flat [ 0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000 [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] swsusp: Registered nosave memory region: 00000000000a0000 - 00000000000c0000 [ 0.000000] Allocating PCI resources starting at 88000000 (gap: 80000000:80000000) [ 0.000000] SMP: Allowing 4 CPUs, 0 hotplug CPUs [ 0.000000] PERCPU: Allocating 34656 bytes of per cpu data [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 451239 [ 0.000000] Policy zone: DMA32 [ 0.000000] Kernel command line: root=UUID=7bb9e8a5-cbc0-4104-92a3-628f56924494 ro console=ttyS0,115200 [ 0.000000] Initializing CPU#0 [ 0.000000] PID hash table entries: 4096 (order: 12, 32768 bytes) [ 0.000000] TSC calibrated against PM_TIMER [ 30.808538] Marking TSC unstable due to TSCs unsynchronized [ 30.808539] time.c: Detected 2305.849 MHz processor. [ 30.809256] Console: colour VGA+ 80x25 [ 30.809274] console [ttyS0] enabled [ 31.168194] Checking aperture... [ 31.171423] CPU 0: aperture @ f4000000 size 64 MB [ 31.187758] Memory: 1797284k/1835008k available (2466k kernel code, 37592k reserved, 1313k data, 316k init) [ 31.197502] SLUB: Genslabs=12, HWalign=64, Order=0-1, MinObjects=4, CPUs=4, Nodes=1 [ 31.282464] Calibrating delay using timer specific routine.. 4616.27 BogoMIPS (lpj=9232540) [ 31.290838] Security Framework initialized [ 31.294933] SELinux: Disabled at boot. [ 31.298776] AppArmor: AppArmor initialized [ 31.302867] Failure registering capabilities with primary security module. [ 31.309876] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 31.318149] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) [ 31.325661] Mount-cache hash table entries: 256 [ 31.330294] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) [ 31.337413] CPU: L2 Cache: 512K (64 bytes/line) [ 31.341937] CPU 0/0 -> Node 0 [ 31.344907] CPU: Physical Processor ID: 0 [ 31.348911] CPU: Processor Core ID: 0 [ 31.352596] SMP alternatives: switching to UP code [ 31.357900] Early unpacking initramfs... done [ 31.605568] ACPI: Core revision 20070126 [ 31.610445] ACPI Warning (tbutils-0217): Incorrect checksum in table [DSDT] - 56, should be 15 [20070126] [ 31.620113] ACPI: Looking for DSDT in initramfs... error, file /DSDT.aml not found. [ 31.628694] ACPI Warning (tbutils-0217): Incorrect checksum in table [DSDT] - 56, should be 15 [20070126] [ 31.639376] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b2cc offset 25F0, ignoring [20070126] [ 31.650790] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b2d6 offset 25FA, ignoring [20070126] [ 31.662188] ACPI Error (psloop-0136): Found unknown opcode 38 at AML address ffffc2000030b2dc offset 2600, ignoring [20070126] [ 31.673610] ACPI Error (psloop-0136): Found unknown opcode E8 at AML address ffffc2000030b2e0 offset 2604, ignoring [20070126] [ 31.685022] ACPI Error (psloop-0136): Found unknown opcode F at AML address ffffc2000030b2e4 offset 2608, ignoring [20070126] [ 31.696346] ACPI Error (psloop-0136): Found unknown opcode 4 at AML address ffffc2000030b2e8 offset 260C, ignoring [20070126] [ 31.707669] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b2ec offset 2610, ignoring [20070126] [ 31.719098] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b2ed offset 2611, ignoring [20070126] [ 31.730440] ACPI Error (psloop-0136): Found unknown opcode 38 at AML address ffffc2000030b2ef offset 2613, ignoring [20070126] [ 31.741846] ACPI Error (psloop-0136): Found unknown opcode 2 at AML address ffffc2000030b2f4 offset 2618, ignoring [20070126] [ 31.753178] ACPI Error (psloop-0136): Found unknown opcode B4 at AML address ffffc2000030b2f8 offset 261C, ignoring [20070126] [ 31.764594] ACPI Error (psloop-0136): Found unknown opcode C6 at AML address ffffc2000030b2f9 offset 261D, ignoring [20070126] [ 31.776014] ACPI Error (psloop-0136): Found unknown opcode E8 at AML address ffffc2000030b300 offset 2624, ignoring [20070126] [ 31.787443] ACPI Error (psloop-0136): Found unknown opcode 2 at AML address ffffc2000030b304 offset 2628, ignoring [20070126] [ 31.798783] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b308 offset 262C, ignoring [20070126] [ 31.810103] ACPI Error (psloop-0136): Found unknown opcode 38 at AML address ffffc2000030b30c offset 2630, ignoring [20070126] [ 31.821513] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b310 offset 2634, ignoring [20070126] [ 31.832922] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b311 offset 2635, ignoring [20070126] [ 31.844331] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b312 offset 2636, ignoring [20070126] [ 31.855743] ACPI Error (psloop-0136): Found unknown opcode 22 at AML address ffffc2000030b319 offset 263D, ignoring [20070126] [ 31.867171] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b31a offset 263E, ignoring [20070126] [ 31.878598] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b31c offset 2640, ignoring [20070126] [ 31.890005] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b31d offset 2641, ignoring [20070126] [ 31.901336] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b320 offset 2644, ignoring [20070126] [ 31.912755] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b321 offset 2645, ignoring [20070126] [ 31.924172] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b322 offset 2646, ignoring [20070126] [ 31.935593] ACPI Error (psloop-0136): Found unknown opcode 22 at AML address ffffc2000030b329 offset 264D, ignoring [20070126] [ 31.947021] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b32a offset 264E, ignoring [20070126] [ 31.958448] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b32c offset 2650, ignoring [20070126] [ 31.969854] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b32d offset 2651, ignoring [20070126] [ 31.981180] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b338 offset 265C, ignoring [20070126] [ 31.992599] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b33a offset 265E, ignoring [20070126] [ 32.004009] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b348 offset 266C, ignoring [20070126] [ 32.015435] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b34a offset 266E, ignoring [20070126] [ 32.026862] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b350 offset 2674, ignoring [20070126] [ 32.038276] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b351 offset 2675, ignoring [20070126] [ 32.049694] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b352 offset 2676, ignoring [20070126] [ 32.061114] ACPI Error (psloop-0136): Found unknown opcode 22 at AML address ffffc2000030b359 offset 267D, ignoring [20070126] [ 32.072531] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b35a offset 267E, ignoring [20070126] [ 32.083950] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b35c offset 2680, ignoring [20070126] [ 32.095379] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b35d offset 2681, ignoring [20070126] [ 32.106721] ACPI Error (psloop-0136): Found unknown opcode 2 at AML address ffffc2000030b364 offset 2688, ignoring [20070126] [ 32.118040] ACPI Error (psloop-0136): Found unknown opcode B4 at AML address ffffc2000030b368 offset 268C, ignoring [20070126] [ 32.129449] ACPI Error (psloop-0136): Found unknown opcode C6 at AML address ffffc2000030b369 offset 268D, ignoring [20070126] [ 32.140858] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b36a offset 268E, ignoring [20070126] [ 32.152269] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b370 offset 2694, ignoring [20070126] [ 32.163687] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b371 offset 2695, ignoring [20070126] [ 32.175116] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b372 offset 2696, ignoring [20070126] [ 32.186545] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b378 offset 269C, ignoring [20070126] [ 32.197949] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b37a offset 269E, ignoring [20070126] [ 32.209369] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b380 offset 26A4, ignoring [20070126] [ 32.220785] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b381 offset 26A5, ignoring [20070126] [ 32.232203] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b382 offset 26A6, ignoring [20070126] [ 32.243623] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b388 offset 26AC, ignoring [20070126] [ 32.254967] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b38c offset 26B0, ignoring [20070126] [ 32.266392] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b38d offset 26B1, ignoring [20070126] [ 32.277722] ACPI Error (psloop-0136): Found unknown opcode B4 at AML address ffffc2000030b398 offset 26BC, ignoring [20070126] [ 32.289139] ACPI Error (psloop-0136): Found unknown opcode C6 at AML address ffffc2000030b399 offset 26BD, ignoring [20070126] [ 32.300548] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b39a offset 26BE, ignoring [20070126] [ 32.311960] ACPI Error (psloop-0136): Found unknown opcode E8 at AML address ffffc2000030b3a0 offset 26C4, ignoring [20070126] [ 32.323390] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b3a8 offset 26CC, ignoring [20070126] [ 32.334815] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b3aa offset 26CE, ignoring [20070126] [ 32.346231] ACPI Error (psloop-0136): Found unknown opcode E8 at AML address ffffc2000030b3b0 offset 26D4, ignoring [20070126] [ 32.357646] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b3b4 offset 26D8, ignoring [20070126] [ 32.368972] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b3b8 offset 26DC, ignoring [20070126] [ 32.380304] ACPI Error (psloop-0136): Found unknown opcode 3F at AML address ffffc2000030b3c1 offset 26E5, ignoring [20070126] [ 32.391720] ACPI Error (psloop-0136): Found unknown opcode 23 at AML address ffffc2000030b3c2 offset 26E6, ignoring [20070126] [ 32.403144] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b3c6 offset 26EA, ignoring [20070126] [ 32.414570] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b3cc offset 26F0, ignoring [20070126] [ 32.425967] ACPI Error (psloop-0136): Found unknown opcode 40 at AML address ffffc2000030b3d0 offset 26F4, ignoring [20070126] [ 32.437376] ACPI Error (psloop-0136): Found unknown opcode E1 at AML address ffffc2000030b3d1 offset 26F5, ignoring [20070126] [ 32.448785] ACPI Error (psloop-0136): Found unknown opcode 21 at AML address ffffc2000030b3d2 offset 26F6, ignoring [20070126] [ 32.460197] ACPI Error (psloop-0136): Found unknown opcode 22 at AML address ffffc2000030b3d9 offset 26FD, ignoring [20070126] [ 32.471612] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b3da offset 26FE, ignoring [20070126] [ 32.483044] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b3dc offset 2700, ignoring [20070126] [ 32.494470] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b3dd offset 2701, ignoring [20070126] [ 32.505791] ACPI Error (psloop-0136): Found unknown opcode E8 at AML address ffffc2000030b3e0 offset 2704, ignoring [20070126] [ 32.517208] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b3e4 offset 2708, ignoring [20070126] [ 32.528541] ACPI Error (psloop-0136): Found unknown opcode F8 at AML address ffffc2000030b3ec offset 2710, ignoring [20070126] [ 32.539958] ACPI Error (psloop-0136): Found unknown opcode 3 at AML address ffffc2000030b3ed offset 2711, ignoring [20070126] [ 32.551301] ACPI Error (psloop-0136): Found unknown opcode 20 at AML address ffffc2000030b3f0 offset 2714, ignoring [20070126] [ 32.562736] ACPI Exception (tbxface-0629): AE_AML_NO_OPERAND, While loading namespace from ACPI tables [20070126] [ 32.573022] ACPI: Unable to load the System Description Tables [ 32.619220] Using local APIC timer interrupts. [ 32.667025] Detected 12.531 MHz APIC timer. [ 32.671279] SMP alternatives: switching to SMP code [ 32.676594] Booting processor 1/4 APIC 0x1 [ 32.690947] Initializing CPU#1 [ 32.771197] Calibrating delay using timer specific routine.. 4611.76 BogoMIPS (lpj=9223539) [ 32.771203] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) [ 32.771205] CPU: L2 Cache: 512K (64 bytes/line) [ 32.771207] CPU 1/1 -> Node 0 [ 32.771209] CPU: Physical Processor ID: 0 [ 32.771209] CPU: Processor Core ID: 1 [ 32.771491] AMD Phenom(tm)9600 Quad-Core Processor stepping 02 [ 32.771565] SMP alternatives: switching to SMP code [ 32.816188] Booting processor 2/4 APIC 0x2 [ 32.830545] Initializing CPU#2 [ 32.911170] Calibrating delay using timer specific routine.. 4611.78 BogoMIPS (lpj=9223567) [ 32.911176] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) [ 32.911178] CPU: L2 Cache: 512K (64 bytes/line) [ 32.911180] CPU 2/2 -> Node 0 [ 32.911182] CPU: Physical Processor ID: 0 [ 32.911182] CPU: Processor Core ID: 2 [ 32.911464] AMD Phenom(tm)9600 Quad-Core Processor stepping 02 [ 32.911563] SMP alternatives: switching to SMP code [ 32.956200] Booting processor 3/4 APIC 0x3 [ 32.970563] Initializing CPU#3 [ 33.051143] Calibrating delay using timer specific routine.. 4611.78 BogoMIPS (lpj=9223571) [ 33.051149] CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) [ 33.051151] CPU: L2 Cache: 512K (64 bytes/line) [ 33.051153] CPU 3/3 -> Node 0 [ 33.051155] CPU: Physical Processor ID: 0 [ 33.051155] CPU: Processor Core ID: 3 [ 33.051437] AMD Phenom(tm)9600 Quad-Core Processor stepping 02 [ 33.051547] Brought up 4 CPUs [ 33.094311] net_namespace: 120 bytes [ 33.098243] Time: 9:24:48 Date: 11/06/09 [ 33.102355] NET: Registered protocol family 16 [ 33.106938] PCI: Using configuration type 1 [ 33.111546] ACPI: Interpreter disabled. [ 33.115380] Linux Plug and Play Support v0.97 (c) Adam Belay [ 33.121048] pnp: PnP ACPI: disabled [ 33.124685] PCI: Probing PCI hardware [ 33.128553] pci 0000:00:11.0: set SATA to AHCI mode [ 33.134392] PCI: Transparent bridge - 0000:00:14.4 [ 33.139876] PCI: Using IRQ router default [1022/9602] at 0000:00:01.0 [ 33.155160] NET: Registered protocol family 8 [ 33.159516] NET: Registered protocol family 20 [ 33.164035] AppArmor: AppArmor Filesystem Enabled [ 33.169016] PCI: Bridge: 0000:00:01.0 [ 33.172675] Time: acpi_pm clocksource has been installed. [ 33.178085] IO window: 1000-1fff [ 33.181507] MEM window: d0000000-d00fffff [ 33.185693] PREFETCH window: e0000000-efffffff [ 33.190308] PCI: Bridge: 0000:00:04.0 [ 33.193972] IO window: disabled. [ 33.197370] MEM window: disabled. [ 33.200866] PREFETCH window: disabled. [ 33.204793] PCI: Bridge: 0000:00:09.0 [ 33.208445] IO window: 2000-2fff [ 33.211853] MEM window: d0100000-d01fffff [ 33.216038] PREFETCH window: f0000000-f00fffff [ 33.220654] PCI: Bridge: 0000:00:0a.0 [ 33.224305] IO window: disabled. [ 33.227714] MEM window: disabled. [ 33.231207] PREFETCH window: disabled. [ 33.235130] PCI: Bridge: 0000:00:14.4 [ 33.238794] IO window: disabled. [ 33.242203] MEM window: disabled. [ 33.245693] PREFETCH window: disabled. [ 33.249655] NET: Registered protocol family 2 [ 33.292653] IP route cache hash table entries: 65536 (order: 7, 524288 bytes) [ 33.300351] TCP established hash table entries: 262144 (order: 10, 4194304 bytes) [ 33.309736] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 33.316933] TCP: Hash tables configured (established 262144 bind 65536) [ 33.323536] TCP reno registered [ 33.336701] checking if image is initramfs... it is [ 33.816286] Freeing initrd memory: 7386k freed [ 33.824783] audit: initializing netlink socket (disabled) [ 33.830195] audit(1257499488.265:1): initialized [ 33.836519] VFS: Disk quotas dquot_6.5.1 [ 33.840719] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 33.847291] io scheduler noop registered [ 33.851217] io scheduler anticipatory registered [ 33.855833] io scheduler deadline registered [ 33.860177] io scheduler cfq registered (default) [ 33.865209] assign_interrupt_mode Found MSI capability [ 33.870431] assign_interrupt_mode Found MSI capability [ 33.875648] assign_interrupt_mode Found MSI capability [ 33.900367] Real Time Clock Driver v1.12ac [ 33.904752] Linux agpgart interface v0.102 [ 33.908844] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled [ 33.916768] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 33.922906] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A [ 33.929523] RAMDISK driver initialized: 16 RAM disks of 65536K size 1024 blocksize [ 33.937128] input: Macintosh mouse button emulation as /devices/virtual/input/input0 [ 33.944940] PNP: No PS/2 controller found. Probing ports directly. [ 33.984577] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 34.004456] mice: PS/2 mouse device common for all mice [ 34.009709] cpuidle: using governor ladder [ 34.013807] cpuidle: using governor menu [ 34.017846] NET: Registered protocol family 1 [ 34.022250] registered taskstats version 1 [ 34.026445] Magic number: 1:807:423 [ 34.030203] /root/build/ubuntu/linux-source/linux-source/drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 34.040348] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 34.046343] EDD information not available. [ 34.050439] Freeing unused kernel memory: 316k freed Loading, please wait... Begin: Loading essential drivers... ... [ 34.345531] thermal: Unknown symbol acpi_processor_set_thermal_limit Done. Begin: Running /scripts/init-premount ... udevd[1248]: add_to_rules: unknown key 'TEST' in /etc/udev/rules.d/05-options.rules:6 udevd[1248]: add_to_rules: unknown key 'WAIT_FOR' in /etc/udev/rules.d/60-persistent-storage-tape.rules:17 udevd[1248]: add_to_rules: unknown key 'TEST' in /etc/udev/rules.d/60-persistent-storage.rules:4 udevd[1248]: add_to_rules: unknown key 'TEST' in /etc/udev/rules.d/60-persistent-storage.rules:18 [ 34.498044] SCSI subsystem initialized [ 34.517535] usbcore: registered new interface driver usbfs [ 34.523326] usbcore: registered new interface driver hub [ 34.528983] usbcore: registered new device driver usb [ 34.548593] r8169 Gigabit Ethernet driver 2.2LK loaded [ 34.553987] PCI: No IRQ known for interrupt pin A of device 0000:03:00.0. Probably buggy MP table. [ 34.563605] eth0: RTL8168c/8111c at 0xffffc2000089e000, 00:24:21:39:cb:eb, XID 3c4000c0 IRQ 508 [ 34.574416] PCI: No IRQ known for interrupt pin A of device 0000:00:12.0. Probably buggy MP table. [ 34.583801] ohci_hcd 0000:00:12.0: Found HC with no IRQ. Check BIOS/PCI 0000:00:12.0 setup! [ 34.592556] ohci_hcd 0000:00:12.0: init 0000:00:12.0 fail, -19 [ 34.598696] PCI: No IRQ known for interrupt pin A of device 0000:00:12.1. Probably buggy MP table. [ 34.607976] ohci_hcd 0000:00:12.1: Found HC with no IRQ. Check BIOS/PCI 0000:00:12.1 setup! [ 34.616759] ohci_hcd 0000:00:12.1: init 0000:00:12.1 fail, -19 [ 34.624155] PCI: No IRQ known for interrupt pin A of device 0000:00:13.0. Probably buggy MP table. [ 34.633529] ohci_hcd 0000:00:13.0: Found HC with no IRQ. Check BIOS/PCI 0000:00:13.0 setup! [ 34.642368] ohci_hcd 0000:00:13.0: init 0000:00:13.0 fail, -19 [ 34.648489] PCI: No IRQ known for interrupt pin A of device 0000:00:13.1. Probably buggy MP table. [ 34.657823] ohci_hcd 0000:00:13.1: Found HC with no IRQ. Check BIOS/PCI 0000:00:13.1 setup! [ 34.666563] ohci_hcd 0000:00:13.1: init 0000:00:13.1 fail, -19 [ 34.672723] PCI: No IRQ known for interrupt pin A of device 0000:00:11.0. Probably buggy MP table. [ 34.682189] ahci 0000:00:11.0: controller can't do PMP, turning off CAP_PMP [ 35.692034] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl SATA mode [ 35.700442] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pio slum part [ 35.708667] scsi0 : ahci [ 35.711374] scsi1 : ahci [ 35.714077] scsi2 : ahci [ 35.716789] scsi3 : ahci [ 35.719468] ata1: SATA max UDMA/133 abar m1024@0xd0209000 port 0xd0209100 irq 507 [ 35.727269] ata2: SATA max UDMA/133 abar m1024@0xd0209000 port 0xd0209180 irq 507 [ 35.735025] ata3: SATA max UDMA/133 abar m1024@0xd0209000 port 0xd0209200 irq 507 [ 35.742837] ata4: SATA max UDMA/133 abar m1024@0xd0209000 port 0xd0209280 irq 507 [ 36.223863] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [ 36.273717] ata1.00: ATA-7: ST3250620NS, 3.AEG, max UDMA/133 [ 36.279620] ata1.00: 488397168 sectors, multi 0: LBA48 NCQ (depth 31/32) [ 36.331860] ata1.00: configured for UDMA/133 [ 36.663749] ata2: SATA link down (SStatus 0 SControl 300) [ 36.979668] ata3: SATA link down (SStatus 0 SControl 300) [ 37.296081] ata4: SATA link down (SStatus 0 SControl 300) [ 37.301787] scsi 0:0:0:0: Direct-Access ATA ST3250620NS 3.AE PQ: 0 ANSI: 5 [ 37.310309] PCI: No IRQ known for interrupt pin C of device 0000:00:14.5. Probably buggy MP table. [ 37.319710] ohci_hcd 0000:00:14.5: Found HC with no IRQ. Check BIOS/PCI 0000:00:14.5 setup! [ 37.328578] ohci_hcd 0000:00:14.5: init 0000:00:14.5 fail, -19 [ 37.334792] PCI: No IRQ known for interrupt pin B of device 0000:00:12.2. Probably buggy MP table. [ 37.344141] ehci_hcd 0000:00:12.2: Found HC with no IRQ. Check BIOS/PCI 0000:00:12.2 setup! [ 37.352927] ehci_hcd 0000:00:12.2: init 0000:00:12.2 fail, -19 [ 37.359874] scsi4 : pata_atiixp [ 37.364477] scsi5 : pata_atiixp [ 37.367781] ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x3010 irq 14 [ 37.375075] ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x3018 irq 15 [ 37.382688] Driver 'sd' needs updating - please use bus_type methods [ 37.389403] sd 0:0:0:0: [sda] 488397168 512-byte hardware sectors (250059 MB) [ 37.396940] sd 0:0:0:0: [sda] Write Protect is off [ 37.402041] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 37.411556] sd 0:0:0:0: [sda] 488397168 512-byte hardware sectors (250059 MB) [ 37.419050] sd 0:0:0:0: [sda] Write Protect is off [ 37.424060] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 37.433536] sda: sda1 sda2 < sda5 > [ 37.472526] sd 0:0:0:0: [sda] Attached SCSI disk [ 37.482891] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 37.711268] PCI: No IRQ known for interrupt pin B of device 0000:00:13.2. Probably buggy MP table. [ 37.720635] ehci_hcd 0000:00:13.2: Found HC with no IRQ. Check BIOS/PCI 0000:00:13.2 setup! [ 37.729513] ehci_hcd 0000:00:13.2: init 0000:00:13.2 fail, -19 [ 37.742756] Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 [ 37.749332] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx Done. Begin: Mounting root file system... ... Begin: Running /scripts/local-top ... Done. Begin: Waiting for root file system... ...

2 1

[PATCH] Ron's v3 code ported to v2
by Myles Watson 05 Nov '09

05 Nov '09

This was helpful in figuring out what was going on with arima/hdama. A very similar one could be written for fam10. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

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coreboot November 2009