coreboot November 2009

coreboot@coreboot.org

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[commit] r4930 - trunk/src
by svn＠coreboot.org 09 Nov '09

09 Nov '09

Author: uwe Date: 2009-11-09 17:56:47 +0000 (Mon, 09 Nov 2009) New Revision: 4930 Modified: trunk/src/Kconfig Log: Enable Multiboot table support (for GRUB2) by default. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Robert Millan <rmh.grub(a)aybabtu.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/Kconfig =================================================================== --- trunk/src/Kconfig 2009-11-09 17:18:02 UTC (rev 4929) +++ trunk/src/Kconfig 2009-11-09 17:56:47 UTC (rev 4930) @@ -319,7 +319,7 @@ config MULTIBOOT bool "Generate Multiboot tables (for GRUB2)" - default n + default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES

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[commit] r4929 - trunk/util/cbfstool
by svn＠coreboot.org 09 Nov '09

09 Nov '09

Author: oxygene Date: 2009-11-09 17:18:02 +0000 (Mon, 09 Nov 2009) New Revision: 4929 Modified: trunk/util/cbfstool/cbfstool.c trunk/util/cbfstool/common.c trunk/util/cbfstool/common.h Log: Add a "locate" function cbfstool, which helps you find out a suitable address to put a XIP stage to. Specifically, you pass it the file (to get its filesize), its filename (as the header has a variable length that depends on it), and the granularity requirement it has to fit in (for XIP). The granularity is MTRR-style: when you request 0x10000, cbfstool looks for a suitable place in a 64kb-aligned 64kb block. cbfstool simply prints out a hex value which is the start address of a suitably located free memory block. That value can then be used with cbfs add-stage to store the file in the ROM image. It's a two-step operation (instead of being merged into cbfs add-stage) because the image must be linked twice: First, with some bogus, but safe base address (eg. 0) to figure out the target address (based on file size). Then a second time at the target address. The work flow is: - link file - cbfstool locate - link file again - cbfstool add-stage. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/cbfstool/cbfstool.c =================================================================== --- trunk/util/cbfstool/cbfstool.c 2009-11-09 11:53:41 UTC (rev 4928) +++ trunk/util/cbfstool/cbfstool.c 2009-11-09 17:18:02 UTC (rev 4929) @@ -28,6 +28,7 @@ CMD_ADD_PAYLOAD, CMD_ADD_STAGE, CMD_CREATE, + CMD_LOCATE, CMD_PRINT } cmd_t; @@ -78,8 +79,7 @@ if (argc > 6) { base = strtoul(argv[6], NULL, 0); } - cbfsfile = - create_cbfs_file(cbfsname, filedata, &filesize, type, &base); + cbfsfile = create_cbfs_file(cbfsname, filedata, &filesize, type, &base); if (add_file_to_cbfs(cbfsfile, filesize, base)) return 1; writerom(romname, rom, romsize); @@ -203,6 +203,23 @@ return create_cbfs_image(romname, size, bootblock, align); } +static int cbfs_locate(int argc, char **argv) +{ + char *romname = argv[1]; + if (argc < 6) { + printf("not enough arguments to 'locate'.\n"); + return 1; + } + + const char *file = argv[3]; + uint32_t filesize = getfilesize(file); + const char *filename = argv[4]; + int align = strtoul(argv[5], NULL, 0); + + printf("%x\n", cbfs_find_location(romname, filesize, filename, align)); + return 0; +} + static int cbfs_print(int argc, char **argv) { char *romname = argv[1]; @@ -223,6 +240,7 @@ {CMD_ADD_PAYLOAD, "add-payload", cbfs_add_payload}, {CMD_ADD_STAGE, "add-stage", cbfs_add_stage}, {CMD_CREATE, "create", cbfs_create}, + {CMD_LOCATE, "locate", cbfs_locate}, {CMD_PRINT, "print", cbfs_print} }; @@ -238,6 +256,7 @@ "add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" "add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" "create SIZE BSIZE BOOTBLOCK [ALIGN] Create a ROM file\n" + "locate FILE NAME ALIGN Find a place for a file of that size\n" "print Show the contents of the ROM\n"); } Modified: trunk/util/cbfstool/common.c =================================================================== --- trunk/util/cbfstool/common.c 2009-11-09 11:53:41 UTC (rev 4928) +++ trunk/util/cbfstool/common.c 2009-11-09 17:18:02 UTC (rev 4929) @@ -27,6 +27,16 @@ #define dprintf +uint32_t getfilesize(const char *filename) +{ + uint32_t size; + FILE *file = fopen(filename, "rb"); + fseek(file, 0, SEEK_END); + size = ftell(file); + fclose(file); + return size; +} + void *loadfile(const char *filename, uint32_t * romsize_p, void *content, int place) { @@ -323,3 +333,58 @@ writerom(romfile, romarea, romsize); return 0; } + +static int in_segment(int addr, int size, int gran) +{ + return ((addr & ~(gran - 1)) == ((addr + size) & ~(gran - 1))); +} + +uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, + const char *filename, uint32_t alignment) +{ + void *rom = loadrom(romfile); + int filename_size = strlen(filename); + + int headersize = + sizeof(struct cbfs_file) + ALIGN(filename_size + 1, + 16) + sizeof(struct cbfs_stage); + int totalsize = headersize + filesize; + + uint32_t current = phys_start; + while (current < phys_end) { + if (!cbfs_file_header(current)) { + current += align; + continue; + } + struct cbfs_file *thisfile = + (struct cbfs_file *)phys_to_virt(current); + + uint32_t top = + current + ntohl(thisfile->len) + ntohl(thisfile->offset); + if (((ntohl(thisfile->type) == 0x0) + || (ntohl(thisfile->type) == 0xffffffff)) + && (ntohl(thisfile->len) + ntohl(thisfile->offset) >= + totalsize)) { + if (in_segment + (current + headersize, filesize, alignment)) + return current + headersize; + if ((ALIGN(current, alignment) + filesize < top) + && (ALIGN(current, alignment) - headersize > + current) + && in_segment(ALIGN(current, alignment), filesize, + alignment)) + return ALIGN(current, alignment); + if ((ALIGN(current, alignment) + alignment + filesize < + top) + && (ALIGN(current, alignment) + alignment - + headersize > current) + && in_segment(ALIGN(current, alignment) + alignment, + filesize, alignment)) + return ALIGN(current, alignment) + alignment; + } + current = + ALIGN(current + ntohl(thisfile->len) + + ntohl(thisfile->offset), align); + } + return 0; +} Modified: trunk/util/cbfstool/common.h =================================================================== --- trunk/util/cbfstool/common.h 2009-11-09 11:53:41 UTC (rev 4928) +++ trunk/util/cbfstool/common.h 2009-11-09 17:18:02 UTC (rev 4929) @@ -34,6 +34,7 @@ #define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) +uint32_t getfilesize(const char *filename); void *loadfile(const char *filename, uint32_t * romsize_p, void *content, int place); void *loadrom(const char *filename); @@ -62,4 +63,7 @@ int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location); void print_cbfs_directory(const char *filename); +uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, + const char *filename, uint32_t align); + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

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[PATCH]cbfs locate function
by Patrick Georgi 09 Nov '09

09 Nov '09

Hi, attached patch adds a "locate" function cbfstool, which helps you find out a suitable address to put a XIP stage to. Specifically, you pass it the file (to get its filesize), its filename (as the header has a variable length that depends on it), and the granularity requirement it has to fit in (for XIP). The granularity is MTRR-style: when you request 0x10000, cbfstool looks for a suitable place in a 64kb-aligned 64kb block. cbfstool simply prints out a hex value which is the start address of a suitably located free memory block. That value can then be used with cbfs add-stage to store the file in the ROM image. I need this function for my "newfailover" project, which will push most of the current bootblock code into CBFS (everything but enable_rom). It's a two-step operation (instead of being merged into cbfs add-stage) because the image must be linked twice: First, with some bogus, but safe base address (eg. 0) to figure out the target address (based on file size). Then a second time at the target address. The approximative code flow is: link file, cbfstool locate, link file again, cbfstool add-stage. I'm not quite sure about the failure modes yet, so all it does for now is returning an address of "0" if no suitable place could be found. Maybe returning "1" is a better idea, as "0" is the value used when cbfstool add-stage can freely choose the location. "1" should already lead to an error. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

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GRUB 1.97.1 released
by Robert Millan 09 Nov '09

09 Nov '09

Hi, GNU GRUB version 1.97.1 has been released. GRUB, also known as the GRand Unified Bootloader, is a modular, portable bootloader that supports a number of platforms, including standard BIOS-based PCs, IEEE-1275 platforms (such as the OLPC and some PowerPC/Sparc64 hardware) and coreboot, the free (as in freedom) pre-boot initialization framework. <http://www.gnu.org/software/grub/> This is a bug-fix release for a number of problems (excerpt from NEWS file is attached) that weren't detected in time for GRUB 1.97, including a security fix, misc fixes for GNU/Hurd support, and a number of improvements in documentation and error messages (specially coreboot-related). A source tarball for the new release can be found at: http://alpha.gnu.org/gnu/grub/grub-1.97.1.tar.gz and its GPG detached signature [*]: http://alpha.gnu.org/gnu/grub/grub-1.97.1.tar.gz.sig [*] You can use either of the above signature file to verify that the corresponding file (without the .sig suffix) is intact. First, be sure to download both the .sig file and the corresponding tarball. Then, run a command like this: gpg --verify grub-1.97.1.tar.gz.sig If that command fails because you don't have the required public key, then run this command to import it: gpg --keyserver keys.gnupg.net --recv-keys DEA2C38E and rerun the `gpg --verify' command. This release was bootstrapped with the following tools: Autoconf 2.61 Ruby 1.8.7 GCC 4.4 is the recommended version for building it, although any version starting with 4.1.3 is supported in this release. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

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[commit] r4928 - trunk/src/mainboard/technexion/tim5690
by svn＠coreboot.org 09 Nov '09

09 Nov '09

Author: stepan Date: 2009-11-09 11:53:41 +0000 (Mon, 09 Nov 2009) New Revision: 4928 Added: trunk/src/mainboard/technexion/tim5690/tn_post_code.c trunk/src/mainboard/technexion/tim5690/tn_post_code.h Modified: trunk/src/mainboard/technexion/tim5690/Config.lb trunk/src/mainboard/technexion/tim5690/Makefile.inc trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c trunk/src/mainboard/technexion/tim5690/mainboard.c Log: These are post codes for TIM-5690 LED debug message. Signed-off-by: Libra Li <libra.li(a)technexion.com> Added object reference to Config.lb, too and Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-07 00:45:17 UTC (rev 4927) +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-09 11:53:41 UTC (rev 4928) @@ -30,6 +30,7 @@ ## driver mainboard.o +object tn_post_code.o #dir /drivers/si/3114 Modified: trunk/src/mainboard/technexion/tim5690/Makefile.inc =================================================================== --- trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-11-07 00:45:17 UTC (rev 4927) +++ trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-11-09 11:53:41 UTC (rev 4928) @@ -29,6 +29,9 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o +# This is debug message for products of Technexion. +obj-y += tn_post_code.o + # This is part of the conversion to init-obj and away from included code. initobj-y += crt0.o Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-07 00:45:17 UTC (rev 4927) +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-09 11:53:41 UTC (rev 4928) @@ -100,6 +100,10 @@ #include "cpu/amd/model_fxx/fidvid.c" +#define TECHNEXION_EARLY_SETUP +#include "tn_post_code.c" + + #if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -161,6 +165,8 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + technexion_post_code_init(); + technexion_post_code(LED_MESSAGE_START); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -233,7 +239,11 @@ /* It's the time to set ctrl now; */ printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + technexion_post_code(LED_MESSAGE_RAM); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); rs690_before_pci_init(); Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-07 00:45:17 UTC (rev 4927) +++ trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-09 11:53:41 UTC (rev 4928) @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <../southbridge/amd/sb600/sb600.h> #include "chip.h" +#include "tn_post_code.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ @@ -44,12 +45,18 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) +/* previous + */ +void tim5690_enable(device_t dev); +int add_mainboard_resources(struct lb_memory *mem); + + uint64_t uma_memory_base, uma_memory_size; /* set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; @@ -176,6 +183,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + technexion_post_code(LED_MESSAGE_FINISH); } struct chip_operations mainboard_ops = { Added: trunk/src/mainboard/technexion/tim5690/tn_post_code.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/tn_post_code.c (rev 0) +++ trunk/src/mainboard/technexion/tim5690/tn_post_code.c 2009-11-09 11:53:41 UTC (rev 4928) @@ -0,0 +1,207 @@ + +#ifdef TECHNEXION_EARLY_SETUP + +#include <arch/cpu.h> +#include "southbridge/amd/sb600/sb600.h" + +#else + +#include <device/pci.h> +#include <device/pci_ids.h> + +#endif + +#include "tn_post_code.h" + + +#ifdef TECHNEXION_EARLY_SETUP + +// TechNexion's Post Code Initially. +void technexion_post_code_init(void) +{ + uint8_t reg8_data; + device_t dev=0; + + // SMBus Module and ACPI Block (Device 20, Function 0) + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); + + // LED[bit0]:GPIO0 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1<<7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1<<0)) & ~(1<<4)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit1]:GPIO1 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit2]:GPIO4 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x5e); + reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA + pmio_write(0x5e, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<0); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<0); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit3]:GPIO6 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1<<7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<2); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<2); + pci_write_config8(dev, 0xa9, reg8_data); + // LED[bit4]:GPIO7 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<3); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<3); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit5]:GPIO8 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<4); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<4); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit6]:GPIO10 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xab); + reg8_data = ((reg8_data | (1<<0)) & ~(1<<1)); + pci_write_config8(dev, 0xab, reg8_data); + + // LED[bit7]:GPIO66 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x68); + reg8_data &= ~(1<<5); // 0: GPIO + pmio_write(0x68, reg8_data); + + reg8_data = pci_read_config8(dev, 0x7e); + reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + pci_write_config8(dev, 0x7e, reg8_data); + +} + +#endif + +/* TechNexion's Post Code. + */ +void technexion_post_code(uint8_t udata8) +{ + uint8_t u8_data; + device_t dev=0; + + // SMBus Module and ACPI Block (Device 20, Function 0) +#ifdef TECHNEXION_EARLY_SETUP + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); +#else + dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); +#endif + + udata8 = ~(udata8); + + // LED[bit0]:GPIO0 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x1) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit1]:GPIO1 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x2) { + u8_data |= (1<<1); + } + else { + u8_data &= ~(1<<1); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit2]:GPIO4 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x4) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit3]:GPIO6 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x8) { + u8_data |= (1<<2); + } + else { + u8_data &= ~(1<<2); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit4]:GPIO7 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x10) { + u8_data |= (1<<3); + } + else { + u8_data &= ~(1<<3); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit5]:GPIO8 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x20) { + u8_data |= (1<<4); + } + else { + u8_data &= ~(1<<4); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit6]:GPIO10 + u8_data = pci_read_config8(dev, 0xab); + if (udata8 & 0x40) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0xab, u8_data); + + // LED[bit7]:GPIO66 + u8_data = pci_read_config8(dev, 0x7e); + if (udata8 & 0x80) { + u8_data |= (1<<1); + } + else { + u8_data &= ~(1<<1); + } + pci_write_config8(dev, 0x7e, u8_data); + +} Added: trunk/src/mainboard/technexion/tim5690/tn_post_code.h =================================================================== --- trunk/src/mainboard/technexion/tim5690/tn_post_code.h (rev 0) +++ trunk/src/mainboard/technexion/tim5690/tn_post_code.h 2009-11-09 11:53:41 UTC (rev 4928) @@ -0,0 +1,15 @@ + + +#define LED_MESSAGE_START 0xFF +#define LED_MESSAGE_FINISH 0x99 +#define LED_MESSAGE_RAM 0x01 + + +#ifdef TECHNEXION_EARLY_SETUP + +// TechNexion's Post Code Initially. +void technexion_post_code_init(void); + +#endif + +void technexion_post_code(uint8_t udata8);

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[PATCH] The LED post code for Technexion TIM-5690.
by Libra Li 09 Nov '09

09 Nov '09

Hi, These are post codes for TIM-5690 LED debug message. It's easy show message. Thanks. Signed-off-by: Libra Li <libra.li(a)technexion.com> Index: src/mainboard/technexion/tim5690/Makefile.inc =================================================================== --- src/mainboard/technexion/tim5690/Makefile.inc (revision 4927) +++ src/mainboard/technexion/tim5690/Makefile.inc (working copy) @@ -29,6 +29,9 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o +# This is debug message for products of Technexion. +obj-y += tn_post_code.o + # This is part of the conversion to init-obj and away from included code. initobj-y += crt0.o Index: src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- src/mainboard/technexion/tim5690/cache_as_ram_auto.c (revision 4927) +++ src/mainboard/technexion/tim5690/cache_as_ram_auto.c (working copy) @@ -100,6 +100,10 @@ #include "cpu/amd/model_fxx/fidvid.c" +#define TECHNEXION_EARLY_SETUP +#include "tn_post_code.c" + + #if CONFIG_USE_FALLBACK_IMAGE == 1 #include "northbridge/amd/amdk8/early_ht.c" @@ -161,6 +165,8 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + technexion_post_code_init(); + technexion_post_code(LED_MESSAGE_START); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -233,7 +239,11 @@ /* It's the time to set ctrl now; */ printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + technexion_post_code(LED_MESSAGE_RAM); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); rs690_before_pci_init(); Index: src/mainboard/technexion/tim5690/tn_post_code.c =================================================================== --- src/mainboard/technexion/tim5690/tn_post_code.c (revision 0) +++ src/mainboard/technexion/tim5690/tn_post_code.c (revision 0) @@ -0,0 +1,207 @@ + +#ifdef TECHNEXION_EARLY_SETUP + +#include <arch/cpu.h> +#include "southbridge/amd/sb600/sb600.h" + +#else + +#include <device/pci.h> +#include <device/pci_ids.h> + +#endif + +#include "tn_post_code.h" + + +#ifdef TECHNEXION_EARLY_SETUP + +// TechNexion's Post Code Initially. +void technexion_post_code_init(void) +{ + uint8_t reg8_data; + device_t dev=0; + + // SMBus Module and ACPI Block (Device 20, Function 0) + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); + + // LED[bit0]:GPIO0 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1<<7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1<<0)) & ~(1<<4)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit1]:GPIO1 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit2]:GPIO4 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x5e); + reg8_data &= ~(1<<7); // 0: GPIO if not used by SATA + pmio_write(0x5e, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<0); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<0); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit3]:GPIO6 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1<<7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<2); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<2); + pci_write_config8(dev, 0xa9, reg8_data); + // LED[bit4]:GPIO7 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<3); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<3); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit5]:GPIO8 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1<<4); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1<<4); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit6]:GPIO10 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xab); + reg8_data = ((reg8_data | (1<<0)) & ~(1<<1)); + pci_write_config8(dev, 0xab, reg8_data); + + // LED[bit7]:GPIO66 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x68); + reg8_data &= ~(1<<5); // 0: GPIO + pmio_write(0x68, reg8_data); + + reg8_data = pci_read_config8(dev, 0x7e); + reg8_data = ((reg8_data | (1<<1)) & ~(1<<5)); + pci_write_config8(dev, 0x7e, reg8_data); + +} + +#endif + +/* TechNexion's Post Code. + */ +void technexion_post_code(uint8_t udata8) +{ + uint8_t u8_data; + device_t dev=0; + + // SMBus Module and ACPI Block (Device 20, Function 0) +#ifdef TECHNEXION_EARLY_SETUP + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); +#else + dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); +#endif + + udata8 = ~(udata8); + + // LED[bit0]:GPIO0 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x1) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit1]:GPIO1 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x2) { + u8_data |= (1<<1); + } + else { + u8_data &= ~(1<<1); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit2]:GPIO4 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x4) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit3]:GPIO6 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x8) { + u8_data |= (1<<2); + } + else { + u8_data &= ~(1<<2); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit4]:GPIO7 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x10) { + u8_data |= (1<<3); + } + else { + u8_data &= ~(1<<3); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit5]:GPIO8 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x20) { + u8_data |= (1<<4); + } + else { + u8_data &= ~(1<<4); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit6]:GPIO10 + u8_data = pci_read_config8(dev, 0xab); + if (udata8 & 0x40) { + u8_data |= (1<<0); + } + else { + u8_data &= ~(1<<0); + } + pci_write_config8(dev, 0xab, u8_data); + + // LED[bit7]:GPIO66 + u8_data = pci_read_config8(dev, 0x7e); + if (udata8 & 0x80) { + u8_data |= (1<<1); + } + else { + u8_data &= ~(1<<1); + } + pci_write_config8(dev, 0x7e, u8_data); + +} Index: src/mainboard/technexion/tim5690/tn_post_code.h =================================================================== --- src/mainboard/technexion/tim5690/tn_post_code.h (revision 0) +++ src/mainboard/technexion/tim5690/tn_post_code.h (revision 0) @@ -0,0 +1,15 @@ + + +#define LED_MESSAGE_START 0xFF +#define LED_MESSAGE_FINISH 0x99 +#define LED_MESSAGE_RAM 0x01 + + +#ifdef TECHNEXION_EARLY_SETUP + +// TechNexion's Post Code Initially. +void technexion_post_code_init(void); + +#endif + +void technexion_post_code(uint8_t udata8); Index: src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- src/mainboard/technexion/tim5690/mainboard.c (revision 4927) +++ src/mainboard/technexion/tim5690/mainboard.c (working copy) @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <../southbridge/amd/sb600/sb600.h> #include "chip.h" +#include "tn_post_code.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ @@ -44,12 +45,18 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) +/* previous + */ +void tim5690_enable(device_t dev); +int add_mainboard_resources(struct lb_memory *mem); + + uint64_t uma_memory_base, uma_memory_size; /* set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; @@ -176,6 +183,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + technexion_post_code(LED_MESSAGE_FINISH); } struct chip_operations mainboard_ops = {

1 0

[PATCH] Kconfig of socket_AM2r2
by Zheng Bao 08 Nov '09

08 Nov '09

Complete the Kconfig of socket_AM2r2. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/amd/socket_AM2r2/Kconfig =================================================================== --- src/cpu/amd/socket_AM2r2/Kconfig (revision 4914) +++ src/cpu/amd/socket_AM2r2/Kconfig (working copy) @@ -2,6 +2,7 @@ bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT + select PCI_IO_CFG_EXT config CPU_SOCKET_TYPE hex @@ -14,3 +15,32 @@ default 0x0104 depends on CPU_AMD_SOCKET_AM2R2 +config EXT_RT_TBL_SUPPORT + bool + default n + depends on CPU_AMD_SOCKET_AM2R2 + +config EXT_CONF_SUPPORT + bool + default n + depends on CPU_AMD_SOCKET_AM2R2 + +config CBB + hex + default 0x0 + depends on CPU_AMD_SOCKET_AM2R2 + +config CDB + hex + default 0x18 + depends on CPU_AMD_SOCKET_AM2R2 + +config XIP_ROM_BASE + hex + default 0xfff80000 + depends on CPU_AMD_SOCKET_AM2R2 + +config XIP_ROM_SIZE + hex + default 0x80000 + depends on CPU_AMD_SOCKET_AM2R2 _________________________________________________________________ Windows Live: Keep your friends up to date with what you do online. http://www.microsoft.com/middleeast/windows/windowslive/see-it-in-action/so…

1 0

[commit] r4927 - in branches/coreboot-v1: . util/ADLO util/ADLO/bochs
by svn＠coreboot.org 07 Nov '09

07 Nov '09

Author: stepan Date: 2009-11-07 00:45:17 +0000 (Sat, 07 Nov 2009) New Revision: 4927 Removed: branches/coreboot-v1/.cvsignore branches/coreboot-v1/util/ADLO/.cvsignore branches/coreboot-v1/util/ADLO/bochs/.cvsignore Log: drop obsolete .cvsignore files.. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: branches/coreboot-v1/.cvsignore =================================================================== --- branches/coreboot-v1/.cvsignore 2009-11-07 00:08:22 UTC (rev 4926) +++ branches/coreboot-v1/.cvsignore 2009-11-07 00:45:17 UTC (rev 4927) @@ -1,12 +0,0 @@ -COPYING -INSTALL -install-sh -missing -mkinstalldirs -aclocal.m4 -Makefile.in -configure -config.log -config.cache -config.status -Makefile Deleted: branches/coreboot-v1/util/ADLO/.cvsignore =================================================================== --- branches/coreboot-v1/util/ADLO/.cvsignore 2009-11-07 00:08:22 UTC (rev 4926) +++ branches/coreboot-v1/util/ADLO/.cvsignore 2009-11-07 00:45:17 UTC (rev 4927) @@ -1 +0,0 @@ -payload Deleted: branches/coreboot-v1/util/ADLO/bochs/.cvsignore =================================================================== --- branches/coreboot-v1/util/ADLO/bochs/.cvsignore 2009-11-07 00:08:22 UTC (rev 4926) +++ branches/coreboot-v1/util/ADLO/bochs/.cvsignore 2009-11-07 00:45:17 UTC (rev 4927) @@ -1 +0,0 @@ -bochs-cvs

1 0

[v2] r4926 - in branches/coreboot-v1: src/arch/alpha src/arch/alpha/init src/arch/i386 src/arch/i386/init src/arch/ppc src/arch/ppc/init src/config src/lib util/config
by svn＠coreboot.org 07 Nov '09

07 Nov '09

Author: stepan Date: 2009-11-07 00:08:22 +0000 (Sat, 07 Nov 2009) New Revision: 4926 Added: branches/coreboot-v1/src/arch/alpha/init/ branches/coreboot-v1/src/arch/i386/init/ branches/coreboot-v1/src/arch/ppc/init/ Removed: branches/coreboot-v1/src/arch/alpha/config/ branches/coreboot-v1/src/arch/i386/config/ branches/coreboot-v1/src/arch/ppc/config/ Modified: branches/coreboot-v1/src/arch/alpha/init/make.base branches/coreboot-v1/src/arch/i386/init/make.base branches/coreboot-v1/src/arch/ppc/init/make.base branches/coreboot-v1/src/config/Config branches/coreboot-v1/src/lib/clog2.c branches/coreboot-v1/util/config/NLBConfig.py Log: Some operating systems, such as Windows and Mac OS X use case insensitive filesystems per default. On those systems checking out coreboot v1 would fail because in src/arch/<ARCH> there's a file Config and a directory config. I renamed the directory to init. The name is not good, but it's the same name that is used for those files in v2. Also change __FUNCTION__ to __func__ and print it via %s so that I could test my changes by building the v1 Epia target on an OpenSUSE 11.1 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: branches/coreboot-v1/src/arch/alpha/init/make.base =================================================================== --- branches/coreboot-v1/src/arch/alpha/config/make.base 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/src/arch/alpha/init/make.base 2009-11-07 00:08:22 UTC (rev 4926) @@ -2,7 +2,7 @@ rambase 0x8000 option USE_DEFAULT_LAYOUT=1 -ldscript arch/alpha/config/ldscript.base USE_DEFAULT_LAYOUT +ldscript arch/alpha/init/ldscript.base USE_DEFAULT_LAYOUT option MAX_CPUS=1 Modified: branches/coreboot-v1/src/arch/i386/init/make.base =================================================================== --- branches/coreboot-v1/src/arch/i386/config/make.base 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/src/arch/i386/init/make.base 2009-11-07 00:08:22 UTC (rev 4926) @@ -13,7 +13,7 @@ # By default on x86 we have a memory hole between 640K and 1MB option MEMORY_HOLE=1 -ldscript arch/i386/config/ldscript.base +ldscript arch/i386/init/ldscript.base # How do I add -mprefered-stack-boundary=2 if the compiler supports it? # On x86 tt results in a code size reduction. Modified: branches/coreboot-v1/src/arch/ppc/init/make.base =================================================================== --- branches/coreboot-v1/src/arch/ppc/config/make.base 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/src/arch/ppc/init/make.base 2009-11-07 00:08:22 UTC (rev 4926) @@ -5,7 +5,7 @@ # Reserve 8K for each stack option STACK_SIZE=0x2000 -ldscript arch/ppc/config/ldscript.base +ldscript arch/ppc/init/ldscript.base dir /src/config Modified: branches/coreboot-v1/src/config/Config =================================================================== --- branches/coreboot-v1/src/config/Config 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/src/config/Config 2009-11-07 00:08:22 UTC (rev 4926) @@ -55,7 +55,7 @@ makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1) -option CRT0=$(TOP)/src/arch/$(ARCH)/config/crt0.base +option CRT0=$(TOP)/src/arch/$(ARCH)/init/crt0.base makerule crt0.S: $(CRT0) ; cp $< $@ # Force crt0.s (which has build time version code in it to rebuild every time) Modified: branches/coreboot-v1/src/lib/clog2.c =================================================================== --- branches/coreboot-v1/src/lib/clog2.c 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/src/lib/clog2.c 2009-11-07 00:08:22 UTC (rev 4926) @@ -7,8 +7,8 @@ unsigned long pow = sizeof(x) * 8 - 1; if (! x) { - printk_emerg(__FUNCTION__ - " called with invalid parameter of 0\n"); + printk_emerg("%s called with invalid parameter of 0\n", + __func__); return -1; } for(; i > x; i >>= 1, pow--) Modified: branches/coreboot-v1/util/config/NLBConfig.py =================================================================== --- branches/coreboot-v1/util/config/NLBConfig.py 2009-11-06 23:42:26 UTC (rev 4925) +++ branches/coreboot-v1/util/config/NLBConfig.py 2009-11-07 00:08:22 UTC (rev 4926) @@ -261,7 +261,7 @@ def set_arch(dir, my_arch): global arch, makebase arch = my_arch - configpath = os.path.join(treetop, "src/arch/", my_arch, "config") + configpath = os.path.join(treetop, "src/arch/", my_arch, "init") makebase = os.path.join(configpath, "make.base") print "Now Process the ", my_arch, " base files" if (debug): @@ -1135,7 +1135,7 @@ for depfile in [ '%s' % top_config_file, # This a duplicate, remove? '$(TOP)/util/config/NLBConfig.py', - '$(TOP)/src/arch/$(ARCH)/config/make.base' ]: + '$(TOP)/src/arch/$(ARCH)/init/make.base' ]: file.write("$(GENERATED): %s\n" % depfile) file.write("$(GENERATED):\n") @@ -1180,7 +1180,7 @@ # Set the default locations for config files. makebase = os.path.join(treetop, "util/config/make.base") -crt0base = os.path.join(treetop, "arch/i386/config/crt0.base") +crt0base = os.path.join(treetop, "arch/i386/init/crt0.base") doxyscriptbase = os.path.join(treetop, "src/config/doxyscript.base") # Now read in the customizing script...

1 0

[PATCH] Drop drivers/pci/onboard
by Myles Watson 06 Nov '09

06 Nov '09

PCI onboard was only used for ROM images at fixed offsets in flash. Now that we have CBFS, there is no use for it. Fix qemu, since it is a special case where the ROM image ends up at 0xc0000 without any help from coreboot. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Abuild tested. Boot tested on qemu. Thanks, Myles

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coreboot November 2009