coreboot May 2008

coreboot@coreboot.org

79 participants
387 discussions

r194 - buildrom-devel/packages/tint
by svn＠coreboot.org 13 May '08

13 May '08

Author: myles Date: 2008-05-13 23:31:20 +0200 (Tue, 13 May 2008) New Revision: 194 Modified: buildrom-devel/packages/tint/tint.mk Log: This makes it so that checking the "USE_LZMA" option in buildrom doesn't break builds. It moves the USE_LZMA option to the payload menu, since it only affects the payload. It assumes that all Config.lb files don't use compression, and all Config-lab.lb files do. It also updates qemu.conf to use 3281 which has the correct Config-lab.lb. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/tint/tint.mk =================================================================== --- buildrom-devel/packages/tint/tint.mk 2008-05-09 23:20:43 UTC (rev 193) +++ buildrom-devel/packages/tint/tint.mk 2008-05-13 21:31:20 UTC (rev 194) @@ -1,6 +1,6 @@ TINT_ORIG_URL=http://ftp.debian.org/debian/pool/main/t/tint/ TINT_TARBALL=tint_0.03b.tar.gz -TINT_PATCH_REV=3239 +TINT_PATCH_REV=3303 TINT_PATCH_URL="http://tracker.coreboot.org/trac/coreboot/browser/trunk/payloads/external/t…" TINT_PATCH=libpayload_tint.patch

1 0

r3303 - trunk/payloads/external/tint
by svn＠coreboot.org 13 May '08

13 May '08

Author: myles Date: 2008-05-13 23:29:48 +0200 (Tue, 13 May 2008) New Revision: 3303 Modified: trunk/payloads/external/tint/libpayload_tint.patch Log: This is a trivial patch which fixes the tint build by removing the extra typedef for time_t. The other half bumps the tint patch revision in buildrom to take advantage of it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/payloads/external/tint/libpayload_tint.patch =================================================================== --- trunk/payloads/external/tint/libpayload_tint.patch 2008-05-13 14:58:23 UTC (rev 3302) +++ trunk/payloads/external/tint/libpayload_tint.patch 2008-05-13 21:29:48 UTC (rev 3303) @@ -15,8 +15,8 @@ +#define random(x) rand(x) +#define srandom(x) srand(x) +#define curs_set(x) -+typedef int time_t; + ++ /* Score file */ +#if 0 const char scorefile[] = SCOREFILE;

1 0

SimNOW V2 LAB problem
by Marc Karasek 13 May '08

13 May '08

All, I finally got some cycles to look at why I was getting a "trap divied error" when trying to run coreboot v2 + LAB on the SimNOW Cheetah BSD. It looks like linuxrc in busybox is the culprit. It gets to the point in kernel init where it tries to run the linuxrc "program" and that is where it crashes, everything is Ok up to that point. Has anyone else seen a similar issue? Marc -- ********************* Marc Karasek MTS Sun Microsystems mailto:marc.karasek@sun.com ph:770.360.6415 *********************

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we've always known this was possible and hence never bothered to do it but ...
by ron minnich 13 May '08

13 May '08

somebody got around to it. http://www.pcworld.com/businesscenter/article/145703/hackers_find_a_new_pla… The world, sooner or later, is going to get the message :-) ron

6 9

LinuxTag 2008: free tickets
by Carl-Daniel Hailfinger 13 May '08

13 May '08

The LinuxTag organizers have offered us a few free tickets for coreboot project members and friends. If you want one of those tickets, reply to me or to the list and tell me in a few words why you deserve that ticket. Contributing code is a very valid reason, but other suggestions are welcome as well. Regards, Carl-Daniel

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[PATCH] artecgroup/dbe62: Route ethernet adapter IRQ correctly and reduce interrupt contention problems by using different IRQs for all the interrupt lines
by Mart Raudsepp 13 May '08

13 May '08

artecgroup/dbe62: Route ethernet adapter IRQ correctly and reduce interrupt contention problems by using different IRQs for all the interrupt lines This makes the network adapter work fully, and reduces problems on high traffic (e.g kernel oopses on fsck run over USB 2.0 HDD) Many thanks for Peter Stuge for a lot of IRQ related help. Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> --- mainboard/artecgroup/dbe62/irq_tables.h | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/mainboard/artecgroup/dbe62/irq_tables.h b/mainboard/artecgroup/dbe62/irq_tables.h index d8d64a6..0d1a4bb 100644 --- a/mainboard/artecgroup/dbe62/irq_tables.h +++ b/mainboard/artecgroup/dbe62/irq_tables.h @@ -23,10 +23,10 @@ #define IRQ_SLOT_COUNT 3 /* Platform IRQs */ -#define PIRQA 10 -#define PIRQB 11 -#define PIRQC 10 -#define PIRQD 11 +#define PIRQA 11 +#define PIRQB 10 +#define PIRQC 9 +#define PIRQD 5 /* Map */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ @@ -60,6 +60,6 @@ const struct irq_routing_table intel_irq_routing_table = { /* chipset */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* ethernet */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, } }; -- 1.5.5.1

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Supermicro h8dmr
by Viswesh S 13 May '08

13 May '08

Hi, I would like to know more about coreboot written for supermicro h8dmr boards. Is there anybody in the list, with whom I can check with some doubts. Thanks in advance, Viswesh Bollywood, fun, friendship, sports and more. You name it, we have it on http://in.promos.yahoo.com/groups/bestofyahoo/

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[PATCH] flashrom: restructure SPI support, part 2
by Carl-Daniel Hailfinger 13 May '08

13 May '08

flashrom: Move the SPI #defines from spi.c to spi.h This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spirestructure/spi.c =================================================================== --- flashrom-spirestructure/spi.c (Revision 3301) +++ flashrom-spirestructure/spi.c (Arbeitskopie) @@ -27,71 +27,12 @@ #include <stdint.h> #include <string.h> #include "flash.h" +#include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e -/* Read Electronic ID */ -#define JEDEC_RDID 0x9f -#define JEDEC_RDID_OUTSIZE 0x01 -#define JEDEC_RDID_INSIZE 0x03 -/* Write Enable */ -#define JEDEC_WREN 0x06 -#define JEDEC_WREN_OUTSIZE 0x01 -#define JEDEC_WREN_INSIZE 0x00 - -/* Write Disable */ -#define JEDEC_WRDI 0x04 -#define JEDEC_WRDI_OUTSIZE 0x01 -#define JEDEC_WRDI_INSIZE 0x00 - -/* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_60 0x60 -#define JEDEC_CE_60_OUTSIZE 0x01 -#define JEDEC_CE_60_INSIZE 0x00 - -/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ -#define JEDEC_CE_C7 0xc7 -#define JEDEC_CE_C7_OUTSIZE 0x01 -#define JEDEC_CE_C7_INSIZE 0x00 - -/* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_52 0x52 -#define JEDEC_BE_52_OUTSIZE 0x04 -#define JEDEC_BE_52_INSIZE 0x00 - -/* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_D8 0xd8 -#define JEDEC_BE_D8_OUTSIZE 0x04 -#define JEDEC_BE_D8_INSIZE 0x00 - -/* Sector Erase 0x20 is supported by Macronix/SST chips. */ -#define JEDEC_SE 0x20 -#define JEDEC_SE_OUTSIZE 0x04 -#define JEDEC_SE_INSIZE 0x00 - -/* Read Status Register */ -#define JEDEC_RDSR 0x05 -#define JEDEC_RDSR_OUTSIZE 0x01 -#define JEDEC_RDSR_INSIZE 0x01 -#define JEDEC_RDSR_BIT_WIP (0x01 << 0) - -/* Write Status Register */ -#define JEDEC_WRSR 0x01 -#define JEDEC_WRSR_OUTSIZE 0x02 -#define JEDEC_WRSR_INSIZE 0x00 - -/* Read the memory */ -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -/* JEDEC_READ_INSIZE : any length */ - -/* Write memory byte */ -#define JEDEC_BYTE_PROGRAM 0x02 -#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 -#define JEDEC_BYTE_PROGRAM_INSIZE 0x00 - uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; Index: flashrom-spirestructure/spi.h =================================================================== --- flashrom-spirestructure/spi.h (Revision 0) +++ flashrom-spirestructure/spi.h (Revision 0) @@ -0,0 +1,88 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SPI_H__ +#define __SPI_H__ 1 + +/* + * Contains the generic SPI headers + */ + +/* Read Electronic ID */ +#define JEDEC_RDID 0x9f +#define JEDEC_RDID_OUTSIZE 0x01 +#define JEDEC_RDID_INSIZE 0x03 + +/* Write Enable */ +#define JEDEC_WREN 0x06 +#define JEDEC_WREN_OUTSIZE 0x01 +#define JEDEC_WREN_INSIZE 0x00 + +/* Write Disable */ +#define JEDEC_WRDI 0x04 +#define JEDEC_WRDI_OUTSIZE 0x01 +#define JEDEC_WRDI_INSIZE 0x00 + +/* Chip Erase 0x60 is supported by Macronix/SST chips. */ +#define JEDEC_CE_60 0x60 +#define JEDEC_CE_60_OUTSIZE 0x01 +#define JEDEC_CE_60_INSIZE 0x00 + +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +#define JEDEC_CE_C7 0xc7 +#define JEDEC_CE_C7_OUTSIZE 0x01 +#define JEDEC_CE_C7_INSIZE 0x00 + +/* Block Erase 0x52 is supported by SST chips. */ +#define JEDEC_BE_52 0x52 +#define JEDEC_BE_52_OUTSIZE 0x04 +#define JEDEC_BE_52_INSIZE 0x00 + +/* Block Erase 0xd8 is supported by EON/Macronix chips. */ +#define JEDEC_BE_D8 0xd8 +#define JEDEC_BE_D8_OUTSIZE 0x04 +#define JEDEC_BE_D8_INSIZE 0x00 + +/* Sector Erase 0x20 is supported by Macronix/SST chips. */ +#define JEDEC_SE 0x20 +#define JEDEC_SE_OUTSIZE 0x04 +#define JEDEC_SE_INSIZE 0x00 + +/* Read Status Register */ +#define JEDEC_RDSR 0x05 +#define JEDEC_RDSR_OUTSIZE 0x01 +#define JEDEC_RDSR_INSIZE 0x01 +#define JEDEC_RDSR_BIT_WIP (0x01 << 0) + +/* Write Status Register */ +#define JEDEC_WRSR 0x01 +#define JEDEC_WRSR_OUTSIZE 0x02 +#define JEDEC_WRSR_INSIZE 0x00 + +/* Read the memory */ +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +/* JEDEC_READ_INSIZE : any length */ + +/* Write memory byte */ +#define JEDEC_BYTE_PROGRAM 0x02 +#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 +#define JEDEC_BYTE_PROGRAM_INSIZE 0x00 + +#endif /* !__SPI_H__ */

2 2

r3302 - trunk/util/flashrom
by svn＠coreboot.org 13 May '08

13 May '08

Author: hailfinger Date: 2008-05-13 16:58:23 +0200 (Tue, 13 May 2008) New Revision: 3302 Added: trunk/util/flashrom/spi.h Modified: trunk/util/flashrom/spi.c Log: flashrom: Move the SPI #defines from spi.c to spi.h This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-05-13 14:01:22 UTC (rev 3301) +++ trunk/util/flashrom/spi.c 2008-05-13 14:58:23 UTC (rev 3302) @@ -27,71 +27,12 @@ #include <stdint.h> #include <string.h> #include "flash.h" +#include "spi.h" #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e -/* Read Electronic ID */ -#define JEDEC_RDID 0x9f -#define JEDEC_RDID_OUTSIZE 0x01 -#define JEDEC_RDID_INSIZE 0x03 -/* Write Enable */ -#define JEDEC_WREN 0x06 -#define JEDEC_WREN_OUTSIZE 0x01 -#define JEDEC_WREN_INSIZE 0x00 - -/* Write Disable */ -#define JEDEC_WRDI 0x04 -#define JEDEC_WRDI_OUTSIZE 0x01 -#define JEDEC_WRDI_INSIZE 0x00 - -/* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_60 0x60 -#define JEDEC_CE_60_OUTSIZE 0x01 -#define JEDEC_CE_60_INSIZE 0x00 - -/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ -#define JEDEC_CE_C7 0xc7 -#define JEDEC_CE_C7_OUTSIZE 0x01 -#define JEDEC_CE_C7_INSIZE 0x00 - -/* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_52 0x52 -#define JEDEC_BE_52_OUTSIZE 0x04 -#define JEDEC_BE_52_INSIZE 0x00 - -/* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_D8 0xd8 -#define JEDEC_BE_D8_OUTSIZE 0x04 -#define JEDEC_BE_D8_INSIZE 0x00 - -/* Sector Erase 0x20 is supported by Macronix/SST chips. */ -#define JEDEC_SE 0x20 -#define JEDEC_SE_OUTSIZE 0x04 -#define JEDEC_SE_INSIZE 0x00 - -/* Read Status Register */ -#define JEDEC_RDSR 0x05 -#define JEDEC_RDSR_OUTSIZE 0x01 -#define JEDEC_RDSR_INSIZE 0x01 -#define JEDEC_RDSR_BIT_WIP (0x01 << 0) - -/* Write Status Register */ -#define JEDEC_WRSR 0x01 -#define JEDEC_WRSR_OUTSIZE 0x02 -#define JEDEC_WRSR_INSIZE 0x00 - -/* Read the memory */ -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -/* JEDEC_READ_INSIZE : any length */ - -/* Write memory byte */ -#define JEDEC_BYTE_PROGRAM 0x02 -#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 -#define JEDEC_BYTE_PROGRAM_INSIZE 0x00 - uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi = 1; Added: trunk/util/flashrom/spi.h =================================================================== --- trunk/util/flashrom/spi.h (rev 0) +++ trunk/util/flashrom/spi.h 2008-05-13 14:58:23 UTC (rev 3302) @@ -0,0 +1,88 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SPI_H__ +#define __SPI_H__ 1 + +/* + * Contains the generic SPI headers + */ + +/* Read Electronic ID */ +#define JEDEC_RDID 0x9f +#define JEDEC_RDID_OUTSIZE 0x01 +#define JEDEC_RDID_INSIZE 0x03 + +/* Write Enable */ +#define JEDEC_WREN 0x06 +#define JEDEC_WREN_OUTSIZE 0x01 +#define JEDEC_WREN_INSIZE 0x00 + +/* Write Disable */ +#define JEDEC_WRDI 0x04 +#define JEDEC_WRDI_OUTSIZE 0x01 +#define JEDEC_WRDI_INSIZE 0x00 + +/* Chip Erase 0x60 is supported by Macronix/SST chips. */ +#define JEDEC_CE_60 0x60 +#define JEDEC_CE_60_OUTSIZE 0x01 +#define JEDEC_CE_60_INSIZE 0x00 + +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +#define JEDEC_CE_C7 0xc7 +#define JEDEC_CE_C7_OUTSIZE 0x01 +#define JEDEC_CE_C7_INSIZE 0x00 + +/* Block Erase 0x52 is supported by SST chips. */ +#define JEDEC_BE_52 0x52 +#define JEDEC_BE_52_OUTSIZE 0x04 +#define JEDEC_BE_52_INSIZE 0x00 + +/* Block Erase 0xd8 is supported by EON/Macronix chips. */ +#define JEDEC_BE_D8 0xd8 +#define JEDEC_BE_D8_OUTSIZE 0x04 +#define JEDEC_BE_D8_INSIZE 0x00 + +/* Sector Erase 0x20 is supported by Macronix/SST chips. */ +#define JEDEC_SE 0x20 +#define JEDEC_SE_OUTSIZE 0x04 +#define JEDEC_SE_INSIZE 0x00 + +/* Read Status Register */ +#define JEDEC_RDSR 0x05 +#define JEDEC_RDSR_OUTSIZE 0x01 +#define JEDEC_RDSR_INSIZE 0x01 +#define JEDEC_RDSR_BIT_WIP (0x01 << 0) + +/* Write Status Register */ +#define JEDEC_WRSR 0x01 +#define JEDEC_WRSR_OUTSIZE 0x02 +#define JEDEC_WRSR_INSIZE 0x00 + +/* Read the memory */ +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +/* JEDEC_READ_INSIZE : any length */ + +/* Write memory byte */ +#define JEDEC_BYTE_PROGRAM 0x02 +#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 +#define JEDEC_BYTE_PROGRAM_INSIZE 0x00 + +#endif /* !__SPI_H__ */

1 0

[PATCH] flashrom: restructure SPI support, part 1
by Carl-Daniel Hailfinger 13 May '08

13 May '08

Change the SPI parts of flashrom to prepare for a merge of ICH9 SPI support. In theory, this patch has no behaviour changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spirestructure/spi.c =================================================================== --- flashrom-spirestructure/spi.c (Revision 3300) +++ flashrom-spirestructure/spi.c (Arbeitskopie) @@ -32,47 +32,47 @@ #define ITE_SUPERIO_PORT2 0x4e /* Read Electronic ID */ -#define JEDEC_RDID {0x9f} +#define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 #define JEDEC_RDID_INSIZE 0x03 /* Write Enable */ -#define JEDEC_WREN {0x06} +#define JEDEC_WREN 0x06 #define JEDEC_WREN_OUTSIZE 0x01 #define JEDEC_WREN_INSIZE 0x00 /* Write Disable */ -#define JEDEC_WRDI {0x04} +#define JEDEC_WRDI 0x04 #define JEDEC_WRDI_OUTSIZE 0x01 #define JEDEC_WRDI_INSIZE 0x00 /* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_60 {0x60}; +#define JEDEC_CE_60 0x60 #define JEDEC_CE_60_OUTSIZE 0x01 #define JEDEC_CE_60_INSIZE 0x00 /* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ -#define JEDEC_CE_C7 {0xc7}; +#define JEDEC_CE_C7 0xc7 #define JEDEC_CE_C7_OUTSIZE 0x01 #define JEDEC_CE_C7_INSIZE 0x00 /* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_52 {0x52}; +#define JEDEC_BE_52 0x52 #define JEDEC_BE_52_OUTSIZE 0x04 #define JEDEC_BE_52_INSIZE 0x00 /* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_D8 {0xd8}; +#define JEDEC_BE_D8 0xd8 #define JEDEC_BE_D8_OUTSIZE 0x04 #define JEDEC_BE_D8_INSIZE 0x00 /* Sector Erase 0x20 is supported by Macronix/SST chips. */ -#define JEDEC_SE {0x20}; +#define JEDEC_SE 0x20 #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 /* Read Status Register */ -#define JEDEC_RDSR {0x05}; +#define JEDEC_RDSR 0x05 #define JEDEC_RDSR_OUTSIZE 0x01 #define JEDEC_RDSR_INSIZE 0x01 #define JEDEC_RDSR_BIT_WIP (0x01 << 0) @@ -251,7 +251,7 @@ static int spi_rdid(unsigned char *readarr) { - const unsigned char cmd[] = JEDEC_RDID; + const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID}; if (spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr)) return 1; @@ -261,7 +261,7 @@ void spi_write_enable() { - const unsigned char cmd[] = JEDEC_WREN; + const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN}; /* Send WREN (Write Enable) */ spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); @@ -269,7 +269,7 @@ void spi_write_disable() { - const unsigned char cmd[] = JEDEC_WRDI; + const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI}; /* Send WRDI (Write Disable) */ spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); @@ -310,7 +310,7 @@ uint8_t spi_read_status_register() { - const unsigned char cmd[] = JEDEC_RDSR; + const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; unsigned char readarr[1]; /* Read Status Register */ @@ -393,7 +393,7 @@ int spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[] = JEDEC_CE_C7; + const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7}; spi_disable_blockprotect(); spi_write_enable(); @@ -414,7 +414,7 @@ */ int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8; + unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8}; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; @@ -433,7 +433,7 @@ /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_sector_erase(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_SE_OUTSIZE] = JEDEC_SE; + unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE}; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); @@ -479,7 +479,7 @@ */ void spi_write_status_register(int status) { - const unsigned char cmd[] = {JEDEC_WRSR, (unsigned char)status}; + const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status}; /* Send WRSR (Write Status Register) */ spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL);

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coreboot May 2008