coreboot May 2008

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splashtop
by Raphaël Jacquot 15 May '08

15 May '08

awefully looks like coreboot with a linux / x / mozilla / skype payload

1 0

r3319 - trunk/util/superiotool
by svn＠coreboot.org 15 May '08

15 May '08

Author: uwe Date: 2008-05-15 00:56:47 +0200 (Thu, 15 May 2008) New Revision: 3319 Modified: trunk/util/superiotool/superiotool.h Log: Some NSC Super I/Os can have their config port at 0x15c (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/superiotool.h =================================================================== --- trunk/util/superiotool/superiotool.h 2008-05-14 21:20:55 UTC (rev 3318) +++ trunk/util/superiotool/superiotool.h 2008-05-14 22:56:47 UTC (rev 3319) @@ -119,7 +119,7 @@ {probe_idregs_ali, {0x3f0, 0x370, EOT}}, {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, {probe_idregs_ite, {0x2e, 0x4e, EOT}}, - {probe_idregs_nsc, {0x2e, 0x4e, EOT}}, + {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, };

1 0

r3318 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: uwe Date: 2008-05-14 23:20:55 +0200 (Wed, 14 May 2008) New Revision: 3318 Modified: trunk/util/inteltool/Makefile trunk/util/inteltool/inteltool.8 trunk/util/inteltool/inteltool.c Log: Cosmetics, whitespace, coding style, partially ident-aided (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/inteltool/Makefile =================================================================== --- trunk/util/inteltool/Makefile 2008-05-14 20:10:02 UTC (rev 3317) +++ trunk/util/inteltool/Makefile 2008-05-14 21:20:55 UTC (rev 3318) @@ -39,7 +39,7 @@ distclean: clean rm -f $(PROGRAM) .dependencies - + dep: @$(CC) -MM *.c > .dependencies Modified: trunk/util/inteltool/inteltool.8 =================================================================== --- trunk/util/inteltool/inteltool.8 2008-05-14 20:10:02 UTC (rev 3317) +++ trunk/util/inteltool/inteltool.8 2008-05-14 21:20:55 UTC (rev 3318) @@ -1,4 +1,4 @@ -.TH INTELTOOL 8 "May 12, 2008" +.TH INTELTOOL 8 "May 14, 2008" .SH NAME inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters .SH SYNOPSIS @@ -7,9 +7,9 @@ .B inteltool is a handy little tool for dumping the configuration space of Intel(R) CPUs, northbridges and southbridges. - +.sp This tool has been developed for the coreboot project (see -.B http://www.coreboot.org/ +.B http://coreboot.org for details on coreboot). .SH OPTIONS .TP @@ -20,31 +20,32 @@ Show version information and exit. .TP .B "\-a, \-\-all" -Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge and Intel(R) Core CPU MSRs. +Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge +and Intel(R) Core CPU MSRs. .TP .B "\-g, \-\-gpio" -Dump I/O Controller Hub (ICH) southbridge GPIO registers +Dump I/O Controller Hub (ICH) southbridge GPIO registers. .TP .B "\-r, \-\-rcba" -Dump I/O Controller Hub (ICH) southbridge RCBA registers +Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP .B "\-p, \-\-pmbase" -Dump I/O Controller Hub (ICH) southbridge pmbase registers +Dump I/O Controller Hub (ICH) southbridge PMBASE registers. .TP .B "\-m, \-\-mchbar" -Dump Intel(R) northbridge MCHBAR registers +Dump Intel(R) northbridge MCHBAR registers. .TP .B "\-e, \-\-epbar" -Dump Intel(R) northbridge EPBAR registers +Dump Intel(R) northbridge EPBAR registers. .TP .B "\-d, \-\-dmibar" -Dump Intel(R) northbridge DMIBAR registers +Dump Intel(R) northbridge DMIBAR registers. .TP .B "\-P, \-\-pciexbar" -Dump Intel(R) northbridge PCIEXBAR registers +Dump Intel(R) northbridge PCIEXBAR registers. .TP .B "\-M, \-\-msrs" -Dump Intel(R) CPU MSRs +Dump Intel(R) CPU MSRs. .SH BUGS Please report any bugs at .BR http://tracker.coreboot.org/trac/coreboot/newticket "," @@ -54,13 +55,13 @@ .B inteltool is covered by the GNU General Public License (GPL), version 2. .SH COPYRIGHT -(C) 2008 coresystems GmbH +Copyright (C) 2008 coresystems GmbH .SH AUTHORS Stefan Reinauer <stepan(a)coresystems.de> .PP This manual page was written by Stefan Reinauer <stepan(a)coresystems.de>. It is licensed under the terms of the GNU GPL (version 2). - -Intel(R) is a registered trademark of Intel Corporation. Other product and/or company names mentioned herein may be trademarks or registered trademarks of their respective owners. - - +.sp +Intel(R) is a registered trademark of Intel Corporation. Other product +and/or company names mentioned herein may be trademarks or registered +trademarks of their respective owners. Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-14 20:10:02 UTC (rev 3317) +++ trunk/util/inteltool/inteltool.c 2008-05-14 21:20:55 UTC (rev 3318) @@ -32,7 +32,7 @@ #define INTELTOOL_VERSION "1.0" -/* Tested Chipsets: */ +/* Tested chipsets: */ #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_ICH 0x2410 #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 @@ -46,7 +46,7 @@ static const struct { uint16_t vendor_id, device_id; - char * name; + char *name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, @@ -59,9 +59,6 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; - - - #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) int fd_mem; @@ -70,8 +67,7 @@ typedef struct { uint32_t hi, lo; } msr_t; typedef struct { uint16_t addr; int size; char *name; } io_register_t; - -static const io_register_t ich0_gpio_registers[] = { +static const io_register_t ich0_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, @@ -90,7 +86,7 @@ { 0x3C, 4, "RESERVED" } }; -static const io_register_t ich4_gpio_registers[] = { +static const io_register_t ich4_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, @@ -109,7 +105,7 @@ { 0x3C, 4, "RESERVED" } }; -static const io_register_t ich7_gpio_registers[] = { +static const io_register_t ich7_gpio_registers[] = { { 0x00, 4, "GPIO_USE_SEL" }, { 0x04, 4, "GP_IO_SEL" }, { 0x08, 4, "RESERVED" }, @@ -167,22 +163,22 @@ printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); - for (i=0; i<size; i++) { + for (i = 0; i < size; i++) { switch (gpio_registers[i].size) { case 4: - printf("gpiobase+0x%04x: 0x%08x (%s)\n", + printf("gpiobase+0x%04x: 0x%08x (%s)\n", gpio_registers[i].addr, inl(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); break; case 2: - printf("gpiobase+0x%04x: 0x%04x (%s)\n", + printf("gpiobase+0x%04x: 0x%04x (%s)\n", gpio_registers[i].addr, inw(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); break; case 1: - printf("gpiobase+0x%04x: 0x%02x (%s)\n", + printf("gpiobase+0x%04x: 0x%02x (%s)\n", gpio_registers[i].addr, inb(gpiobase+gpio_registers[i].addr), gpio_registers[i].name); @@ -195,7 +191,7 @@ int print_rcba(struct pci_dev *sb) { - int i, size=0x4000; + int i, size = 0x4000; volatile uint8_t *rcba; uint32_t rcba_phys; @@ -206,7 +202,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: - rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: @@ -229,18 +225,18 @@ printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys); - for (i=0; i<size; i+=4) { - if(*(uint32_t *)(rcba+i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba+i)); + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(rcba + i)) + printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); } - munmap((void *) rcba, size); + munmap((void *)rcba, size); return 0; } int print_pmbase(struct pci_dev *sb) { - int i, size=0x80; + int i, size = 0x80; uint16_t pmbase; printf("\n============= PMBASE ============\n\n"); @@ -250,7 +246,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: - pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pmbase = pci_read_word(sb, 0x40) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); @@ -262,8 +258,8 @@ printf("PMBASE = 0x%04x (IO)\n\n", pmbase); - for (i=0; i<size; i+=4) { - printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase+i)); + for (i = 0; i < size; i += 4) { + printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i)); } return 0; @@ -272,10 +268,9 @@ /* * (G)MCH MMIO Config Space */ - int print_mchbar(struct pci_dev *nb) { - int i, size=(16*1024); + int i, size = (16 * 1024); volatile uint8_t *mchbar; uint32_t mchbar_phys; @@ -283,7 +278,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: - mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; + mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); @@ -294,7 +289,7 @@ } mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) mchbar_phys ); + fd_mem, (off_t) mchbar_phys); if (mchbar == MAP_FAILED) { perror("Error mapping MCHBAR"); @@ -303,12 +298,12 @@ printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); - for (i=0; i<size; i+=4) { - if(*(uint32_t *)(mchbar+i)) + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(mchbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } - munmap((void *) mchbar, size); + munmap((void *)mchbar, size); return 0; } @@ -317,7 +312,7 @@ */ int print_epbar(struct pci_dev *nb) { - int i, size=4096; + int i, size = (4 * 1024); volatile uint8_t *epbar; uint32_t epbar_phys; @@ -325,7 +320,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: - epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have EPBAR.\n"); @@ -336,7 +331,7 @@ } epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) epbar_phys ); + fd_mem, (off_t) epbar_phys); if (epbar == MAP_FAILED) { perror("Error mapping EPBAR"); @@ -344,22 +339,21 @@ } printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); - for (i=0; i<size; i+=4) { - if(*(uint32_t *)(epbar+i)) + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } - munmap((void *) epbar, size); + munmap((void *)epbar, size); return 0; } - /* - * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space + * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space */ int print_dmibar(struct pci_dev *nb) { - int i, size=4096; + int i, size = (4 * 1024); volatile uint8_t *dmibar; uint32_t dmibar_phys; @@ -367,7 +361,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: - dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; + dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have DMIBAR.\n"); @@ -378,7 +372,7 @@ } dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) dmibar_phys ); + fd_mem, (off_t) dmibar_phys); if (dmibar == MAP_FAILED) { perror("Error mapping DMIBAR"); @@ -386,12 +380,12 @@ } printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); - for (i=0; i<size; i+=4) { - if(*(uint32_t *)(dmibar+i)) + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } - munmap((void *) dmibar, size); + munmap((void *)dmibar, size); return 0; } @@ -410,7 +404,7 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: - pciexbar_reg = pci_read_long(nb, 0x48); + pciexbar_reg = pci_read_long(nb, 0x48); break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); @@ -420,7 +414,7 @@ return 1; } - if( !(pciexbar_reg & (1 << 0))) { + if (!(pciexbar_reg & (1 << 0))) { printf("PCIEXBAR register is disabled.\n"); return 0; } @@ -439,14 +433,14 @@ max_busses = 64; break; default: // RSVD - printf("Undefined Address base. Bailing out\n"); + printf("Undefined address base. Bailing out.\n"); return 1; } printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); - pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) pciexbar_phys ); + pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, + MAP_SHARED, fd_mem, (off_t) pciexbar_phys); if (pciexbar == MAP_FAILED) { perror("Error mapping PCIEXBAR"); @@ -471,7 +465,7 @@ } printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn); - for (i=0; i<4096; i++) { + for (i = 0; i < 4096; i++) { if((i % 0x10) == 0) printf("\n%04x:", i); printf(" %02x", *(pciexbar+devbase+i)); @@ -481,7 +475,7 @@ } } - munmap((void *) pciexbar, (max_busses * 1024 * 1024)); + munmap((void *)pciexbar, (max_busses * 1024 * 1024)); return 0; } @@ -490,7 +484,7 @@ msr_t rdmsr(int addr) { - unsigned char buf[8]; + uint8_t buf[8]; msr_t msr = { 0xffffffff, 0xffffffff }; if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { @@ -501,7 +495,7 @@ if (read(fd_msr, buf, 8) == 8) { msr.lo = *(uint32_t *)buf; - msr.hi = *(uint32_t *)(buf+4); + msr.hi = *(uint32_t *)(buf + 4); return msr; } @@ -524,7 +518,6 @@ unsigned int i, core; msr_t msr; - #define IA32_PLATFORM_ID 0x0017 #define EBL_CR_POWERON 0x002a #define FSB_CLK_STS 0x00cd @@ -610,8 +603,8 @@ //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO }; - fd_msr = open("/dev/cpu/0/msr", O_RDWR); - if (fd_msr<0) { + fd_msr = open("/dev/cpu/0/msr", O_RDWR); + if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; @@ -622,38 +615,39 @@ for (i = 0; i < ARRAY_SIZE(global_msrs); i++) { msr = rdmsr(global_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - global_msrs[i].number, msr.hi, msr.lo, global_msrs[i].name); + global_msrs[i].number, msr.hi, msr.lo, + global_msrs[i].name); } - close(fd_msr); - - for (core=0; core < 8; core++) { + + for (core = 0; core < 8; core++) { char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); fd_msr = open(msrfilename, O_RDWR); - if (fd_msr<0) { - /* If the file is not there, we're probably through. - * No error, since we successfully opened /dev/cpu/0/msr before - */ + + /* If the file is not there, we're probably through. No error, + * since we successfully opened /dev/cpu/0/msr before. + */ + if (fd_msr < 0) break; - } printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < ARRAY_SIZE(per_core_msrs); i++) { msr = rdmsr(per_core_msrs[i].number); printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", - per_core_msrs[i].number, msr.hi, msr.lo, per_core_msrs[i].name); + per_core_msrs[i].number, msr.hi, msr.lo, + per_core_msrs[i].name); } close(fd_msr); } if (msr_readerror) - printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); + printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); return 0; } @@ -689,7 +683,7 @@ " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" " -a | --all: dump all known registers\n" - "\n"); + "\n"); exit(1); } @@ -697,15 +691,13 @@ { struct pci_access *pacc; struct pci_dev *sb, *nb; - int opt; - int option_index = 0; - int i; + int i, opt, option_index = 0; - char *sbname="unknown", *nbname="unknown"; + char *sbname = "unknown", *nbname = "unknown"; - int dump_gpios=0, dump_mchbar=0, dump_rcba=0; - int dump_pmbase=0, dump_epbar=0, dump_dmibar=0; - int dump_pciexbar=0, dump_coremsrs=0; + int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; + int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; + int dump_pciexbar = 0, dump_coremsrs = 0; static struct option long_options[] = { {"version", 0, 0, 'v'}, @@ -723,7 +715,7 @@ }; while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", - long_options, &option_index)) != EOF) { + long_options, &option_index)) != EOF) { switch (opt) { case 'v': print_version(); @@ -772,7 +764,10 @@ } } - if (iopl(3)) { printf("You need to be root.\n"); exit(1); } + if (iopl(3)) { + printf("You need to be root.\n"); + exit(1); + } if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); @@ -783,7 +778,6 @@ pci_init(pacc); pci_scan_bus(pacc); - /* Find the required devices */ sb = pci_get_dev(pacc, 0, 0, 0x1f, 0); @@ -815,10 +809,10 @@ /* TODO check cpuid, too */ /* Determine names */ - for (i=0; i<ARRAY_SIZE(supported_chips_list); i++) + for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) if (nb->device_id == supported_chips_list[i].device_id) nbname = supported_chips_list[i].name; - for (i=0; i<ARRAY_SIZE(supported_chips_list); i++) + for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) if (sb->device_id == supported_chips_list[i].device_id) sbname = supported_chips_list[i].name; @@ -870,9 +864,7 @@ printf("\n\n"); } - /* Clean up */ - pci_free_dev(nb); pci_free_dev(sb); pci_cleanup(pacc);

1 0

r3317 - trunk/payloads/libpayload/curses
by svn＠coreboot.org 14 May '08

14 May '08

Author: jcrouse Date: 2008-05-14 22:10:02 +0200 (Wed, 14 May 2008) New Revision: 3317 Modified: trunk/payloads/libpayload/curses/tinycurses.c Log: libpayload: implement wborder function Implement the wborder function for curses to draw a box around a window. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/payloads/libpayload/curses/tinycurses.c =================================================================== --- trunk/payloads/libpayload/curses/tinycurses.c 2008-05-14 20:07:31 UTC (rev 3316) +++ trunk/payloads/libpayload/curses/tinycurses.c 2008-05-14 20:10:02 UTC (rev 3317) @@ -464,7 +464,39 @@ } // int wbkgd (WINDOW *, chtype) {} void wbkgdset(WINDOW *win, chtype ch) { /* TODO */ } -// int wborder (WINDOW *,chtype,chtype,chtype,chtype,chtype,chtype,chtype,chtype) {} + +int wborder(WINDOW *win, chtype ls, chtype rs, chtype ts, chtype bs, + chtype tl, chtype tr, chtype bl, chtype br) +{ + int x, y; + + for(y = 0; y <= win->_maxy; y++) { + + if (y == 0) { + mvwaddch(win, y, 0, tl); + + for(x = 1; x < win->_maxx; x++) + mvwaddch(win, y, x, ts); + + mvwaddch(win, y, win->_maxx, tr); + } + else if (y == win->_maxy) { + mvwaddch(win, y, 0, bl); + + for(x = 1; x < win->_maxx; x++) + mvwaddch(win, y, x, bs); + + mvwaddch(win, y, win->_maxx, br); + } + else { + mvwaddch(win, y, 0, ls); + mvwaddch(win, y, win->_maxx, rs); + } + } + + return OK; +} + // int wchgat (WINDOW *, int, attr_t, short, const void *) {} /* D */ int wclear(WINDOW *win) {

1 0

r3316 - in trunk/payloads/libpayload: drivers/video sample
by svn＠coreboot.org 14 May '08

14 May '08

Author: jcrouse Date: 2008-05-14 22:07:31 +0200 (Wed, 14 May 2008) New Revision: 3316 Modified: trunk/payloads/libpayload/drivers/video/video.c trunk/payloads/libpayload/sample/hello.c Log: libpayload: Fix the putc function Reverse rows and columns on the video putc() function, and watch printf work again. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/payloads/libpayload/drivers/video/video.c =================================================================== --- trunk/payloads/libpayload/drivers/video/video.c 2008-05-14 20:05:00 UTC (rev 3315) +++ trunk/payloads/libpayload/drivers/video/video.c 2008-05-14 20:07:31 UTC (rev 3316) @@ -126,14 +126,14 @@ case '\t': while(cursorx % 8 && cursorx < VIDEO_COLS) { if (console) - console->putc(cursorx, cursory, (ch & 0xFF00) | ' '); + console->putc(cursory, cursorx, (ch & 0xFF00) | ' '); cursorx++; } break; default: if (console) - console->putc(cursorx++, cursory, ch); + console->putc(cursory, cursorx++, ch); break; } Modified: trunk/payloads/libpayload/sample/hello.c =================================================================== --- trunk/payloads/libpayload/sample/hello.c 2008-05-14 20:05:00 UTC (rev 3315) +++ trunk/payloads/libpayload/sample/hello.c 2008-05-14 20:07:31 UTC (rev 3316) @@ -33,5 +33,6 @@ int main(void) { + printf("Hello world!\n"); return 0; }

1 0

r3315 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: stepan Date: 2008-05-14 22:05:00 +0200 (Wed, 14 May 2008) New Revision: 3315 Modified: trunk/util/inteltool/inteltool.c Log: add ICH7-M and ICH7 DH to inteltool (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-14 14:51:22 UTC (rev 3314) +++ trunk/util/inteltool/inteltool.c 2008-05-14 20:05:00 UTC (rev 3315) @@ -38,7 +38,9 @@ #define PCI_DEVICE_ID_INTEL_ICH0 0x2420 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 @@ -48,7 +50,9 @@ } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, @@ -134,6 +138,8 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich7_gpio_registers; @@ -197,6 +203,8 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; @@ -239,6 +247,8 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: pmbase = pci_read_word(sb, 0x40) & 0xfffc; break;

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Re: [coreboot] r3307 - trunk/util/inteltool
by Joseph Smith 14 May '08

14 May '08

On Wed, 14 May 2008 13:38:23 +0200, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-05-14 13:38:22 +0200 (Wed, 14 May 2008) > New Revision: 3307 > > Modified: > trunk/util/inteltool/inteltool.c > Log: > Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and > ICH7 > have different register meanings, so they get their own lookup tables. > Is this for me Stephan? Thanks I will test it out asap :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[PATCH] flashrom: Infrastructure for ICH9 merge
by Carl-Daniel Hailfinger 14 May '08

14 May '08

Add more infrastructure for flashrom ICH9 support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich9/flash.h =================================================================== --- flashrom-ich9/flash.h (Revision 3311) +++ flashrom-ich9/flash.h (Arbeitskopie) @@ -336,6 +336,8 @@ /* chipset_enable.c */ int chipset_flash_enable(void); void print_supported_chipsets(void); +extern int ich9_detected; +extern void *ich_spibar; /* Physical memory mapping device */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) @@ -345,6 +347,7 @@ #endif extern int fd_mem; +extern int fd_mem_uncached; /* debug.c */ extern int verbose; Index: flashrom-ich9/chipset_enable.c =================================================================== --- flashrom-ich9/chipset_enable.c (Revision 3311) +++ flashrom-ich9/chipset_enable.c (Arbeitskopie) @@ -185,33 +185,43 @@ return enable_flash_ich(dev, name, 0xdc); } -static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +void *ich_spibar = NULL; + +static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar) { uint8_t old, new, bbs; uint32_t tmp, gcs; - void *rcba; + void *rcrb; - /* Root Complex Base Address Register (RCBA) */ + /* Read the Root Complex Base Address Register (RCBA) */ tmp = pci_read_long(dev, 0xf0); + /* Calculate the Root Complex Register Block address */ tmp &= 0xffffc000; - printf_debug("Root Complex Base Address Register = 0x%x\n", tmp); - rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); - if (rcba == MAP_FAILED) { + printf_debug("Root Complex Register Block address = 0x%x\n", tmp); + rcrb = mmap(0, 0x3A00, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + if (rcrb == MAP_FAILED) { perror("Can't mmap memory using " MEM_DEV); exit(1); } printf_debug("GCS address = 0x%x\n", tmp + 0x3410); - gcs = *(volatile uint32_t *)(rcba + 0x3410); + gcs = *(volatile uint32_t *)(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); - /* SPIBAR is at RCBA+0x3020 for ICH[78] and RCBA+0x3800 for ICH9. */ - /* printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); */ + munmap(rcrb, 0x3A00); + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + printf_debug("SPIBAR = 0x%lx\n", tmp + spibar); /* TODO: Dump the SPI config regs */ - munmap(rcba, 0x3510); + ich_spibar = mmap(0, 0x200, PROT_READ, MAP_SHARED, fd_mem_uncached, + (off_t)tmp + (off_t)spibar); + if (ich_spibar == MAP_FAILED) { + perror("Can't mmap memory using " MEM_DEV); + exit(1); + } old = pci_read_byte(dev, 0xdc); printf_debug("SPI Read Configuration: "); @@ -230,6 +240,19 @@ return enable_flash_ich_dc(dev, name); } +static int enable_flash_ich78(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 0x3020); +} + +int ich9_detected = 0; + +static int enable_flash_ich9(struct pci_dev *dev, const char *name) +{ + ich9_detected = 1; + return enable_flash_ich_dc_spi(dev, name, 0x3800); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -580,21 +603,21 @@ {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, - {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, - {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, - {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich_dc_spi}, - {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich_dc_spi}, - {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich_dc_spi}, - {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich_dc_spi}, - {0x8086, 0x2918, "Intel ICH9", enable_flash_ich_dc_spi}, - {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich_dc_spi}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich78}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich78}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich78}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich78}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich78}, + {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich78}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich78}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich78}, + {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich78}, + {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9}, + {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9}, + {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9}, + {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, Index: flashrom-ich9/flashrom.c =================================================================== --- flashrom-ich9/flashrom.c (Revision 3311) +++ flashrom-ich9/flashrom.c (Arbeitskopie) @@ -45,6 +45,7 @@ int exclude_start_page, exclude_end_page; int force = 0, verbose = 0; int fd_mem; +int fd_mem_uncached; struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device) { @@ -387,6 +388,12 @@ ". You need to be root."); exit(1); } + /* Open the memory device UNCACHED. That's important for MMIO. */ + if ((fd_mem_uncached = open(MEM_DEV, O_RDWR|O_SYNC)) < 0) { + perror("Error: Can not access memory using " MEM_DEV + ". You need to be root."); + exit(1); + } myusec_calibrate_delay();

2 3

r3314 - trunk/util/flashrom
by svn＠coreboot.org 14 May '08

14 May '08

Author: hailfinger Date: 2008-05-14 16:51:22 +0200 (Wed, 14 May 2008) New Revision: 3314 Modified: trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/flashrom.c Log: Add more infrastructure for flashrom ICH9 support. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-05-14 14:47:32 UTC (rev 3313) +++ trunk/util/flashrom/chipset_enable.c 2008-05-14 14:51:22 UTC (rev 3314) @@ -185,33 +185,37 @@ return enable_flash_ich(dev, name, 0xdc); } -static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +void *ich_spibar = NULL; + +static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar) { uint8_t old, new, bbs; uint32_t tmp, gcs; - void *rcba; + void *rcrb; - /* Root Complex Base Address Register (RCBA) */ + /* Read the Root Complex Base Address Register (RCBA) */ tmp = pci_read_long(dev, 0xf0); + /* Calculate the Root Complex Register Block address */ tmp &= 0xffffc000; - printf_debug("Root Complex Base Address Register = 0x%x\n", tmp); - rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); - if (rcba == MAP_FAILED) { + printf_debug("Root Complex Register Block address = 0x%x\n", tmp); + rcrb = mmap(0, 0x4000, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + if (rcrb == MAP_FAILED) { perror("Can't mmap memory using " MEM_DEV); exit(1); } printf_debug("GCS address = 0x%x\n", tmp + 0x3410); - gcs = *(volatile uint32_t *)(rcba + 0x3410); + gcs = *(volatile uint32_t *)(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); - /* SPIBAR is at RCBA+0x3020 for ICH[78] and RCBA+0x3800 for ICH9. */ - /* printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); */ + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + printf_debug("SPIBAR = 0x%lx\n", tmp + spibar); /* TODO: Dump the SPI config regs */ - munmap(rcba, 0x3510); + ich_spibar = rcrb + spibar; old = pci_read_byte(dev, 0xdc); printf_debug("SPI Read Configuration: "); @@ -230,6 +234,19 @@ return enable_flash_ich_dc(dev, name); } +static int enable_flash_ich78(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 0x3020); +} + +int ich9_detected = 0; + +static int enable_flash_ich9(struct pci_dev *dev, const char *name) +{ + ich9_detected = 1; + return enable_flash_ich_dc_spi(dev, name, 0x3800); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -580,21 +597,21 @@ {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, - {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, - {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, - {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich_dc_spi}, - {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich_dc_spi}, - {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich_dc_spi}, - {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich_dc_spi}, - {0x8086, 0x2918, "Intel ICH9", enable_flash_ich_dc_spi}, - {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich_dc_spi}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich78}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich78}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich78}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich78}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich78}, + {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich78}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich78}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich78}, + {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich78}, + {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9}, + {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9}, + {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9}, + {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-14 14:47:32 UTC (rev 3313) +++ trunk/util/flashrom/flash.h 2008-05-14 14:51:22 UTC (rev 3314) @@ -336,6 +336,8 @@ /* chipset_enable.c */ int chipset_flash_enable(void); void print_supported_chipsets(void); +extern int ich9_detected; +extern void *ich_spibar; /* Physical memory mapping device */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-05-14 14:47:32 UTC (rev 3313) +++ trunk/util/flashrom/flashrom.c 2008-05-14 14:51:22 UTC (rev 3314) @@ -381,8 +381,8 @@ pci_init(pacc); /* Initialize the PCI library */ pci_scan_bus(pacc); /* We want to get the list of devices */ - /* Open the memory device. A lot of functions need it */ - if ((fd_mem = open(MEM_DEV, O_RDWR)) < 0) { + /* Open the memory device UNCACHED. That's important for MMIO. */ + if ((fd_mem = open(MEM_DEV, O_RDWR|O_SYNC)) < 0) { perror("Error: Can not access memory using " MEM_DEV ". You need to be root."); exit(1);

1 0

r3313 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: stepan Date: 2008-05-14 16:47:32 +0200 (Wed, 14 May 2008) New Revision: 3313 Modified: trunk/util/inteltool/inteltool.8 Log: fix license mentioning in manpage (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.8 =================================================================== --- trunk/util/inteltool/inteltool.8 2008-05-14 14:22:59 UTC (rev 3312) +++ trunk/util/inteltool/inteltool.8 2008-05-14 14:47:32 UTC (rev 3313) @@ -52,7 +52,7 @@ .RB "(" http://coreboot.org/Mailinglist ")." .SH LICENCE .B inteltool -is covered by the GNU General Public License (GPL), version 2 or later. +is covered by the GNU General Public License (GPL), version 2. .SH COPYRIGHT (C) 2008 coresystems GmbH .SH AUTHORS

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