coreboot May 2008

coreboot@coreboot.org

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387 discussions

#95: Run coreboot in VirtualBox
by coreboot 09 Dec '14

09 Dec '14

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ It would be nice if we could test coreboot images in VirtualBox, see http://virtualbox.org/. VirtualBox does not (yet) provide a simple mechanism to use a different BIOS in their emulated machines (something like "-L" in qemu). Instead the BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code (an array of bytes, or the like) and merged into the VirtualBox executable. The relevant files are {{{ src/VBox/Devices/PC/DevPcBios.cpp bldprogs/bin2c.c }}} if someone want to hack VirtualBox to easily support using coreboot images instead of their usual BIOS. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95> coreboot <http://www.coreboot.org/>

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filo and usb boot
by Masoud Fatollahy 18 Aug '10

18 Aug '10

Hi, Why is it problem to boot from an usb port when we are using linuxbios and filo. as I can see all usb code are there, what is missing? Thanks, /Masoud

4 8

sony vaio pcg sr1k
by misi e 21 Jul '09

21 Jul '09

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

5 10

[LinuxBIOS] Add initial support for intel i855gme northbridge
by Jon Dufresne 20 Jan '09

20 Jan '09

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

4 4

[LinuxBIOS] A8N5X port
by Robert Millan 21 Nov '08

21 Nov '08

This patch includes config files for the asus/a8n5x port. It is the same as asus/a8n_e with a different pnp layout, so I used #include's whenever possible. System boots and is usable with usb keyboard. works: - serial port - vga (old pci card) - memtest86+ succeeds, but only with Rudolf's patch for unbuffered dimms in K8. Otherwise you get spurious memory corruption. - ide disk - usb doesn't: - ps/2 keyboard - onboard ethernet - vga pci-e card (??) - any other pci card I tried wasn't tested: - sata - game port - onboard audio (not supported by alsa anyway) - ps/2 mouse -- Robert Millan <GPLv2> I know my rights; I want my phone call! <DRM> What use is a phone call, if you are unable to speak? (as seen on /.)

8 27

LZMA magic number
by Myles Watson 29 Sep '08

29 Sep '08

Is there a magic number for LZMA? Should there be? I accidentally used an uncompressed payload with v2 when it expected a compressed payload, and it gave me the message: Decoder scratchpad too small!! Decoding error = 1 I think it would be nicer to have an error like: Payload not compressed with lzma! Myles

5 9

epia-cn patch
by aaron lwe 28 Aug '08

28 Aug '08

> Do you have the dsdt.dsl source? Where did it come from? dsdt.c comes from disassembling the dsl file. the dsl file is extracted from memory when booted with factory bios. I'll add that file if necessary. > Index: src/mainboard/via/epia-cn/fadt.c > =================================================================== > --- src/mainboard/via/epia-cn/fadt.c (revision 0) > +++ src/mainboard/via/epia-cn/fadt.c (revision 0) > @@ -0,0 +1,154 @@ > +/* > + * ACPI - create the Fixed ACPI Description Tables (FADT) > + * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> > Did you change anything in this file? Then I think you should add your copyright, possibly even remove Nick's. yes, I changed the values. > +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ > + acpi_header_t *header=&(fadt->header); > + > + memset((void *)fadt,0,sizeof(acpi_fadt_t)); > + memcpy(header->signature,"FACP",4); > + header->length = 244; > + header->revision = 1; > + memcpy(header->oem_id,"CN700 ",6); > + memcpy(header->oem_table_id,"AWRDACPI",8); > + memcpy(header->asl_compiler_id,"AWRD",4); > We are not Award. What is this about? These values are extracted from factory bios FACP table, so I just keep them. > + header->asl_compiler_revision=0; > + > + fadt->firmware_ctrl=facs; > + fadt->dsdt= dsdt; > + fadt->preferred_pm_profile=0; > + fadt->sci_int=9; > + fadt->smi_cmd = 0x0; > + fadt->acpi_enable = 0x0; > + fadt->acpi_disable = 0x0; > + fadt->s4bios_req = 0x0; > + fadt->pstate_cnt = 0x0; > + > + fadt->pm1a_evt_blk = 0x400; > + fadt->pm1b_evt_blk = 0x0; > + fadt->pm1a_cnt_blk = 0x404; > + fadt->pm1b_cnt_blk = 0x0; > + fadt->pm2_cnt_blk = 0x0; > + fadt->pm_tmr_blk = 0x408; > + fadt->gpe0_blk = 0x420; > + fadt->gpe1_blk = 0x0; > Where do all these magic values come from? By extracting FACP table of the factory BIOS, these values are all in that table. > -/** > - * Configure the bus between the cpu and the northbridge. This might be able to > - * be moved to post-ram code in the future. For the most part, these registers > - * should not be messed around with. These are too complex to explain short of > - * copying the datasheets into the comments, but most of these values are from > - * the BIOS Porting Guide, so they should work on any board. If they don't, > - * try the values from your factory BIOS. > - * > - * TODO: Changing the DRAM frequency doesn't work (hard lockup) > - * > - * @param dev The northbridge's CPU Host Interface (D0F2) > - */ > static void c7_cpu_setup(device_t dev) > { > Hey, please don't remove doxygen. :) Oh...my bad ;-) > Index: src/northbridge/via/cn700/northbridge.c > =================================================================== > --- src/northbridge/via/cn700/northbridge.c (revision 3300) > +++ src/northbridge/via/cn700/northbridge.c (working copy) > @@ -1,6 +1,8 @@ > /* > * This file is part of the coreboot project. > * > + * Copyright (C) 2008 VIA Technologies, Inc. > + * Copyright (C) 2008 Aaron Lwe <aaron.lwe(a)gmail.com> > How is VIA involved in this? I'm a VIA employee, so I think I should add VIA here, sorry not making this clear. >Thanks a lot for the patch! I guess Corey and Bari will have a go at it but I'll try to test as well. Thanks. If dram didn't work right, try to change the values of D0F2 registers in c7_cpu_setup to be the same as the facotry BIOS set. -Aaron

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[v3] VT8237R support
by Corey Osgood 28 Aug '08

28 Aug '08

See attached. Not perfect, but enough to get started with.

5 11

[PATCH] v3: missing 640k-1024k mem hole for i440bxemulation
by Carl-Daniel Hailfinger 22 Aug '08

22 Aug '08

i440bxemulation is missing the 640k-1024k mem hole. geodelx has the hole. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c (Revision 644) +++ LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -59,7 +59,10 @@ mc_dev = dev->link[0].children; if (mc_dev) { idx = 10; - ram_resource(dev, idx++, 0, tolmk); + /* 0 .. 640 KB */ + ram_resource(dev, idx++, 0, 640); + /* 1 MB .. (Systop - 1 MB) (in KB) */ + ram_resource(dev, idx++, 1024, tolmk - 1024); } phase4_assign_resources(&dev->link[0]); } -- http://www.hailfinger.org/

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[PATCH] [RFC] v3: CS5536 cleanup
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Clean up Geode companion chip CS5536 code and improve VPCI hiding debug message. This also eliminates a few dev_find_pci_device(). I'm not happy with the new code yet. hide_vpci() should have a variant which takes a struct device *. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Revision 676) +++ LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -175,8 +175,7 @@ static void enable_ide_nand_flash_header(void) { /* Tell VSA to use FLASH PCI header. Not IDE header. */ - outl(0x80007A40, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + hide_vpci(0x800079C4); } #define RTC_CENTURY 0x32 @@ -240,16 +239,13 @@ * * @param sb Southbridge config structure. */ -static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb) +static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb, + struct device *dev) { struct msr msr; u16 addr = 0; u32 gpio_addr; - struct device *dev; - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); - gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); gpio_addr &= ~1; /* Clear I/O bit */ printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); @@ -418,7 +414,7 @@ { u32 *bar; struct msr msr; - struct device *dev; + struct device *dev, *otg_dev; dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); @@ -440,9 +436,9 @@ *(bar + HCCPARAMS) = 0x00005012; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, + otg_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCMUX) &= PUEN_SET; @@ -472,9 +468,7 @@ *(bar + UDCDEVCTL) |= UDC_SD_SET; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCCTL) |= PADEN_SET; *(bar + UOCCAP) |= APU_SET; @@ -482,15 +476,8 @@ } /* Disable virtual PCI UDC and OTG headers. */ - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); - - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); + hide_vpci(0x80007e00); /* UDC */ + hide_vpci(0x80007f00); /* OTG */ } /** @@ -603,9 +590,19 @@ static void hide_vpci(u32 vpci_devid) { - /* Hide unwanted virtual PCI device. */ - printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n", - vpci_devid); + /* Hide unwanted virtual PCI device. + * bits 0 -> 1 zero + * bits 2 -> 7 target dword within the target function + * (zero if we're disabling entire pci devices) + * bits 8 -> 10 target function of the device + * bits 11 -> 15 target pci device + * bits 16 -> 23 pci bus + * bits 24 -> 30 reserved and set to zero + * bit 31 triggers the config cycle + */ + printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", + vpci_devid, (vpci_devid >> 16) & 0xff, + (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7); outl(vpci_devid + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } @@ -630,7 +627,7 @@ setup_i8259(); lpc_init(sb); - uarts_init(sb); + uarts_init(sb, dev); if (sb->enable_gpio_int_route) { printk(BIOS_SPEW, "cs5536: call vr_write\n");

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coreboot May 2008