coreboot May 2008

coreboot@coreboot.org

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[PATCH] v3: convert stage2 and initram makefile rules from object to source files
by Carl-Daniel Hailfinger 02 Aug '08

02 Aug '08

Convert stage2 and initram makefile rules from object to source files. This creates a clearer distinction between source files in the source tree we want to have compiled and indirectly created object/source files in the object tree. It also will make enable us to move to whole-program optimization/compilation which should yield substantial size savings. Then again, we may be able to do that without the makefile conversion as well. This is a RFC, not to be applied immediately. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Arbeitskopie) @@ -21,7 +21,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) -STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o Index: LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Arbeitskopie) @@ -20,6 +20,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) -STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c endif Index: LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Arbeitskopie) @@ -25,6 +25,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o # Always add to variables, as there could be more than one Super I/O. -STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o +STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c endif Index: LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Arbeitskopie) @@ -24,6 +24,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o # Always add to variables, as there could be more than one Super I/O. -STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o +STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c endif Index: LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Arbeitskopie) @@ -21,12 +21,12 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = +STAGE2_MAINBOARD_SRC = $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Arbeitskopie) @@ -21,12 +21,12 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = +STAGE2_MAINBOARD_SRC = $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Arbeitskopie) @@ -28,10 +28,10 @@ # directory and is built from what was auto.c in v2. # -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c -STAGE2_MAINBOARD_OBJ = vga.o +STAGE2_MAINBOARD_SRC = vga.c # # VPD or SIP ROM or... how does NVIDIA call it? Index: LinuxBIOSv3-makefilerewrite/device/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/device/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/device/Makefile (Arbeitskopie) @@ -24,6 +24,6 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ -STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \ - pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o +STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \ + pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c Index: LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Arbeitskopie) @@ -21,9 +21,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) -STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ - $(obj)/northbridge/amd/geodelx/vsmsetup.o \ - $(obj)/util/x86emu/vm86_gdt.o \ - $(obj)/northbridge/amd/geodelx/grphinit.o +STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \ + $(src)/northbridge/amd/geodelx/vsmsetup.c \ + $(src)/util/x86emu/vm86_gdt.c \ + $(src)/northbridge/amd/geodelx/grphinit.c endif Index: LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Arbeitskopie) @@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y) -STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o +STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c endif Index: LinuxBIOSv3-makefilerewrite/arch/x86/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Arbeitskopie) @@ -179,27 +179,32 @@ # TODO: This should be compressed with the default compressor. # -STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ - compute_ip_checksum.o string.o +STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \ + compute_ip_checksum.c string.c -STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o -STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o -STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o +STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c +STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c +STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c ifeq ($(CONFIG_PIRQ_TABLE),y) -STAGE2_ARCH_X86_OBJ += pirq_routing.o +STAGE2_ARCH_X86_SRC += pirq_routing.c endif STAGE2_DYNAMIC_OBJ = statictree.o -STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \ - $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \ - $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \ - $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \ - $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) +STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \ + $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \ + $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \ + $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC)) -STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ) +STAGE2_SRC += $(STAGE2_CHIPSET_SRC) +STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC)) + +# This one is special, but only due to slightly incorrect rules and dependencies. +# Don't change the dependencies for now. +STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) + ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) # x86emu wants libgcc @@ -215,7 +220,7 @@ STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ)) -$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) +$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC) $(Q)# leave a .o with full symbols in it for debugging. $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \ @@ -249,9 +254,9 @@ $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ -$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) +$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC) $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" - $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ -- http://www.hailfinger.org/

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superiotool: add dump support for Winbond (NSC) PC87427
by Tom Sylla 16 Jul '08

16 Jul '08

Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware. Signed-off-by: Tom Sylla <tsylla(a)gmail.com> Index: nsc.c =================================================================== --- nsc.c (revision 3358) +++ nsc.c (working copy) @@ -408,6 +408,65 @@ {EOT}}}, {0xf2, "PC87427", { /* SRID[7..5] is marked as "not applicable for the PC87427". */ + {NOLDN, NULL, + {0x10,0x12,0x13,0x1d,0x20,0x21,0x22,0x23,0x24,0x25, + 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, + EOT}, + {0x00,0x00,0x00,0x00,0xf2,0x11,0xa0,MISC,MISC,MISC, + 0x02,NANA,0x00,MISC,0x00,0x00,MISC,MISC,RSVD,RSVD, + EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x70, + 0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x04,0x04,EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40, + EOT}}, + {0x7, "GPIO", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x9, "Fan Monitor and Control (FMC)", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x19,0x06, + EOT}}, + {0xa, "Watchdog timer (WDT)", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xf, "X-Bus", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc, + 0xfd,0xfe,0xff,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x80,0x10,EOT}}, + {0x10, "Real-time clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + 0xf1,0xf2,0xf3,0xf6,0xf7,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00, + 0x00,0x00,0x00,MISC,0x00,EOT}}, + {0x14, "Health Monitoring and Control (HMC)", + {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75, + 0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, + 0x05,EOT}}, {EOT}}}, {0xf3, "PC87373", { {EOT}}}, Index: superiotool.h =================================================================== --- superiotool.h (revision 3358) +++ superiotool.h (working copy) @@ -51,7 +51,7 @@ #define NANA -3 /* Not Available */ #define RSVD -4 /* Reserved */ #define MISC -5 /* Needs special comment in output */ -#define MAXLDN 0x10 /* Biggest LDN */ +#define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ #define MAXNUMIDX 170 /* Maximum number of indexes */ #define IDXSIZE (MAXNUMIDX + 1)

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[PATCH] filo: Add missing Artec license headers
by Uwe Hermann 11 Jul '08

11 Jul '08

See patch. I assume the *.h files and Makefile were also written by Andrei Birjukov <andrei.birjukov(a)artecdesign.ee> as is the rest of the new code, please correct me if that's wrong. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

some thoughts on dts vs. Kconfig vs. makefiles vs. C code
by ron minnich 11 Jul '08

11 Jul '08

I have no idea if this helps. But there's been discussion of "DRAM settings in DTS" and "where does CARBASE go" and so on, so I think we need to try to document some rules. Here is a first cut. thanks ron

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[PATCH] buildrom: Update kconfig to recent version
by Uwe Hermann 02 Jul '08

02 Jul '08

See patch. The actual patch is buildrom_update_kconfig.patch.gz but that's huge and totally unreadable so I recommend reviewing buildrom_update_kconfig_makefile.patch That's the only change to the buildrom code itself, the rest is just replacing the whole scripts/kconfig/ dir with the new kconfig. I used the coreinfo kconfig/ with only a handful of string replacements a la s/coreinfo/buildrom/ so the diff to coreinfo's kconfig is tiny. I did some ad-hoc testing with this, tried various kconfig targets (menuconfig, xconfig, gconfig, ...) and various buildrom builds and it seems to work fine so far, but some more testing by others is highly appreciated. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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flashrom: Move options -s -e to -S -E and -E to -e.
by Peter Stuge 02 Jul '08

02 Jul '08

NOTE! This will break all scripts that erase flash chips automatically. But better now than post 1.0. //Peter

2 2

Re: [coreboot] #88: Add UHCI/OHCI/EHCI support to GRUB2
by joe＠settoplinux.org 22 Jun '08

22 Jun '08

#88: Add UHCI/OHCI/EHCI support to GRUB2 ----------------------------+----------------------------------------------- Reporter: uwe | Owner: oxygene Type: enhancement | Status: new Priority: critical | Milestone: Port GRUB2 to coreboot Component: filo | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by stepan): * owner: => oxygene -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/88#comment:2> coreboot <http://www.coreboot.org/> I can't wait for this to happen :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 1

RCA RM4100 vs Thomson IP1000
by Joseph Smith 22 Jun '08

22 Jun '08

Need some suggestions/help. I think I figured out why coreboot for RCA RM4100 will not work on the Thomson IP1000. The only difference is that the IP1000 only has 64MB of onboard memory and the RCA RM4100 has 128MB of onboard memory. coreboot chokes because there is no onboard spd, so the spd settings are manually set via an array (see spd_table.h). If you want to see a high res pic of the boards, they are on my site: www.settoplinux.org So I guess with that being the only difference, should we create a new target for the Thomson IP1000 ??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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flashrom verify fails, CK804, MCP55
by Tiago Marques 21 Jun '08

21 Jun '08

On two boards, one MCP55 based and another CK804, if I flash the proprietary BIOS with: flasrom -wv bios.bin Verification fails and if I try to boot, it doesn't. Have to flash the BIOS in another board based on K8T890 that I have. In that one all works fine, with both BIOS chips I have - one winbond and a PMC. Haven't tried flashing coreboot due to lack of support. Since the chipsets are support, this isn't supposed to happen, right? Best regards, Tiago Marques On 1/27/08, Stefan Reinauer <stepan(a)coresystems.de> wrote: > * Tiago Marques <tiagomnm(a)gmail.com> [080127 16:21]: > > Hi. > > Both failed, tried with two different BIOS chips. > > Flashing with AWDFlash works fine though. > > Had to flash it again in a VIA K8T890 board, which works flawlessly. > > Any ideas, fix? > > What's the problem? > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info(a)coresystems.de • http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg • HRB 7656 > Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 >

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Thin Client Compaq Evo T20
by Philip Loewen 17 Jun '08

17 Jun '08

I'm thinking about trying coreboot on the Compaq Evo T20 thin client. This is a Geode GX1 machine with CS5530 companion chip and National Semiconductor DP83815 ethernet card. It has 48MB of flash memory and 64 MB of RAM (soldered). The superiotool from coreboot can't find any evidence of super-I/O. The mainboard contains a chip that looks like a socketed PLCC BIOS chip, Winbond 29C020... with a sticker on top giving credit to Wyse Tech 01'V9.0. The keyboard and mouse use a USB 1.1 interface. `lspci` says 00:13.0 USB Controller: Compaq ... ZFMicro Chipset USB (rev 06) Expert advice on these questions would be very welcome: 1. Does coreboot support this setup? (Particularly the USB devices?) 2. What advantages will coreboot offer over the manufacturer's original BIOS? E.g., will I get a BIOS control screen I can use to change settings until they work? 3. I don't have too much time to indulge in hardware hacking. I'm hoping for an approach that would not require me to even open the Evo's case! And this might be possible: like the Wyse Winterm, the Evo boots from on-board flash memory that can be rewritten using 'netxfer'. One of the files that netxfer delivers to the thin client is called "the BIOS" by people who know these things. Tradition among users like me is to treat that file with great respect, making sure an exact copy of the factory original is present whenever other files in the bundle are replaced. Here's my main question: can I replace that file (named ulc_code.ce, size 4 MB) with something from coreboot and use 'netxfer' to get a working alternative to the factory BIOS? What can I test before trying this to make sure I don't turn my little device into a brick? Are there some magic bytes or signatures to look for in the factory-file to confirm that it really is some kind of BIOS, and that program execution starts from the same location in the commercial file as it will in coreboot? What else should I be watching for? Thanks in advance for any comments or pointers. Philip

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coreboot May 2008