coreboot May 2008

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r3312 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: stepan Date: 2008-05-14 16:22:59 +0200 (Wed, 14 May 2008) New Revision: 3312 Modified: trunk/util/inteltool/inteltool.c Log: trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-14 13:52:50 UTC (rev 3311) +++ trunk/util/inteltool/inteltool.c 2008-05-14 14:22:59 UTC (rev 3312) @@ -39,8 +39,25 @@ #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 +#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +static const struct { + uint16_t vendor_id, device_id; + char * name; +} supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } +}; + + + + #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) int fd_mem; @@ -117,6 +134,7 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7MDH: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); @@ -134,7 +152,7 @@ size = ARRAY_SIZE(ich0_gpio_registers); break; case 0x1234: // Dummy for non-existent functionality - printf("Error: This southbridge does not have GPIOBASE.\n"); + printf("This southbridge does not have GPIOBASE.\n"); return 1; default: printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); @@ -179,13 +197,14 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7MDH: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: - printf("Error: This southbridge does not have RCBA.\n"); + printf("This southbridge does not have RCBA.\n"); return 1; default: printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); @@ -220,10 +239,11 @@ switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7MDH: pmbase = pci_read_word(sb, 0x40) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality - printf("Error: This southbridge does not have PMBASE.\n"); + printf("This southbridge does not have PMBASE.\n"); return 1; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); @@ -256,7 +276,7 @@ mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have MCHBAR.\n"); + printf("This northbrigde does not have MCHBAR.\n"); return 1; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); @@ -298,7 +318,7 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have EPBAR.\n"); + printf("This northbrigde does not have EPBAR.\n"); return 1; default: printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n"); @@ -340,7 +360,7 @@ dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have DMIBAR.\n"); + printf("This northbrigde does not have DMIBAR.\n"); return 1; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); @@ -692,18 +712,6 @@ {0, 0, 0, 0} }; - struct { - uint16_t vendor_id, device_id; - char * name; - } supported_chips_list[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } - }; - while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", long_options, &option_index)) != EOF) { switch (opt) {

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r3311 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: stepan Date: 2008-05-14 15:52:50 +0200 (Wed, 14 May 2008) New Revision: 3311 Modified: trunk/util/inteltool/inteltool.8 trunk/util/inteltool/inteltool.c Log: trivial patch to fix options. Thanks to Uwe Hermann for the hint! Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.8 =================================================================== --- trunk/util/inteltool/inteltool.8 2008-05-14 12:22:38 UTC (rev 3310) +++ trunk/util/inteltool/inteltool.8 2008-05-14 13:52:50 UTC (rev 3311) @@ -2,7 +2,7 @@ .SH NAME inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters .SH SYNOPSIS -.B inteltool \fR[\fB\-vh?grpmedPM\fR] +.B inteltool \fR[\fB\-vh?grpmedPMa\fR] .SH DESCRIPTION .B inteltool is a handy little tool for dumping the configuration space of Intel(R) Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-14 12:22:38 UTC (rev 3310) +++ trunk/util/inteltool/inteltool.c 2008-05-14 13:52:50 UTC (rev 3311) @@ -646,7 +646,7 @@ void print_usage(const char *name) { - printf("usage: %s [-vh?grpmedPM]\n", name); + printf("usage: %s [-vh?grpmedPMa]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -658,6 +658,7 @@ " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" + " -a | --all: dump all known registers\n" "\n"); exit(1); } @@ -703,7 +704,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; - while ((opt = getopt_long(argc, argv, "vh?gmrpedPca", + while ((opt = getopt_long(argc, argv, "vh?grpmedPMa", long_options, &option_index)) != EOF) { switch (opt) { case 'v':

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[PATCH] flashrom: Add the Intel 6300ESB chipset
by Dominik Geyer 14 May '08

14 May '08

Adds the Intel 6300ESB as known chipset to the chipset enables-structure. Signed-off-by: Claus Gindhart <claus.gindhart <at> kontron.com> --- coreboot-v2.orig/util/flashrom/chipset_enable.c 2008-05-14 10:20:23.000000000 +0200 +++ coreboot-v2/util/flashrom/chipset_enable.c 2008-05-14 11:39:45.000000000 +0200 @@ -577,6 +577,7 @@ {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e}, {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, + {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, -- Dominik Geyer - SW R&D - Kontron Modular Computers Sudetenstraße 7 D - 87600 Kaufbeuren Tel.: +49 (0) 83 41 / 803 -395 dominik.geyer(a)kontron.com Kontron Modular Computers GmbH Geschaeftsfuehrer / Managing Directors: Ulrich Gehrmann, Thomas Sabisch Sitz der Gesellschaft / Registered Office: Kaufbeuren, Rechtsform / Legal: GmbH Amtsgericht / Local District Court Kempten, HRB Nr. / Trade Register No. 6195 The information contained in this document is CONFIDENTIAL and property of Kontron. Any unauthorized review, use, disclosure or distribution is prohibited without express written consent of Kontron. If you are not the intended recipient, please contact the sender and destroy all copies of the original message and enclosed attachments. Diese E-Mail enthält vertrauliche und/oder rechtlich geschützte Informationen und ist Eigentum von Kontron. Die Verwendung und Weitergabe von jeglichen Inhalten ist ohne ausdrückliche schriftliche Genehmigung von Kontron strikt untersagt. Wenn Sie diese E-Mail irrtümlich erhalten haben, informieren Sie bitte sofort den Absender und vernichten diese Mail und enthaltene Dokumente.

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r3310 - trunk/util/flashrom
by svn＠coreboot.org 14 May '08

14 May '08

Author: hailfinger Date: 2008-05-14 14:22:38 +0200 (Wed, 14 May 2008) New Revision: 3310 Modified: trunk/util/flashrom/chipset_enable.c Log: Add the Intel 6300ESB as known chipset to the chipset struct enables. Signed-off-by: Claus Gindhart <claus.gindhart(a)kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-05-14 12:09:31 UTC (rev 3309) +++ trunk/util/flashrom/chipset_enable.c 2008-05-14 12:22:38 UTC (rev 3310) @@ -577,6 +577,7 @@ {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e}, {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, + {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi},

1 0

r3309 - trunk/util/flashrom
by svn＠coreboot.org 14 May '08

14 May '08

Author: hailfinger Date: 2008-05-14 14:09:31 +0200 (Wed, 14 May 2008) New Revision: 3309 Modified: trunk/util/flashrom/flashchips.c Log: Fix crash caused by division by zero for unknown flash chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-14 12:03:06 UTC (rev 3308) +++ trunk/util/flashrom/flashchips.c 2008-05-14 12:09:31 UTC (rev 3309) @@ -136,11 +136,11 @@ {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, - {"EON", "unknown SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 0, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"Macronix", "unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"PMC", "unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"SST", "unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"ST", "unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, {NULL,} };

1 0

[PATCH] flashrom: Check the JEDEC vendor ID for correct parity
by Carl-Daniel Hailfinger 14 May '08

14 May '08

Check the JEDEC vendor ID for correct parity. Flash chips which can be detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spijedecparity/flash.h =================================================================== --- flashrom-spijedecparity/flash.h (Revision 3306) +++ flashrom-spijedecparity/flash.h (Arbeitskopie) @@ -396,6 +396,7 @@ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios); /* jedec.c */ +uint8_t oddparity(uint8_t val); void toggle_ready_jedec(volatile uint8_t *dst); void data_polling_jedec(volatile uint8_t *dst, uint8_t data); void unprotect_jedec(volatile uint8_t *bios); Index: flashrom-spijedecparity/jedec.c =================================================================== --- flashrom-spijedecparity/jedec.c (Revision 3306) +++ flashrom-spijedecparity/jedec.c (Arbeitskopie) @@ -27,6 +27,14 @@ #define MAX_REFLASH_TRIES 0x10 +/* Check one byte for odd parity */ +uint8_t oddparity(uint8_t val) +{ + val = (val ^ (val >> 4)) & 0xf; + val = (val ^ (val >> 2)) & 0x3; + return (val ^ (val >> 1)) & 0x1; +} + void toggle_ready_jedec(volatile uint8_t *dst) { unsigned int i = 0; @@ -123,7 +131,10 @@ *(volatile uint8_t *)(bios + 0x5555) = 0xF0; myusec_delay(40); - printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, largeid1, largeid2); + printf_debug("%s: id1 0x%x, id2 0x%x", __FUNCTION__, largeid1, largeid2); + if (!oddparity(id1)) + printf_debug(", id1 parity violation"); + printf_debug("\n"); if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) return 1; Index: flashrom-spijedecparity/spi.c =================================================================== --- flashrom-spijedecparity/spi.c (Revision 3306) +++ flashrom-spijedecparity/spi.c (Arbeitskopie) @@ -71,8 +71,12 @@ uint32_t manuf_id; uint32_t model_id; if (!spi_rdid(readarr)) { + if (!oddparity(readarr[0])) + printf_debug("RDID byte 0 parity violation.\n"); /* Check if this is a continuation vendor ID */ if (readarr[0] == 0x7f) { + if (!oddparity(readarr[1])) + printf_debug("RDID byte 1 parity violation.\n"); manuf_id = (readarr[0] << 8) | readarr[1]; model_id = readarr[2]; } else {

2 2

r3308 - trunk/util/flashrom
by svn＠coreboot.org 14 May '08

14 May '08

Author: hailfinger Date: 2008-05-14 14:03:06 +0200 (Wed, 14 May 2008) New Revision: 3308 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/jedec.c trunk/util/flashrom/spi.c Log: Check the JEDEC vendor ID for correct parity. Flash chips which can be detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-14 11:38:22 UTC (rev 3307) +++ trunk/util/flashrom/flash.h 2008-05-14 12:03:06 UTC (rev 3308) @@ -396,6 +396,7 @@ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios); /* jedec.c */ +uint8_t oddparity(uint8_t val); void toggle_ready_jedec(volatile uint8_t *dst); void data_polling_jedec(volatile uint8_t *dst, uint8_t data); void unprotect_jedec(volatile uint8_t *bios); Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2008-05-14 11:38:22 UTC (rev 3307) +++ trunk/util/flashrom/jedec.c 2008-05-14 12:03:06 UTC (rev 3308) @@ -27,6 +27,14 @@ #define MAX_REFLASH_TRIES 0x10 +/* Check one byte for odd parity */ +uint8_t oddparity(uint8_t val) +{ + val = (val ^ (val >> 4)) & 0xf; + val = (val ^ (val >> 2)) & 0x3; + return (val ^ (val >> 1)) & 0x1; +} + void toggle_ready_jedec(volatile uint8_t *dst) { unsigned int i = 0; @@ -123,7 +131,10 @@ *(volatile uint8_t *)(bios + 0x5555) = 0xF0; myusec_delay(40); - printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, largeid1, largeid2); + printf_debug("%s: id1 0x%x, id2 0x%x", __FUNCTION__, largeid1, largeid2); + if (!oddparity(id1)) + printf_debug(", id1 parity violation"); + printf_debug("\n"); if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) return 1; Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-05-14 11:38:22 UTC (rev 3307) +++ trunk/util/flashrom/spi.c 2008-05-14 12:03:06 UTC (rev 3308) @@ -71,8 +71,12 @@ uint32_t manuf_id; uint32_t model_id; if (!spi_rdid(readarr)) { + if (!oddparity(readarr[0])) + printf_debug("RDID byte 0 parity violation.\n"); /* Check if this is a continuation vendor ID */ if (readarr[0] == 0x7f) { + if (!oddparity(readarr[1])) + printf_debug("RDID byte 1 parity violation.\n"); manuf_id = (readarr[0] << 8) | readarr[1]; model_id = readarr[2]; } else {

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r3307 - trunk/util/inteltool
by svn＠coreboot.org 14 May '08

14 May '08

Author: stepan Date: 2008-05-14 13:38:22 +0200 (Wed, 14 May 2008) New Revision: 3307 Modified: trunk/util/inteltool/inteltool.c Log: Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7 have different register meanings, so they get their own lookup tables. This is a trivial patch. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2008-05-14 04:27:02 UTC (rev 3306) +++ trunk/util/inteltool/inteltool.c 2008-05-14 11:38:22 UTC (rev 3307) @@ -34,6 +34,10 @@ /* Tested Chipsets: */ #define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_ICH 0x2410 +#define PCI_DEVICE_ID_INTEL_ICH0 0x2420 +#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 +#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 @@ -45,36 +49,90 @@ typedef struct { uint32_t hi, lo; } msr_t; typedef struct { uint16_t addr; int size; char *name; } io_register_t; + +static const io_register_t ich0_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "GPO_TTL" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "RESERVED" }, + { 0x34, 4, "RESERVED" }, + { 0x38, 4, "RESERVED" }, + { 0x3C, 4, "RESERVED" } +}; + +static const io_register_t ich4_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "GPO_TTL" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "RESERVED" } +}; + +static const io_register_t ich7_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "RESERVED" } +}; + int print_gpios(struct pci_dev *sb) { - int i; + int i, size; uint16_t gpiobase; + const io_register_t *gpio_registers; - io_register_t ich7_gpio_registers[] = { - { 0x00, 4, "GPIO_USE_SEL" }, - { 0x04, 4, "GP_IO_SEL" }, - { 0x08, 4, "RESERVED" }, - { 0x0c, 4, "GP_LVL" }, - { 0x10, 4, "RESERVED" }, - { 0x14, 4, "RESERVED" }, - { 0x18, 4, "GPO_BLINK" }, - { 0x1c, 4, "RESERVED" }, - { 0x20, 4, "RESERVED" }, - { 0x24, 4, "RESERVED" }, - { 0x28, 4, "RESERVED" }, - { 0x2c, 4, "GPI_INV" }, - { 0x30, 4, "GPIO_USE_SEL2" }, - { 0x34, 4, "GP_IO_SEL2" }, - { 0x38, 4, "GP_LVL2" }, - { 0x3C, 4, "RESERVED" } - }; - printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_ICH7: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich7_gpio_registers; + size = ARRAY_SIZE(ich7_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH4: + case PCI_DEVICE_ID_INTEL_ICH4M: + gpiobase = pci_read_word(sb, 0x58) & 0xfffc; + gpio_registers = ich4_gpio_registers; + size = ARRAY_SIZE(ich4_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_ICH: + case PCI_DEVICE_ID_INTEL_ICH0: + gpiobase = pci_read_word(sb, 0x58) & 0xfffc; + gpio_registers = ich0_gpio_registers; + size = ARRAY_SIZE(ich0_gpio_registers); + break; case 0x1234: // Dummy for non-existent functionality printf("Error: This southbridge does not have GPIOBASE.\n"); return 1; @@ -85,25 +143,25 @@ printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase); - for (i=0; i<ARRAY_SIZE(ich7_gpio_registers); i++) { - switch (ich7_gpio_registers[i].size) { + for (i=0; i<size; i++) { + switch (gpio_registers[i].size) { case 4: printf("gpiobase+0x%04x: 0x%08x (%s)\n", - ich7_gpio_registers[i].addr, - inl(gpiobase+ich7_gpio_registers[i].addr), - ich7_gpio_registers[i].name); + gpio_registers[i].addr, + inl(gpiobase+gpio_registers[i].addr), + gpio_registers[i].name); break; case 2: printf("gpiobase+0x%04x: 0x%04x (%s)\n", - ich7_gpio_registers[i].addr, - inw(gpiobase+ich7_gpio_registers[i].addr), - ich7_gpio_registers[i].name); + gpio_registers[i].addr, + inw(gpiobase+gpio_registers[i].addr), + gpio_registers[i].name); break; case 1: printf("gpiobase+0x%04x: 0x%02x (%s)\n", - ich7_gpio_registers[i].addr, - inb(gpiobase+ich7_gpio_registers[i].addr), - ich7_gpio_registers[i].name); + gpio_registers[i].addr, + inb(gpiobase+gpio_registers[i].addr), + gpio_registers[i].name); break; } } @@ -123,7 +181,10 @@ case PCI_DEVICE_ID_INTEL_ICH7: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_ICH: + case PCI_DEVICE_ID_INTEL_ICH0: + case PCI_DEVICE_ID_INTEL_ICH4: + case PCI_DEVICE_ID_INTEL_ICH4M: printf("Error: This southbridge does not have RCBA.\n"); return 1; default: @@ -635,7 +696,11 @@ char * name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" } + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; while ((opt = getopt_long(argc, argv, "vh?gmrpedPca",

1 0

r3306 - trunk/util/flashrom
by svn＠coreboot.org 14 May '08

14 May '08

Author: hailfinger Date: 2008-05-14 06:27:02 +0200 (Wed, 14 May 2008) New Revision: 3306 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Add lots of ATMEL SPI flash chips to flash.h. Add a few flashchips already mentioned in flash.h to flashchips.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-13 23:03:12 UTC (rev 3305) +++ trunk/util/flashrom/flash.h 2008-05-14 04:27:02 UTC (rev 3306) @@ -66,7 +66,7 @@ #define TEST_OK_READ (1<<1) #define TEST_OK_ERASE (1<<2) #define TEST_OK_WRITE (1<<3) -#define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE) +#define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE) #define TEST_OK_MASK 0x0f #define TEST_BAD_PROBE (1<<4) @@ -103,6 +103,18 @@ #define ASD_AE49F2008 0x52 #define ATMEL_ID 0x1F /* Atmel */ +#define AT_25DF021 0x4300 +#define AT_25DF041A 0x4401 +#define AT_25DF081 0x4502 +#define AT_25DF161 0x4602 +#define AT_25DF321 0x4700 /* also 26DF321 */ +#define AT_25DF321A 0x4701 +#define AT_25DF641 0x4800 +#define AT_26DF041 0x4400 +#define AT_26DF081 0x4500 /* guessed, no datasheet available */ +#define AT_26DF081A 0x4501 +#define AT_26DF161 0x4600 +#define AT_26DF161A 0x4601 #define AT_29C040A 0xA4 #define AT_29C020 0xDA #define AT_49F002N 0x07 /* for AT49F002(N) */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-13 23:03:12 UTC (rev 3305) +++ trunk/util/flashrom/flashchips.c 2008-05-14 04:27:02 UTC (rev 3306) @@ -49,9 +49,10 @@ {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, - {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L1605", MX_ID, MX_25L1605, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, #ifndef DISABLE_DOC {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, TEST_UNTESTED, probe_md2802, erase_md2802, write_md2802, read_md2802}, @@ -92,13 +93,13 @@ {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b},

1 0

epia-cn patch
by aaron lwe 14 May '08

14 May '08

Hi, This is a working patch for epia-cn which uses C7 + CN700 + VT8237R. Signed-off-by: Aaron Lwe <aaron.lwe(a)gmail.com> -Aaron

5 6

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coreboot May 2008