coreboot May 2008

coreboot@coreboot.org

79 participants
387 discussions

r3322 - in trunk/coreboot-v2/src: mainboard/rca/rm4100 northbridge/intel/i82830
by svn＠coreboot.org 15 May '08

15 May '08

Author: linux_junkie Date: 2008-05-15 15:44:33 +0200 (Thu, 15 May 2008) New Revision: 3322 Added: trunk/coreboot-v2/src/northbridge/intel/i82830/memory_initialized.c Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c Log: This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2008-05-15 03:24:43 UTC (rev 3321) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/auto.c 2008-05-15 13:44:33 UTC (rev 3322) @@ -33,7 +33,9 @@ #include "ram/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" +#include "northbridge/intel/i82830/memory_initialized.c" #include "southbridge/intel/i82801xx/i82801xx.h" +#include "southbridge/intel/i82801xx/i82801xx_reset.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" @@ -95,6 +97,9 @@ if (bist == 0) early_mtrr_init(); + if (memory_initialized()) { + hard_reset(); + } enable_smbus(); @@ -103,6 +108,9 @@ uart_init(); console_init(); + /* Prevent the TCO timer from rebooting us */ + i82801xx_halt_tco_timer(); + /* Halt if there was a built in self test failure. */ report_bist_failure(bist); @@ -114,6 +122,5 @@ /* ram_check(0, 640 * 1024); */ /* ram_check(130048 * 1024, 131072 * 1024); */ - i82801xx_halt_tco_timer(); ac97_io_enable(); } Added: trunk/coreboot-v2/src/northbridge/intel/i82830/memory_initialized.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/memory_initialized.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/memory_initialized.c 2008-05-15 13:44:33 UTC (rev 3322) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include "i82830.h" +#define NB_DEV PCI_DEV(0, 0, 0) + +static inline int memory_initialized(void) +{ + u32 drc; + drc = pci_read_config32(NB_DEV, DRC); + return (drc & (1<<29)); +}

1 0

Trac spam bots at work
by Gregg C Levine 15 May '08

15 May '08

Hello! I just explored a series of trac messages to the list. It seems it's been invaded by another spam 'bot. I am not including examples of this trash in the message. Obviously all of you have seen them and will be taking appropriate action. The ticket number chosen for starters was #86 for example. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

1 0

Add support for SPI-Chips on ICH9 to flash rom / please delete the last mail
by Claus Gindhart 15 May '08

15 May '08

This patch adds support for the SPI Chips Atmel AT25DF32, ST M25P80, ST M25P16, M25P32, ST M25P64 attached to the ICH9. Because chipset plays an important role in communicating with these chips, it was not possible to integrate this support into the already existing spi.c This module was tested with the devices as mentioned above, but it should be easy to expand it for other SPI chips attached to an ICH. Signed-off-by: Claus Gindhart <claus.gindhart(a)kontron.com> --- Oops, if have forgotten to replace the patch file; here it is Fixed it to fulfil feedback of Uwe Hermann and Peter Stuge, related to coreboot coding conventions. Mit freundlichen Grüßen / Best regards Claus Gindhart SW R&D Kontron Modular Computers phone :++49 (0)8341-803-374 mailto:claus.gindhart@kontron.com http://www.kontron.com Kontron Modular Computers GmbH Geschaeftsfuehrer / Managing Directors: Ulrich Gehrmann, Thomas Sabisch Sitz der Gesellschaft / Registered Office: Kaufbeuren, Rechtsform / Legal: GmbH Amtsgericht / Local District Court Kempten, HRB Nr. / Trade Register No. 6195 The information contained in this document is CONFIDENTIAL and property of Kontron. Any unauthorized review, use, disclosure or distribution is prohibited without express written consent of Kontron. If you are not the intended recipient, please contact the sender and destroy all copies of the original message and enclosed attachments. Diese E-Mail enthält vertrauliche und/oder rechtlich geschützte Informationen und ist Eigentum von Kontron. Die Verwendung und Weitergabe von jeglichen Inhalten ist ohne ausdrückliche schriftliche Genehmigung von Kontron strikt untersagt. Wenn Sie diese E-Mail irrtümlich erhalten haben, informieren Sie bitte sofort den Absender und vernichten diese Mail und enthaltene Dokumente.

5 10

Re: [coreboot] #86: filo sata boot delay patch
by coreboot 15 May '08

15 May '08

#86: filo sata boot delay patch -------------------------+-------------------------------------------------- Reporter: ward | Owner: somebody Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Version: Resolution: fixed | Keywords: Dependencies: | Patchstatus: patch has been committed -------------------------+-------------------------------------------------- Comment (by anonymous): [http://www.iron-dvb.com.cn installing metal stair rails Interior stair handrail exterior baluster Glass wood stainless wrought CONTEMPORARY designs stairways aluminum modern log banister DECK outdoor price posts vinyl curved] -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/86#comment:4> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] #87: flashrom issues on m57sli-s4
by coreboot 15 May '08

15 May '08

#87: flashrom issues on m57sli-s4 -------------------------+-------------------------------------------------- Reporter: ward | Owner: hailfinger Type: defect | Status: closed Priority: major | Milestone: Component: flashrom | Version: v2 Resolution: fixed | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Comment (by anonymous): [http://www.iron-dvb.com.cn installing metal stair rails Interior stair handrail exterior baluster Glass wood stainless wrought CONTEMPORARY designs stairways aluminum modern log banister DECK outdoor price posts vinyl curved] -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/87#comment:7> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] Thin Client Compaq Evo T20
by Philip Loewen 15 May '08

15 May '08

Thanks for your replies. It's exciting to have my questions received so well. I'm not quite allergic to opening the case of my unit, but I should be totally honest about my plan to be a 'consumer' rather than a 'producer' of coreboot knowledge. Investing time and money in hardware to program the flash ROM and to detect small steps toward success would take me off-line from other projects (like earning a living) that I can't afford to quit. My little Evo has a socket for additional flash memory, but the socket is empty and that's OK with me: I am using the T20 as a thin client for several hours each day, with gentoo linux kernel 2.6.24. I get X graphics at 1280x1024@16bpp, the maximum supported by the GX1, by using a patched version of GRUB that lies to the kernel about what memory should be used where. This patch, kindly supplied by others, sacrifices the framebuffer console displays, though. (All of them!) I am hoping that coreboot might get me everything: best-possible video, hi-res framebuffer, and efficient [non-emulated] sound support. (Then I would drop X and go with directfb for VNC.) Success stories and documentation are on the wiki at http://open-evot20.sourceforge.net/wiki/ Thanks again, ... Philip

3 2

Spashtop??
by Marc Karasek 15 May '08

15 May '08

Have any of you heard of this splashtop thing that ASUS partnering with. ?? http://www.splashtop.com/get.php http://www.geek.com/splashtops-instant-on-linux-desktop/ -- ********************* Marc Karasek MTS Sun Microsystems mailto:marc.karasek@sun.com ph:770.360.6415 *********************

6 6

r3321 - trunk/util/flashrom
by svn＠coreboot.org 15 May '08

15 May '08

Author: hailfinger Date: 2008-05-15 05:24:43 +0200 (Thu, 15 May 2008) New Revision: 3321 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Lots of new SST flash chip IDs. Only a subset has been added to flashchips.c, but the IDs in flash.h will make lookups easier if anybody wants to add support for them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-15 03:19:49 UTC (rev 3320) +++ trunk/util/flashrom/flash.h 2008-05-15 03:24:43 UTC (rev 3321) @@ -237,8 +237,21 @@ #define SST_25VF032B 0x254A #define SST_25VF040B 0x258D #define SST_25VF080B 0x258E +#define SST_27SF512 0xA4 +#define SST_27SF010 0xA5 +#define SST_27SF020 0xA6 +#define SST_27VF010 0xA9 +#define SST_27VF020 0xAA +#define SST_28SF040 0x04 +#define SST_29EE512 0x5D +#define SST_29EE010 0x07 +#define SST_29LE010 0x08 /* also SST29VE010 */ #define SST_29EE020A 0x10 -#define SST_28SF040 0x04 +#define SST_29LE020 0x12 /* also SST29VE020 */ +#define SST_29SF020 0x24 +#define SST_29VF020 0x25 +#define SST_29SF040 0x13 +#define SST_29VF040 0x14 #define SST_39SF010 0xB5 #define SST_39SF020 0xB6 #define SST_39SF040 0xB7 Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-15 03:19:49 UTC (rev 3320) +++ trunk/util/flashrom/flashchips.c 2008-05-15 03:24:43 UTC (rev 3321) @@ -70,7 +70,10 @@ {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040}, + {"SST", "SST29EE010", SST_ID, SST_29EE010, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"SST", "SST29LE010", SST_ID, SST_29LE010, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"SST", "SST29LE020", SST_ID, SST_29LE020, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020},

1 0

r3320 - trunk/util/flashrom
by svn＠coreboot.org 15 May '08

15 May '08

Author: hailfinger Date: 2008-05-15 05:19:49 +0200 (Thu, 15 May 2008) New Revision: 3320 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c trunk/util/flashrom/spi.h Log: Add support for the JEDEC RES (Read Electronic Signature and Resume from Powerdown) SPI command to flashrom to identify older SPI chips which can't handle JEDEC RDID. Since RES gives a one-byte identifier which is shared among many different vendors and even different sizes, we want to match RES as a last resort if RDID returns 0xff 0xff 0xff. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> This is a heavily reworked version of a patch by Fredrik Tolf, which was Signed-off-by: Fredrik Tolf <fredrik(a)dolda2000.com> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-14 22:56:47 UTC (rev 3319) +++ trunk/util/flashrom/flash.h 2008-05-15 03:19:49 UTC (rev 3320) @@ -177,6 +177,8 @@ /* * MX25 chips are SPI, first byte of device ID is memory type, * second byte of device ID is log(bitsize)-9. + * Generalplus SPI chips seem to be compatible with Macronix + * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ #define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ @@ -266,6 +268,7 @@ #define ST_M25P10A 0x2011 #define ST_M25P20 0x2012 #define ST_M25P40 0x2013 +#define ST_M25P40_RES 0x12 #define ST_M25P80 0x2014 #define ST_M25P16 0x2015 #define ST_M25P32 0x2016 @@ -366,7 +369,8 @@ extern char *lb_part, *lb_vendor; /* spi.c */ -int probe_spi(struct flashchip *flash); +int probe_spi_rdid(struct flashchip *flash); +int probe_spi_res(struct flashchip *flash); int it87xx_probe_spi_flash(const char *name); int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void spi_write_enable(); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-14 22:56:47 UTC (rev 3319) +++ trunk/util/flashrom/flashchips.c 2008-05-15 03:19:49 UTC (rev 3320) @@ -49,26 +49,26 @@ {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, - {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Macronix", "MX25L1605", MX_ID, MX_25L1605, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L1605", MX_ID, MX_25L1605, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, #ifndef DISABLE_DOC {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, TEST_UNTESTED, probe_md2802, erase_md2802, write_md2802, read_md2802}, #endif - {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"PMC", "Pm49FL002", PMC_ID_NOPREFIX,PMC_49FL002, 256, 16 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49fl004}, {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, 512, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49fl004}, {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, TEST_UNTESTED, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, - {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040}, {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, @@ -91,15 +91,16 @@ {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, TEST_UNTESTED, probe_jedec, erase_49lf040, write_49lf040}, {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P40-old", ST_ID, ST_M25P40_RES, 512, 256, TEST_UNTESTED, probe_spi_res, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, @@ -118,10 +119,10 @@ {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, - {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, TEST_OK_PREW, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, @@ -136,11 +137,11 @@ {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, TEST_UNTESTED, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, - {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, - {"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi, NULL, NULL}, + {"EON", "unknown EON SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, + {"Macronix", "unknown Macronix SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, + {"PMC", "unknown PMC SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, + {"SST", "unknown SST SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, + {"ST", "unknown ST SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 256, TEST_UNTESTED, probe_spi_rdid, NULL, NULL}, {NULL,} }; Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-05-14 22:56:47 UTC (rev 3319) +++ trunk/util/flashrom/spi.c 2008-05-15 03:19:49 UTC (rev 3320) @@ -49,6 +49,16 @@ return 0; } +static int spi_res(unsigned char *readarr) +{ + const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0}; + + if (spi_command(JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr)) + return 1; + printf_debug("RES returned %02x.\n", readarr[0]); + return 0; +} + void spi_write_enable() { const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN}; @@ -65,7 +75,7 @@ spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); } -int probe_spi(struct flashchip *flash) +int probe_spi_rdid(struct flashchip *flash) { unsigned char readarr[3]; uint32_t manuf_id; @@ -102,6 +112,35 @@ return 0; } +int probe_spi_res(struct flashchip *flash) +{ + unsigned char readarr[3]; + uint32_t model_id; + if (!spi_rdid(readarr)) { + /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */ + if ((readarr[0] != 0xff) || (readarr[1] != 0xff) || + (readarr[2] != 0xff)) + return 0; + } else { + /* We couldn't issue RDID, it's pointless to try RES. */ + return 0; + } + if (!spi_res(readarr)) { + model_id = readarr[0]; + printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); + if (model_id == flash->model_id) { + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + + return 1; + } + } + + return 0; +} + uint8_t spi_read_status_register() { const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; Modified: trunk/util/flashrom/spi.h =================================================================== --- trunk/util/flashrom/spi.h 2008-05-14 22:56:47 UTC (rev 3319) +++ trunk/util/flashrom/spi.h 2008-05-15 03:19:49 UTC (rev 3320) @@ -29,6 +29,11 @@ #define JEDEC_RDID_OUTSIZE 0x01 #define JEDEC_RDID_INSIZE 0x03 +/* Read Electronic Signature */ +#define JEDEC_RES 0xab +#define JEDEC_RES_OUTSIZE 0x04 +#define JEDEC_RES_INSIZE 0x01 + /* Write Enable */ #define JEDEC_WREN 0x06 #define JEDEC_WREN_OUTSIZE 0x01

1 0

Re: [coreboot] r3300 - trunk/util/flashrom
by Stefan Reinauer 15 May '08

15 May '08

* svn(a)coreboot.org <svn(a)coreboot.org> [080512 23:19]: > Author: hailfinger > Date: 2008-05-12 23:19:53 +0200 (Mon, 12 May 2008) > New Revision: 3300 > > Modified: trunk/util/flashrom/flash.h > =================================================================== > --- trunk/util/flashrom/flash.h 2008-05-12 14:25:31 UTC (rev 3299) > +++ trunk/util/flashrom/flash.h 2008-05-12 21:19:53 UTC (rev 3300) > @@ -66,6 +66,7 @@ > #define TEST_OK_READ (1<<1) > #define TEST_OK_ERASE (1<<2) > #define TEST_OK_WRITE (1<<3) > +#define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE) Can we call this TEST_OK_ALL or something? PREW is not exactly intuitive. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 4

← Newer
1
...
18
19
20
21
22
23
24
...
39
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2008