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flashrom: Rename generic_spi_*() functions to spi_*()
by Peter Stuge 10 May '08

10 May '08

See patch. //Peter

2 2

r3295 - trunk/util/flashrom
by svn＠coreboot.org 10 May '08

10 May '08

Author: stuge Date: 2008-05-11 01:07:52 +0200 (Sun, 11 May 2008) New Revision: 3295 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: flashrom: Rename generic_spi_*() functions to spi_*() This is a very early step toward cleaning up SPI code in flashrom. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-09 15:32:46 UTC (rev 3294) +++ trunk/util/flashrom/flash.h 2008-05-10 23:07:52 UTC (rev 3295) @@ -349,12 +349,12 @@ /* spi.c */ int probe_spi(struct flashchip *flash); int it87xx_probe_spi_flash(const char *name); -int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -void generic_spi_write_enable(); -void generic_spi_write_disable(); -int generic_spi_chip_erase_c7(struct flashchip *flash); -int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf); -int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf); +int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +void spi_write_enable(); +void spi_write_disable(); +int spi_chip_erase_c7(struct flashchip *flash); +int spi_chip_write(struct flashchip *flash, uint8_t *buf); +int spi_chip_read(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-09 15:32:46 UTC (rev 3294) +++ trunk/util/flashrom/flashchips.c 2008-05-10 23:07:52 UTC (rev 3295) @@ -49,25 +49,25 @@ {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, - {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002}, #ifndef DISABLE_DOC {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, TEST_UNTESTED, probe_md2802, erase_md2802, write_md2802, read_md2802}, #endif - {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"PMC", "Pm49FL002", PMC_ID_NOPREFIX,PMC_49FL002, 256, 16 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49fl004}, {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, 512, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49fl004}, {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, TEST_UNTESTED, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, - {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, TEST_UNTESTED, probe_28sf040, erase_28sf040, write_28sf040}, {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, @@ -87,15 +87,15 @@ {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, TEST_UNTESTED, probe_jedec, erase_49lf040, write_49lf040}, {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, @@ -114,10 +114,10 @@ {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, - {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, TEST_UNTESTED, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Winbond", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, TEST_UNTESTED, probe_spi, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-05-09 15:32:46 UTC (rev 3294) +++ trunk/util/flashrom/spi.c 2008-05-10 23:07:52 UTC (rev 3295) @@ -241,7 +241,7 @@ return 0; } -int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (it8716f_flashport) return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr); @@ -249,30 +249,30 @@ return 1; } -static int generic_spi_rdid(unsigned char *readarr) +static int spi_rdid(unsigned char *readarr) { const unsigned char cmd[] = JEDEC_RDID; - if (generic_spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr)) + if (spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr)) return 1; printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); return 0; } -void generic_spi_write_enable() +void spi_write_enable() { const unsigned char cmd[] = JEDEC_WREN; /* Send WREN (Write Enable) */ - generic_spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); + spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); } -void generic_spi_write_disable() +void spi_write_disable() { const unsigned char cmd[] = JEDEC_WRDI; /* Send WRDI (Write Disable) */ - generic_spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); + spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL); } int probe_spi(struct flashchip *flash) @@ -280,7 +280,7 @@ unsigned char readarr[3]; uint32_t manuf_id; uint32_t model_id; - if (!generic_spi_rdid(readarr)) { + if (!spi_rdid(readarr)) { /* Check if this is a continuation vendor ID */ if (readarr[0] == 0x7f) { manuf_id = (readarr[0] << 8) | readarr[1]; @@ -308,13 +308,13 @@ return 0; } -uint8_t generic_spi_read_status_register() +uint8_t spi_read_status_register() { const unsigned char cmd[] = JEDEC_RDSR; unsigned char readarr[1]; /* Read Status Register */ - generic_spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr); + spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr); return readarr[0]; } @@ -376,7 +376,7 @@ { uint8_t status; - status = generic_spi_read_status_register(); + status = spi_read_status_register(); printf_debug("Chip status register is %02x\n", status); switch (flash->manufacture_id) { case ST_ID: @@ -391,18 +391,18 @@ } } -int generic_spi_chip_erase_c7(struct flashchip *flash) +int spi_chip_erase_c7(struct flashchip *flash) { const unsigned char cmd[] = JEDEC_CE_C7; spi_disable_blockprotect(); - generic_spi_write_enable(); + spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); + spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ - while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) sleep(1); return 0; } @@ -412,39 +412,39 @@ * 32k for SST * 4-32k non-uniform for EON */ -int generic_spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) +int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); - generic_spi_write_enable(); + spi_write_enable(); /* Send BE (Block Erase) */ - generic_spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); + spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ - while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) usleep(100 * 1000); return 0; } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ -int generic_spi_sector_erase(const struct flashchip *flash, unsigned long addr) +int spi_sector_erase(const struct flashchip *flash, unsigned long addr) { unsigned char cmd[JEDEC_SE_OUTSIZE] = JEDEC_SE; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); - generic_spi_write_enable(); + spi_write_enable(); /* Send SE (Sector Erase) */ - generic_spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); + spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ - while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) usleep(10 * 1000); return 0; } @@ -453,7 +453,7 @@ void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { int i; - generic_spi_write_enable(); + spi_write_enable(); outb(0x06 , it8716f_flashport + 1); outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { @@ -463,11 +463,11 @@ /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ - while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) usleep(1000); } -void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios) +void spi_page_program(int block, uint8_t *buf, uint8_t *bios) { if (it8716f_flashport) it8716f_spi_page_program(block, buf, bios); @@ -482,7 +482,7 @@ const unsigned char cmd[] = {JEDEC_WRSR, (unsigned char)status}; /* Send WRSR (Write Status Register) */ - generic_spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL); + spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -495,18 +495,18 @@ }; /* Send Byte-Program */ - generic_spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL); + spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL); } void spi_disable_blockprotect(void) { uint8_t status; - status = generic_spi_read_status_register(); + status = spi_read_status_register(); /* If there is block protection in effect, unprotect it first. */ if ((status & 0x3c) != 0) { printf_debug("Some block protection in effect, disabling\n"); - generic_spi_write_enable(); + spi_write_enable(); spi_write_status_register(status & ~0x3c); } } @@ -523,9 +523,9 @@ spi_disable_blockprotect(); for (i = 0; i < total_size; i++) { - generic_spi_write_enable(); + spi_write_enable(); spi_byte_program(i, buf[i]); - while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) myusec_delay(10); } /* resume normal ops... */ @@ -542,14 +542,14 @@ }; /* Send Read */ - generic_spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes); + spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes); } /* * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf) +int spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; int i; @@ -568,14 +568,14 @@ return 0; } -int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf) { +int spi_chip_write(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; int i; if (total_size > 512 * 1024) { it8716f_over512k_spi_chip_write(flash, buf); } else { for (i = 0; i < total_size / 256; i++) { - generic_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); + spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); } } return 0;

1 0

v2 patch for alix1c
by ron minnich 10 May '08

10 May '08

This is the MFGPT patch for alix1c on v2. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Not tested. Index: src/mainboard/pcengines/alix1c/Config.lb =================================================================== --- src/mainboard/pcengines/alix1c/Config.lb (revision 3294) +++ src/mainboard/pcengines/alix1c/Config.lb (working copy) @@ -148,9 +148,9 @@ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # How to get these? Boot linux and do this: # rdmsr 0x51400025 - register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_enable" = "0x0000105A" # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_polarity" = "0x0000EFA5" # mode is high 10 bits (determined from code) register "lpc_serirq_mode" = "1" # Don't yet know how to find this.

2 4

here's a good one
by ron minnich 10 May '08

10 May '08

on alix1c, I put a pci usb card in. Then I plug in a usb device. I get this: usb 3-2: new full speed USB device using uhci_hcd and address 2 usb 3-2: device descriptor read/64, error -110 usb 3-2: device descriptor read/64, error -110 usb 3-2: new full speed USB device using uhci_hcd and address 3 usb 3-2: device descriptor read/64, error -110 usb 3-2: device descriptor read/64, error -110 usb 3-2: new full speed USB device using uhci_hcd and address 4 usb 3-2: device not accepting address 4, error -110 usb 3-2: new full speed USB device using uhci_hcd and address 5 usb 3-2: device not accepting address 5, error -110 hub 3-0:1.0: unable to enumerate USB device on port 2 interrupts, however, don't happen: 0: 88 XT-PIC-XT timer 2: 0 XT-PIC-XT cascade 4: 1058 XT-PIC-XT serial 7: 4793137 XT-PIC-XT mfgpt-timer 8: 0 XT-PIC-XT rtc 9: 2 XT-PIC-XT ohci_hcd:usb1, uhci_hcd:usb3 10: 210 XT-PIC-XT eth0 11: 0 XT-PIC-XT uhci_hcd:usb2 14: 360 XT-PIC-XT ide0 NMI: 0 Non-maskable interrupts TRM: 0 Thermal event interrupts SPU: 0 Spurious interrupts ERR: 0 So the IRQ 9 is this via usb card in 3V pci slot. I get one interrupt per USB plug/unplug event. For the onboard, working USB, when I hotplug, well, I get lots more: 9: 24 XT-PIC-XT ohci_hcd:usb1, uhci_hcd:usb3 So it seems to be back to IRQ stuff. Now my devices look like this: 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) (prog-if 10 [OHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 9 Region 0: Memory at fe016000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 9 Region 0: Memory at fe017000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- note that the onboard usb, which is NOT routed from the pci bus, is irq 9. The via USB card looks like this: 00:0c.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 61) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, cache line size 10 Interrupt: pin A routed to IRQ 11 Region 4: I/O ports at 1c80 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 00:0c.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 61) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, cache line size 10 Interrupt: pin B routed to IRQ 9 Region 4: I/O ports at 1ca0 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 00:0c.2 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 63) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin C routed to IRQ 11 Region 0: Memory at fe019000 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- so it's using IRQ 9 and 11, depending on port. The port I plugged the usb into was UHCI. But we had a problem with MFGPT not working due to improper IRQ controller setup. Is there any chance of a PCI conflict with the onboard USB controller? not in terms of "sharing interrupts' but in terms of some internal cs5536 issue? ron

4 3

Re: [coreboot] SimNOW V2 LAB problem
by Jordan Crouse 10 May '08

10 May '08

Okay, so there seems to be breakage in SimNow - the serial ports are not detected from within the kernel. I'm not exactly sure why - I don't know if there is some detection in the kernel that is failing to work, or if SimNow itself is being troublesome. I'll start the debug on Monday. Jordan

2 1

r193 - buildrom-devel/config/platforms
by svn＠coreboot.org 09 May '08

09 May '08

Author: ward Date: 2008-05-10 01:20:43 +0200 (Sat, 10 May 2008) New Revision: 193 Modified: buildrom-devel/config/platforms/alix1c.conf Log: Bump up v3 revision for alix.1c, which fixes the MFGPT problem. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/alix1c.conf =================================================================== --- buildrom-devel/config/platforms/alix1c.conf 2008-05-09 23:13:32 UTC (rev 192) +++ buildrom-devel/config/platforms/alix1c.conf 2008-05-09 23:20:43 UTC (rev 193) @@ -25,7 +25,7 @@ CBV2_TDIR=alix1c CBV2_TAG=3079 -CBV3_TAG=656 +CBV3_TAG=682 # FILO configuration

1 0

r192 - buildrom-devel/config/platforms
by svn＠coreboot.org 09 May '08

09 May '08

Author: ward Date: 2008-05-10 01:13:32 +0200 (Sat, 10 May 2008) New Revision: 192 Modified: buildrom-devel/config/platforms/alix2c3.conf Log: Bump up alix.2c3 revision to r682, which fixes the MFGPT issue. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/alix2c3.conf =================================================================== --- buildrom-devel/config/platforms/alix2c3.conf 2008-05-09 15:35:01 UTC (rev 191) +++ buildrom-devel/config/platforms/alix2c3.conf 2008-05-09 23:13:32 UTC (rev 192) @@ -22,7 +22,7 @@ COREBOOT_VENDOR=pcengines COREBOOT_BOARD=alix2c3 -CBV3_TAG=680 +CBV3_TAG=682 # FILO configuration

1 0

patch: fix interupts for MFGPT for alix1c and alix2c3
by ron minnich 09 May '08

09 May '08

attached. Thanks again to Marc and Jordan and of course AMD. ron

4 4

r682 - in coreboot-v3/mainboard/pcengines: alix1c alix2c3
by svn＠coreboot.org 09 May '08

09 May '08

Author: rminnich Date: 2008-05-09 23:48:28 +0200 (Fri, 09 May 2008) New Revision: 682 Modified: coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/mainboard/pcengines/alix2c3/dts Log: This is the fix for MFGPT on those boards which have a cs5536 and ALSO have a superio. With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it is likely it will work. Thanks to Marc and Jordan for this one. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-09 16:12:41 UTC (rev 681) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-09 21:48:28 UTC (rev 682) @@ -36,9 +36,9 @@ /config/("southbridge/amd/cs5536/dts"); /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ - lpc_serirq_enable = "0x000010da"; + lpc_serirq_enable = "0x0000105A"; /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ - lpc_serirq_polarity = "0x0000EF25"; + lpc_serirq_polarity = "0x0000EFA5"; /* 0:continuous 1:quiet */ lpc_serirq_mode = "1"; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-09 16:12:41 UTC (rev 681) +++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-09 21:48:28 UTC (rev 682) @@ -34,9 +34,9 @@ /config/("southbridge/amd/cs5536/dts"); /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ - lpc_serirq_enable = "0x000010da"; + lpc_serirq_enable = "0x0000105A"; /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ - lpc_serirq_polarity = "0x0000EF25"; + lpc_serirq_polarity = "0x0000EFA5"; /* 0:continuous 1:quiet */ lpc_serirq_mode = "1"; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.

1 0

buildrom failure
by ron minnich 09 May '08

09 May '08

Building TINT... make[1]: Entering directory `/home/rminnich/src/bios/buildrom/buildrom-devel/work/tint/tint-0.03b' /home/rminnich/src/bios/buildrom/buildrom-devel/staging/libpayload/bin/lpgcc -Wall -Os -c -o tint.o tint.c In file included from tint.c:43: config.h:37: error: conflicting types for 'time_t' /home/rminnich/src/bios/buildrom/buildrom-devel/staging/libpayload/bin/../include/arch/types.h:53: error: previous declaration of 'time_t' was here make[1]: *** [tint.o] Error 1 make[1]: Leaving directory `/home/rminnich/src/bios/buildrom/buildrom-devel/work/tint/tint-0.03b' make: *** [/home/rminnich/src/bios/buildrom/buildrom-devel/work/tint/tint-0.03b/tint.elf] Error 2 [rminnich@xcpu buildrom-devel]$ I'm looking but maybe someone has seen this. ron

4 8

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coreboot May 2008