coreboot May 2008

coreboot@coreboot.org

79 participants
387 discussions

bug in cs5536 ide enable. Is this also in 8111 ...
by ron minnich 08 May '08

08 May '08

#define IDE_CFG 0x40 #define CHANEN (1L << 1) #define PWB (1L << 14) #define CABLE (1L << 16) #define IDE_DTC 0x48 #define IDE_CAST 0x4C #define IDE_ETC 0x50 static void ide_init(struct device *dev) { uint32_t ide_cfg; printk_spew("cs5536_ide: %s\n", __FUNCTION__); /* GPIO and IRQ setup are handled in the main chipset code. */ // Enable the channel and Post Write Buffer // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; pci_write_config8(dev, IDE_CFG, ide_cfg); } Note the pci_read_config32 followed by the pci_write_config8. HMM, why did this ever work? Anyway, I changed the write_config8 to write_config32 and it is still no good on the alix1c on v3. If someone wants to try this fix on v2, go for it: Index: southbridge/amd/cs5536/cs5536.c =================================================================== --- southbridge/amd/cs5536/cs5536.c (revision 676) +++ southbridge/amd/cs5536/cs5536.c (working copy) @@ -597,7 +597,7 @@ // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; - pci_write_config8(dev, IDE_CFG, ide_cfg); + pci_write_config32(dev, IDE_CFG, ide_cfg); } you need to translate for the v2 filename. off to rest, if somebody gets somewhere with this, let me know. ron

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Re: [coreboot] r3293 - trunk/util/superiotool
by Uwe Hermann 08 May '08

08 May '08

On Thu, May 08, 2008 at 04:37:18PM +0200, svn(a)coreboot.org wrote: > Add support for dumping ITE IT8718F EC registers (trivial). For reference here's a dump from actual hardware (GIGABYTE 8I945GZME-RH): $ superiotool -de superiotool r3292 Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e Register dump: idx 07 20 21 22 23 24 2b val 04 87 18 01 10 00 00 def NA 87 18 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 c0 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 68 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 02 00 40 00 00 1c 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 02 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26 00 00 00 00 00 53 00 00 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Environment controller (0x0295) Register dump: idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 20 21 22 23 24 25 26 27 28 29 2a 2b 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 50 51 52 53 54 56 57 58 59 5b 5c 5d 5e 5f 60 61 62 63 64 65 68 69 6a 6b 6c 6d 70 71 72 73 74 75 80 81 82 83 88 89 8a 8b 8c 8d 8e 8f 90 91 92 94 95 96 a0 a1 a2 a3 a4 a5 a6 val 11 10 88 00 37 ff 00 37 ff 87 40 09 07 17 cd ff ff ff ff 73 d7 82 7f 7f 02 01 ff ff ff ff 55 73 cf ff be 02 50 ff ff ca fe 1b ff 00 ff 00 ff 00 ff 00 ff 00 ff 00 ff 00 ff 00 7f 7f 7f 7f 7f 7f ff 1c 7f 7f 7f de de 90 de 12 00 00 00 00 00 14 41 23 90 03 7f 7f 7f 00 00 7f 00 14 41 23 90 03 00 00 00 00 00 00 00 00 00 00 02 00 ff 00 00 ff 00 00 00 00 00 00 00 00 00 def 18 00 00 00 00 00 00 00 00 80 40 09 00 NA NA NA NA NA NA 07 50 MM MM MM NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 7f 7f 7f 00 00 90 00 12 00 00 00 00 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f 7f 7f 7f 00 00 7f NA NA NA NA 00 00 00 00 00 00 02 00 ff 00 00 ff 00 00 00 00 00 00 00 00 00 Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

r678 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 08 May '08

08 May '08

Author: rminnich Date: 2008-05-08 16:51:40 +0200 (Thu, 08 May 2008) New Revision: 678 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: Changed erroneous write config 8 to write config 32 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-07 23:21:55 UTC (rev 677) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-08 14:51:40 UTC (rev 678) @@ -602,7 +602,7 @@ // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set ide_cfg = pci_read_config32(dev, IDE_CFG); ide_cfg |= CHANEN | PWB; - pci_write_config8(dev, IDE_CFG, ide_cfg); + pci_write_config32(dev, IDE_CFG, ide_cfg); }

1 0

r3293 - trunk/util/superiotool
by svn＠coreboot.org 08 May '08

08 May '08

Author: uwe Date: 2008-05-08 16:37:12 +0200 (Thu, 08 May 2008) New Revision: 3293 Modified: trunk/util/superiotool/ite.c Log: Add support for dumping ITE IT8718F EC registers (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-05-08 13:50:23 UTC (rev 3292) +++ trunk/util/superiotool/ite.c 2008-05-08 14:37:12 UTC (rev 3293) @@ -350,6 +350,35 @@ 0x99,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f, 0x00,0x00,0x7f,EOT}}, {EOT}}}, + {0x8718, "IT8718F", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2b,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41, + 0x42,0x43,0x44,0x45,0x50,0x51,0x52,0x53,0x54,0x56, + 0x57,0x58,0x59,0x5b,0x5c,0x5d,0x5e,0x5f,0x60,0x61, + 0x62,0x63,0x64,0x65,0x68,0x69,0x6a,0x6b,0x6c,0x6d, + 0x70,0x71,0x72,0x73,0x74,0x75,0x80,0x81,0x82,0x83, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,0x90,0x91, + 0x92,0x94,0x95,0x96,0xa0,0xa1,0xa2,0xa3,0xa4,0xa5, + 0xa6,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80, + 0x40,0x09,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x07, + 0x50,MISC,MISC,MISC,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,0x00,0x00,0x7f,0x7f,0x7f,0x00, + 0x00,0x90,0x00,0x12,0x00,0x00,0x00,0x00,0x7f,0x7f, + 0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00,0x7f, + 0x7f,0x7f,0x7f,0x00,0x00,0x7f,NANA,NANA,NANA,NANA, + 0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0xff,0x00, + 0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,EOT}}, + {EOT}}}, {EOT} };

1 0

ARM joins UEFI
by ron minnich 08 May '08

08 May '08

A friend writes: http://www.industrial-europe.com/207501172 This second article is almost funny in that it contradicts the direction that UEFI takes. http://www.industrial-europe.com/207600269 amazing. Put an OS in the BIOS FLASH part. Now who would ever have thought of such a ridiculous idea. ron

2 1

r3292 - trunk/util/superiotool
by svn＠coreboot.org 08 May '08

08 May '08

Author: uwe Date: 2008-05-08 15:50:23 +0200 (Thu, 08 May 2008) New Revision: 3292 Modified: trunk/util/superiotool/ite.c trunk/util/superiotool/superiotool.h Log: Don't split up register list in two blocks, otherwise "Register dump:" will be printed twice in the output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-05-08 00:31:44 UTC (rev 3291) +++ trunk/util/superiotool/ite.c 2008-05-08 13:50:23 UTC (rev 3292) @@ -332,20 +332,19 @@ 0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39, 0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41,0x42,0x43, 0x44,0x45,0x48,0x50,0x51,0x52,0x53,0x54,0x56,0x57, - 0x59,0x5c,EOT}, + 0x59,0x5c, + 0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63,0x64,0x65,0x68, + 0x69,0x6a,0x6b,0x6c,0x6d,0x70,0x71,0x72,0x73,0x74, + 0x75,0x84,0x85,0x86,0x87,0x88,0x89,0x8c,0x8d,0x8e, + 0x8f,0x90,0x91,0x92,0x93,0x94,0x95,0x98,0x99,0x9a, + 0x9b,0x9c,0x9d,EOT}, {0x18,0x00,0x00,0x00,0x00,0x00,0x80,0x09,0x00,NANA, NANA,NANA,0x07,0x50,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,RSVD,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00, - 0x00,0x00,EOT}}, - {NOLDN, NULL, - {0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63,0x64,0x65,0x68, - 0x69,0x6a,0x6b,0x6c,0x6d,0x70,0x71,0x72,0x73,0x74, - 0x75,0x84,0x85,0x86,0x87,0x88,0x89,0x8c,0x8d,0x8e, - 0x8f,0x90,0x91,0x92,0x93,0x94,0x95,0x98,0x99,0x9a, - 0x9b,0x9c,0x9d,EOT}, - {0x00,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f, + 0x00,0x00, + 0x00,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f, 0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00, 0x7f,NANA,NANA,NANA,NANA,0x00,0x00,0x02,0x00,0x99, 0x99,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f, Modified: trunk/util/superiotool/superiotool.h =================================================================== --- trunk/util/superiotool/superiotool.h 2008-05-08 00:31:44 UTC (rev 3291) +++ trunk/util/superiotool/superiotool.h 2008-05-08 13:50:23 UTC (rev 3292) @@ -53,7 +53,7 @@ #define MISC -5 /* Needs special comment in output */ #define MAXLDN 0x10 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ -#define MAXNUMIDX 70 /* Maximum number of indexes */ +#define MAXNUMIDX 170 /* Maximum number of indexes */ #define IDXSIZE (MAXNUMIDX + 1) #define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */

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Re: [coreboot] AMDk8 - HT routing
by Viswesh S 08 May '08

08 May '08

Hi, I understand that before the node ids are being assigned, each AP node is considered as Node7. We will just go through the sequence of code in setup_smp2() in coherent_ht.c. From the link type register 0x98, in Node0, it is seen that link1 is coherent and connected. setup_row_local(0, 0); /* it will update the broadcast RT*/ // value is 0x50101 in F0 register 0x40 val = get_row(0,0); byte = (val>>16) & 0xfe; // byte = 0xf4 if(byte<0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } /* Setup and check a temporary connection to node 1 */ #if TRY_HIGH_FIRST == 1 byte = get_linkn_last(byte); /* Max Link to node1 */ #else // TRY_HIGH_FIRST = 0 here byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/ #endif // byte = 1 print_linkn("(0,1) link=", byte); setup_row_direct(0,1, byte); // ( We are modifying the routing register 0x44, which is for the connection between Node0 and Node1. So here itself we consider Node1 itself and node7, though we copy the value from register 0x44 to 0x5c in the next function. setup_temp_row(0, 1); // As mentioned, we copy the value from 0x44 to 0x5c, ie setting up of routing register for connection between node0 and node7 --> which is actually AP verify_connection(7); // Here is where I get confused.See verify the connection tries to read the 0x0 register from Node7, which doesnt exist at all.ie in our case node0 has device address 0x18 and hence node7 will have 0x18+7 = 0x1f and such a device doesnt exist at all if you do lspci. 00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:01.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:02.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:02.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) 00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05) 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev 03) 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:00.0 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:00.1 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:06.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27) So then what value do we read..The same question arises for the next function also - /* We found 2 nodes so far */ val = pci_read_config32(NODE_HT(7), 0x6c); // Here also the same issues arises byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ print_linkn("(1,0) link=", byte); setup_row_local(7,1); setup_remote_row_direct(1, 0, byte); Viswesh Bring your gang together. Do your thing. Find your favourite Yahoo! group at http://in.promos.yahoo.com/groups/

2 1

[PATCH] artecgroup/dbe61: Sync irq_tables with dbe62 code to fix compilation and have a chance of working properly.
by Mart Raudsepp 08 May '08

08 May '08

Hello, Here's a patch that fixes DBE61 target compilation by making irq_tables.h take the v3 approach. It might actually work on hardware regarding interrupt setup, but we need to get the raminit to work properly to see... so this is in the name of compilation fix and common sense that as all the IRQ routing is the same in DBE61 and DBE62, that the routing settings in dbe62 code should be fine for dbe61 as well. Compilable target makes poking at raminit easier ;) Regards, Mart Raudsepp Artec Design LLC

2 1

Unable to flash Pm49FL004
by Richard Stellingwerff 08 May '08

08 May '08

Hi all, I finally got myself a PLCC extractor so I can start getting coreboot to work on my Jetway J7F4K1G2E-PB board. However, I'm already running into a problem trying to write the original bios on the Pm49FL004. Extracting the BIOS from the original ROM works fine, but trying to write it into the new chip (after hot-swapping them) results in this: # flashrom -wv backup.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA VT8237", enabling flash write... OK. Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... FAILED! Reading from the Pm49FL004 returns all FF's (checked with hexedit). I compiled flashrom myself from SVN a few minutes ago. Anyone know what I can do? Kind regards, Richard Stellingwerff.

2 3

[PATCH] Implement GPIO configuration options for Intel 3100 southbridge
by Ed Swierk 08 May '08

08 May '08

When I originally ported the GPIO configuration routines for the Intel 3100 southbridge from esb6300_lpc.c, I left out the code that lets you specify per-mainboard GPIO settings. This patch implements those configuration routines, so you can put something like register "gpio[23]" = "I3100_GPIO_USE_AS_GPIO | I3100_GPIO_SEL_OUTPUT | I3100_GPIO_LVL_LOW" in Config.lb to set GPIO 23 as an output, driving the signal low. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

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coreboot May 2008