coreboot May 2008

coreboot@coreboot.org

79 participants
387 discussions

Re: [coreboot] flashrom: Probe for up to 3 flash chips. [was: Fix ambiguity, if a board is equipped with more than one chip]
by Peter Stuge 08 May '08

08 May '08

On Tue, May 06, 2008 at 09:01:07AM +0200, Claus Gindhart wrote: > i've tested the patch, it worked; i've acked-by the attached patch. Thanks! rev 3291. //Peter

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r3291 - trunk/util/flashrom
by svn＠coreboot.org 08 May '08

08 May '08

Author: stuge Date: 2008-05-08 02:31:44 +0200 (Thu, 08 May 2008) New Revision: 3291 Modified: trunk/util/flashrom/flashrom.c Log: flashrom: Probe for up to 3 flash chips. Currently there is an ongoing technology migration from LPC/FWH to SPI chips. For this reason some boards have multiple chips of different technologies onboard. This patch makes flashrom probe for up to 3 chips and if more than one chip is found flashrom exits, asking the user to specify -c. [root@localhost src]# ./flashrom ... Multiple flash chips were detected: SST49LF008A M25P16@ICH9 Please specify which chip to use with the -c <chipname> option. [root@localhost src]# Signed-off-by: Claus Gindhart <claus.gindhart(a)kontron.com> Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Claus Gindhart <claus.gindhart(a)kontron.com> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-05-07 21:57:12 UTC (rev 3290) +++ trunk/util/flashrom/flashrom.c 2008-05-08 00:31:44 UTC (rev 3291) @@ -246,11 +246,12 @@ uint8_t *buf; unsigned long size; FILE *image; - struct flashchip *flash; + /* Probe for up to three flash chips. */ + struct flashchip *flash, *flashes[3]; int opt; int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int ret = 0; + int ret = 0, i; static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -405,12 +406,27 @@ board_flash_enable(lb_vendor, lb_part); - if ((flash = probe_flash(flashchips)) == NULL) { + for (i = 0; i < ARRAY_SIZE(flashes); i++) { + flashes[i] = probe_flash(i ? flashes[i - 1] + 1 : flashchips); + if (!flashes[i]) + for (i++; i < ARRAY_SIZE(flashes); i++) + flashes[i] = NULL; + } + + if (flashes[1]) { + printf("Multiple flash chips were detected:"); + for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) + printf(" %s", flashes[i]->name); + printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); + exit(1); + } else if (!flashes[0]) { printf("No EEPROM/flash device found.\n"); // FIXME: flash writes stay enabled! exit(1); } + flash = flashes[0]; + printf("Flash part is %s (%d KB).\n", flash->name, flash->total_size); if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { printf("===\n");

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legacy bios support and coreboot
by Kevin O'Connor 08 May '08

08 May '08

Hi, As has been discussed a couple of times on this list, I have been working on a project to port the "bochs bios" to gcc. The code is available via git at: http://git.linuxtogo.org/ This email is to go through some of the details of what the "legacybios" code provides and how it works. Note that the code in "legacybios" really is a port of "bochs bios", so the two code bases have nearly identical coverage. There are three major parts of the "legacybios" code: * 16bit software interrupt handlers * 16bit hardware interrupt handlers * "post" code The 16bit software interrupt handlers can be thought of as a code library. They provide a series of standard 'functions' that boot loaders and operating systems may call. Granted, the calling convention of the bios is a bit odd - instead of using 'call' insns one uses 'int' insns, parameters are generally passed in registers, and everything runs in 16bit mode. Fortunately, there is plenty of documentation describing what these calls do - implementing the library itself is not technically challenging. The 16bit hardware interrupts are like the 16bit software interrupt handlers, except they get called by hardware instead of software. The "legacybios" code only implements enough hardware interrupts to make the standard software interrupt handlers work properly. Finally, the "post" code is used to initialize the system and start the boot process. This "post" code is compiled in 32bit mode. It is possible to enter the bios in 16bit mode (by jumping to 0xf000:0xfff0), however all this will do is transition the cpu to 32bit mode and then call the 32bit "post" code. The "post" stage does the following tasks: * minimal hardware detection and init * option rom scan and execution * pci init * various bios table creation * transition to 16bit mode and raise int19 to start boot process I suspect the hardware detection and initialization does not have much overlap with coreboot. The most important part of this section is the IDE initialization and disk scan. (Some other code, for example keyboard init, may be redundant when used with coreboot.) The option rom scan and execution allows the bios code to call out to additional system roms. The "post" stage runs in 32bit mode, but the option roms are called in 16bit mode - the "legacybios" code simply transitions to/from 16bit mode to make these calls. The option rom code is executed natively on the processor. The "pci init" code looks to be redundant with what coreboot already provides. The code in "legacybios" seems to be intel northbride/soutbridge specific. The "legacybios" code provides the following memory tables: * bda, ebda, and 0xf0000 segment * e820 memory map * PIR * mptable * smbios * acpi tables (rsdp, rsdt, fadt, facs, dsdt, madt) Some old DOS programs make assumptions about specific memory locations in the first 1Meg of ram. The "legacybios" code fills in these areas to make these old programs happy - in short they are the "bios data area" at 0x00000 - 0x00500, the "extended bios data area" at 0x9fc00 - 0xa0000, and some hardcoded locations in the 0xf0000 bios segment itself. The bios working storage areas (in bda and ebda) and the 16bit interrupt vector table is also setup (part of the bda). The e820 map is populated by assuming a linear memory layout. The maximum memory is passed into the bios (via a cmos variable, see below), and the resulting e820 map is then generated. The PIR table is simply hard coded at compile time. The mptable code attempts to auto-detect the number of cpus in the system (by raising a "broadcast SIPI"). The rest of the table is then filled with hardcoded information. The smbios and acpi tables use the passed in memory size, the detected cpu count, and info from the "cpuid" insn - the rest is hardcoded. It is not clear to me how much of the acpi/mptable/smbios code is reusable on real hardware. It is possible that most of the info in these tables is irrelevant, and the "legacybios" code may therefore be a good starting point. However, it may also be simpler to have coreboot just pass these tables in. Hardware assumptions that "legacybios" makes: * code loaded into 0xf0000, and execution jumps to it (16bit or 32bit) * cmos settings * ioports (debug port) * hardware specific code (ram shadowing, apm) As mentioned earlier, the bios needs to be loaded into memory starting at 0xf0000 and its init code needs to be run. The rom code is 64K in size (compressed with lzma it is currently 23K). Certain settings are passed into the bios via cmos variables - qemu and bochs emulators use this to select certain settings. The main variables needed are: memory size, floppy drive type, and boot order. The system also uses variables for harddrive geometry and "equipment list flags", but I believe the code can be extended to autodetect these settings. Both qemu and bochs implement a debug port (0x0403) that allows the bios to send debug messages to the console. This will not, of course, work on real hardware. It should be possible to send the debug messages to a serial port. The remainder of the ioports used by "legacybios" look to be standard hardware. Some of the hardware accesses made by the "legacybios" code appear to be specific to hardware in the emulator. The code attempts to enable ram shadowing of the memory segment at 0xf00000 - it does this so that it can put acpi/mptable/smbios tables into that area. After it is complete, it attempts to disable writes to that region. The code sequence looks to be specific to intel north/southbridges. It isn't necessary to disable writes to 0xf0000 (though it would be nice), but it is necessary to have the ability to alter that memory. Also, there are stubs in "legacybios" for apm support - should one want to implement this on real hardware the appropriate power saving code would need to be implemented. Comments? -Kevin

2 3

patch: two bugs in the cs5536 ide code
by ron minnich 07 May '08

07 May '08

I know some people will get upset by the find_pci_device, but: This patch fixes a long-standing problem in the cs5536 driver, that is probably also in v2. The ide_init is called with the sb device but needs the IDE device, which is different. It also did a write_config8,not write_config32; this bug has been in there since the code was written for v2. I don't know how or why it ever worked, since PWB is 1<<14. Works fine with 2.6.24. 2.6.15 hangs on boot, but I don't think it was ever IDE. POST on the 2.6.25 boot hang is 00. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>

8 26

r677 - in coreboot-v3: mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 southbridge/amd/cs5536
by svn＠coreboot.org 07 May '08

07 May '08

Author: hailfinger Date: 2008-05-08 01:21:55 +0200 (Thu, 08 May 2008) New Revision: 677 Added: coreboot-v3/southbridge/amd/cs5536/ide Modified: coreboot-v3/mainboard/amd/db800/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/mainboard/pcengines/alix2c3/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: Move CS5536 IDE configuration into a separate dts and its own PCI device. Fix dbe62 IDE/NAND selection. Build-tested on db800, norwich, dbe62, alix.1c, alix.2c3. No additional breakage for dbe61. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/mainboard/amd/db800/dts =================================================================== --- coreboot-v3/mainboard/amd/db800/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/amd/db800/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -47,6 +46,10 @@ enable_gpio_int_route = "0x0D0C0700"; enable_USBP4_device = "1"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/amd/norwich/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; @@ -50,5 +49,9 @@ com1_address = "0x3f8"; com1_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; }; }; Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -105,5 +105,8 @@ com2_address = "0x3f8"; com2_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + }; }; }; Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x00001002"; @@ -54,5 +53,8 @@ /* Set com2 IRQ to be what is usually COM1 */ com2_irq = "4"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + }; }; }; Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -34,7 +34,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -46,6 +45,10 @@ * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -32,7 +32,6 @@ }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); - enable_ide = "1"; /* Interrupt enables for LPC bus. * Each bit is an IRQ 0-15. */ lpc_serirq_enable = "0x000010da"; @@ -50,5 +49,9 @@ /* this board does not really have vga; disable it (pci device 00:01.1) */ unwanted_vpci = < 80000900 0 >; }; + pci@15,2 { + /config/("southbridge/amd/cs5536/ide"); + enable_ide = "1"; + }; }; }; Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-07 23:21:55 UTC (rev 677) @@ -590,6 +590,11 @@ { u32 ide_cfg; + struct southbridge_amd_cs5536_ide_config *ide = + (struct southbridge_amd_cs5536_ide_config *)dev->device_configuration; + if (!ide->enable_ide) + return; + printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ @@ -654,9 +659,6 @@ hide_vpci(sb->unwanted_vpci[i]); } - if (sb->enable_ide) - ide_init(dev); - cs5536_setup_power_button(sb); printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__); @@ -688,3 +690,17 @@ .phase6_init = southbridge_init, }; +struct device_operations cs5536_ide = { + .id = {.type = DEVICE_ID_PCI, + .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, + .constructor = default_device_constructor, +#warning FIXME: what has to go in phase3_scan? + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init, + .ops_pci = &pci_dev_ops_pci, +}; + Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-05-05 13:59:01 UTC (rev 676) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-05-07 23:21:55 UTC (rev 677) @@ -36,9 +36,6 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0"; - /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ - enable_ide = "0"; - /* Enable USB Port 4 (0:host 1:device). */ enable_USBP4_device = "0"; Added: coreboot-v3/southbridge/amd/cs5536/ide =================================================================== --- coreboot-v3/southbridge/amd/cs5536/ide (rev 0) +++ coreboot-v3/southbridge/amd/cs5536/ide 2008-05-07 23:21:55 UTC (rev 677) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_ide"; + + /* IDE: enable CS5536 IDE. There may be a different IDE controller on board */ + enable_ide = "0"; +};

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r3290 - trunk/coreboot-v2/src/southbridge/intel/i3100
by svn＠coreboot.org 07 May '08

07 May '08

Author: eswierk Date: 2008-05-07 23:57:12 +0200 (Wed, 07 May 2008) New Revision: 3290 Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c Log: Implement GPIO configuration routines for the Intel 3100 southbridge, allowing you to specify per-mainboard GPIO settings. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-05-07 20:43:15 UTC (rev 3289) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-05-07 21:57:12 UTC (rev 3290) @@ -111,10 +111,32 @@ device_t dev, struct resource *res, config_t *config) { u32 gpio_use_sel, gpio_use_sel2; + int i; - gpio_use_sel = 0x1b0ce7c3; - gpio_use_sel2 = 0x00000107; - outl(gpio_use_sel, res->base + 0x00); + gpio_use_sel = inl(res->base + 0x00) | 0x0000c603; + gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100; + for (i = 0; i < 64; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_USE_MASK) { + case I3100_GPIO_USE_AS_NATIVE: + val = 0; + break; + case I3100_GPIO_USE_AS_GPIO: + val = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_use_sel &= ~(1 << i); + gpio_use_sel |= (val << i); + } else { + gpio_use_sel2 &= ~(1 << (i - 32)); + gpio_use_sel2 |= (val << (i - 32)); + } + } + outl(gpio_use_sel, res->base + 0x00); outl(gpio_use_sel2, res->base + 0x30); } @@ -122,10 +144,32 @@ device_t dev, struct resource *res, config_t *config) { u32 gpio_io_sel, gpio_io_sel2; + int i; - gpio_io_sel = 0xed00ffff; - gpio_io_sel2 = 0x00000307; - outl(gpio_io_sel, res->base + 0x04); + gpio_io_sel = inl(res->base + 0x04); + gpio_io_sel2 = inl(res->base + 0x34); + for (i = 0; i < 64; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_SEL_MASK) { + case I3100_GPIO_SEL_OUTPUT: + val = 0; + break; + case I3100_GPIO_SEL_INPUT: + val = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_io_sel &= ~(1 << i); + gpio_io_sel |= (val << i); + } else { + gpio_io_sel2 &= ~(1 << (i - 32)); + gpio_io_sel2 |= (val << (i - 32)); + } + } + outl(gpio_io_sel, res->base + 0x04); outl(gpio_io_sel2, res->base + 0x34); } @@ -134,22 +178,68 @@ { u32 gpio_lvl, gpio_lvl2; u32 gpio_blink; + int i; - gpio_lvl = 0x00030000; - gpio_blink = 0x00000000; - gpio_lvl2 = 0x00000300; - outl(gpio_lvl, res->base + 0x0c); + gpio_lvl = inl(res->base + 0x0c); + gpio_blink = inl(res->base + 0x18); + gpio_lvl2 = inl(res->base + 0x38); + for (i = 0; i < 64; i++) { + int val, blink; + switch (config->gpio[i] & I3100_GPIO_LVL_MASK) { + case I3100_GPIO_LVL_LOW: + val = 0; + blink = 0; + break; + case I3100_GPIO_LVL_HIGH: + val = 1; + blink = 0; + break; + case I3100_GPIO_LVL_BLINK: + val = 1; + blink = 1; + break; + default: + continue; + } + /* The caller is responsible for not playing with unimplemented bits */ + if (i < 32) { + gpio_lvl &= ~(1 << i); + gpio_blink &= ~(1 << i); + gpio_lvl |= (val << i); + gpio_blink |= (blink << i); + } else { + gpio_lvl2 &= ~(1 << (i - 32)); + gpio_lvl2 |= (val << (i - 32)); + } + } + outl(gpio_lvl, res->base + 0x0c); outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); + outl(gpio_lvl2, res->base + 0x38); } static void set_i3100_gpio_inv( device_t dev, struct resource *res, config_t *config) { u32 gpio_inv; + int i; - gpio_inv = 0x00006000; - outl(gpio_inv, res->base + 0x2c); + gpio_inv = inl(res->base + 0x2c); + for (i = 0; i < 32; i++) { + int val; + switch (config->gpio[i] & I3100_GPIO_INV_MASK) { + case I3100_GPIO_INV_OFF: + val = 0; + break; + case I3100_GPIO_INV_ON: + val = 1; + break; + default: + continue; + } + gpio_inv &= ~(1 << i); + gpio_inv |= (val << i); + } + outl(gpio_inv, res->base + 0x2c); } static void i3100_pirq_init(device_t dev)

1 0

r189 - in buildrom-devel/packages: coreinfo coreinfo/conf libpayload
by svn＠coreboot.org 07 May '08

07 May '08

Author: jcrouse Date: 2008-05-07 23:27:49 +0200 (Wed, 07 May 2008) New Revision: 189 Added: buildrom-devel/packages/coreinfo/conf/defconfig-coreboot buildrom-devel/packages/coreinfo/conf/defconfig-coreboot-v3 Removed: buildrom-devel/packages/coreinfo/conf/defconfig Modified: buildrom-devel/packages/coreinfo/coreinfo.mk buildrom-devel/packages/libpayload/libpayload.mk Log: buildrom: Bump the revision for coreinfo & libpayload Bump the coreinfo & libpayload revisions to take advantage of new goodness. Also update the default configuration, and provide two different configurations for coreboot-v2 and coreboot-v3, the latter showing off our new bootlog and LAR browsers. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Deleted: buildrom-devel/packages/coreinfo/conf/defconfig =================================================================== --- buildrom-devel/packages/coreinfo/conf/defconfig 2008-05-07 20:54:48 UTC (rev 188) +++ buildrom-devel/packages/coreinfo/conf/defconfig 2008-05-07 21:27:49 UTC (rev 189) @@ -1,18 +0,0 @@ -# -# Automatically generated make config: don't edit -# coreinfo version: 0.1.0 -# Wed Apr 9 15:45:52 2008 -# - -# -# General settings -# -CONFIG_SHOW_DATE_TIME=y - -# -# Modules -# -CONFIG_MODULE_COREBOOT=y -CONFIG_MODULE_CPUINFO=y -CONFIG_MODULE_PCI=y -CONFIG_MODULE_NVRAM=y Copied: buildrom-devel/packages/coreinfo/conf/defconfig-coreboot (from rev 188, buildrom-devel/packages/coreinfo/conf/defconfig) =================================================================== --- buildrom-devel/packages/coreinfo/conf/defconfig-coreboot (rev 0) +++ buildrom-devel/packages/coreinfo/conf/defconfig-coreboot 2008-05-07 21:27:49 UTC (rev 189) @@ -0,0 +1,20 @@ +# +# Automatically generated make config: don't edit +# coreinfo version: 0.1.0 +# Wed Apr 9 15:45:52 2008 +# + +# +# General settings +# +CONFIG_SHOW_DATE_TIME=y + +# +# Modules +# +CONFIG_MODULE_COREBOOT=y +CONFIG_MODULE_CPUINFO=y +CONFIG_MODULE_PCI=y +CONFIG_MODULE_NVRAM=y +# CONFIG_MODULE_BOOTLOG is not set +# CONFIG_MODULE_LAR is not set Added: buildrom-devel/packages/coreinfo/conf/defconfig-coreboot-v3 =================================================================== --- buildrom-devel/packages/coreinfo/conf/defconfig-coreboot-v3 (rev 0) +++ buildrom-devel/packages/coreinfo/conf/defconfig-coreboot-v3 2008-05-07 21:27:49 UTC (rev 189) @@ -0,0 +1,20 @@ +# +# Automatically generated make config: don't edit +# coreinfo version: 0.1.0 +# Wed May 7 14:47:11 2008 +# + +# +# General settings +# +CONFIG_SHOW_DATE_TIME=y + +# +# Modules +# +CONFIG_MODULE_COREBOOT=y +CONFIG_MODULE_CPUINFO=y +CONFIG_MODULE_PCI=y +CONFIG_MODULE_NVRAM=y +CONFIG_MODULE_BOOTLOG=y +CONFIG_MODULE_LAR=y Modified: buildrom-devel/packages/coreinfo/coreinfo.mk =================================================================== --- buildrom-devel/packages/coreinfo/coreinfo.mk 2008-05-07 20:54:48 UTC (rev 188) +++ buildrom-devel/packages/coreinfo/coreinfo.mk 2008-05-07 21:27:49 UTC (rev 189) @@ -1,5 +1,5 @@ COREINFO_URL=svn://coreboot.org/repos/trunk/payloads/coreinfo -COREINFO_TAG=3228 +COREINFO_TAG=3289 COREINFO_DIR=$(BUILD_DIR)/coreinfo COREINFO_SRC_DIR=$(COREINFO_DIR)/svn @@ -14,7 +14,11 @@ COREINFO_FETCH_LOG=$(COREINFO_LOG_DIR)/fetch.log endif -COREINFO_CONFIG=$(PACKAGE_DIR)/coreinfo/conf/defconfig +ifeq ($(CONFIG_COREBOOT_V3),y) +COREINFO_CONFIG=$(PACKAGE_DIR)/coreinfo/conf/defconfig-coreboot-v3 +else +COREINFO_CONFIG=$(PACKAGE_DIR)/coreinfo/conf/defconfig-coreboot +endif COREINFO_TARBALL=coreinfo-svn-$(COREINFO_TAG).tar.gz Modified: buildrom-devel/packages/libpayload/libpayload.mk =================================================================== --- buildrom-devel/packages/libpayload/libpayload.mk 2008-05-07 20:54:48 UTC (rev 188) +++ buildrom-devel/packages/libpayload/libpayload.mk 2008-05-07 21:27:49 UTC (rev 189) @@ -1,5 +1,5 @@ LIBPAYLOAD_URL=svn://coreboot.org/repos/trunk/payloads/libpayload -LIBPAYLOAD_TAG=3272 +LIBPAYLOAD_TAG=3289 LIBPAYLOAD_DIR=$(BUILD_DIR)/libpayload LIBPAYLOAD_SRC_DIR=$(LIBPAYLOAD_DIR)/svn

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buildrom: Bump the revision for coreinfo & libpayload
by Jordan Crouse 07 May '08

07 May '08

Bump the coreinfo & libpayload revisions - with this, we should be up to goodness. This also adjusts the default coreinfo config accordingly depending on the version of coreboot being used - this is so that v3 users can see the bootlog and LAR browsers in action. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

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Re: [coreboot] AMDk8 - HT routing
by Viswesh S 07 May '08

07 May '08

Hi, But when you read the registers of Node7, as the device is not there, what value will it return, if we try to read any register, say 0x6c for getting the default link. val = pci_read_config32(NODE_HT(7), 0x6c); // What value does get return, as node7 is not there. byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ Viswesh ----- Original Message ---- From: Marc Jones <marc.jones(a)amd.com> To: Viswesh S <viswesh_vichu(a)yahoo.com> Cc: coreboot(a)coreboot.org Sent: Wednesday, 7 May, 2008 9:38:13 PM Subject: Re: [coreboot] AMDk8 - HT routing Viswesh S wrote: > Hi, > > I am looking into the Linux bios code for AMD 64 boards. > > In the setup_coherent_ht_domain function, we have functions > setup_smp() and setup_smp2(). > > In the setup_smp2(), say the link1 is coherent and connected, we write > the routing table for it, but then we veriify the connection for Node7 > and then try to set the routing table registers for the link between 7 > and 1. > > //* > print_linkn("(0,1) link=", byte); > setup_row_direct(0,1, byte); // > setup_temp_row(0, 1); > > verify_connection(7); > /* We found 2 nodes so far */ > val = pci_read_config32(NODE_HT(7), 0x6c); > byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ > print_linkn("(1,0) link=", byte); > setup_row_local(7,1); > setup_remote_row_direct(1, 0, byte); > *// > > What is the logic reason behind checking the node7 here. > > In the case of my board, there is no Node7 itself and will the > pci_write(outb instruction) cause any unknown behaviour, as the node > is not present. > > Thanks, > > Viswesh > > ------------------------------------------------------------------------ > Explore your hobbies and interests. Click here to begin. > <http://in.rd.yahoo.com/tagline_groups_6/*http://in.promos.yahoo.com/groups/> Hi Viswesh, All AP nodes are node7 until they have been found and initialized by the BSP. The BSP looks at each active link and then sets the nodeids. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Unlimited freedom, unlimited storage. Get it now, on http://help.yahoo.com/l/in/yahoo/mail/yahoomail/tools/tools-08.html/

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r188 - buildrom-devel/packages/busybox
by svn＠coreboot.org 07 May '08

07 May '08

Author: myles Date: 2008-05-07 22:54:48 +0200 (Wed, 07 May 2008) New Revision: 188 Modified: buildrom-devel/packages/busybox/busybox.mk Log: This is a trivial patch which puts back a -P wget option that got deleted in Rev 171. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/packages/busybox/busybox.mk =================================================================== --- buildrom-devel/packages/busybox/busybox.mk 2008-05-07 19:24:04 UTC (rev 187) +++ buildrom-devel/packages/busybox/busybox.mk 2008-05-07 20:54:48 UTC (rev 188) @@ -26,7 +26,7 @@ $(SOURCE_DIR)/$(BUSYBOX_SOURCE): @ echo "Downloading busybox..." @ mkdir -p $(SOURCE_DIR) - @ wget $(WGET_Q) $(SOURCE_DIR) $(BUSYBOX_URL)/$(BUSYBOX_SOURCE) + @ wget $(WGET_Q) -P $(SOURCE_DIR) $(BUSYBOX_URL)/$(BUSYBOX_SOURCE) $(BUSYBOX_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(BUSYBOX_SOURCE) | $(BUSYBOX_STAMP_DIR) $(BUSYBOX_DIR) @ echo "Unpacking busybox..."

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coreboot May 2008