coreboot May 2008

coreboot@coreboot.org

79 participants
387 discussions

[PATCH] flashrom: Add SST39VF512, SST39VF010, SST39VF040 support
by Carl-Daniel Hailfinger 12 May '08

12 May '08

Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF series has the same IDs. Add short AMIC vendor ID to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-tmp4/flash.h =================================================================== --- flashrom-tmp4/flash.h (Revision 3296) +++ flashrom-tmp4/flash.h (Arbeitskopie) @@ -96,6 +96,7 @@ #define AM_29F016D 0xAD #define AMIC_ID 0x7F37 /* AMIC */ +#define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define ASD_ID 0x25 /* ASD, not listed in JEP106W */ #define ASD_AE49F2008 0x52 @@ -226,7 +227,10 @@ #define SST_39SF010 0xB5 #define SST_39SF020 0xB6 #define SST_39SF040 0xB7 +#define SST_39VF512 0xD4 +#define SST_39VF010 0xD5 #define SST_39VF020 0xD6 +#define SST_39VF040 0xD7 #define SST_49LF040B 0x50 #define SST_49LF040 0x51 #define SST_49LF020A 0x52 Index: flashrom-tmp4/flashchips.c =================================================================== --- flashrom-tmp4/flashchips.c (Revision 3296) +++ flashrom-tmp4/flashchips.c (Arbeitskopie) @@ -73,7 +73,10 @@ {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF512", SST_ID, SST_39VF512, 64, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF010", SST_ID, SST_39VF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF040", SST_ID, SST_39VF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, // assume similar to 004B, ignoring data sheet {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},

2 2

r3299 - trunk/util/flashrom
by svn＠coreboot.org 12 May '08

12 May '08

Author: hailfinger Date: 2008-05-12 16:25:31 +0200 (Mon, 12 May 2008) New Revision: 3299 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF series has the same IDs. Add short AMIC vendor ID to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-11 16:13:24 UTC (rev 3298) +++ trunk/util/flashrom/flash.h 2008-05-12 14:25:31 UTC (rev 3299) @@ -96,6 +96,7 @@ #define AM_29F016D 0xAD #define AMIC_ID 0x7F37 /* AMIC */ +#define AMIC_ID_NOPREFIX 0x37 /* AMIC */ #define ASD_ID 0x25 /* ASD, not listed in JEP106W */ #define ASD_AE49F2008 0x52 @@ -226,7 +227,10 @@ #define SST_39SF010 0xB5 #define SST_39SF020 0xB6 #define SST_39SF040 0xB7 +#define SST_39VF512 0xD4 +#define SST_39VF010 0xD5 #define SST_39VF020 0xD6 +#define SST_39VF040 0xD7 #define SST_49LF040B 0x50 #define SST_49LF040 0x51 #define SST_49LF020A 0x52 Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-11 16:13:24 UTC (rev 3298) +++ trunk/util/flashrom/flashchips.c 2008-05-12 14:25:31 UTC (rev 3299) @@ -73,7 +73,10 @@ {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF512", SST_ID, SST_39VF512, 64, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF010", SST_ID, SST_39VF010, 128, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF040", SST_ID, SST_39VF040, 512, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, // assume similar to 004B, ignoring data sheet {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},

1 0

Supermicro support - V3
by Viswesh S 12 May '08

12 May '08

Hi, Does Coreboot V3 support supermicro boards. I know that coreboot V2 support h8dmr from supermicro, just wanted to know about V3. Viswesh Best Jokes, Best Friends, Best Food and more. Go to http://in.promos.yahoo.com/groups/bestofyahoo/

2 1

proposed patch, notsigned off, comments welcome.
by ron minnich 11 May '08

11 May '08

This is a first try at a program to grok lxirqs. Sanity check first, I'm not signing this off yet. Are the enable and invert tests correct below? Long term goal is a program that will follow the IRQ through the magic rabbit hole and up to the CPU. I don't know how to do vr reads in user mode, however. Here's the current output on alix1c, which is strange looking to me. IRQ A, GPIO pin 0 Input Enabled and Not Inverted IRQ B, GPIO pin 7 Input Enabled and Inverted IRQ C, GPIO pin 12 Input Enabled and Inverted IRQ D, GPIO pin 13 Input Disabled and Not Inverted

2 2

r3298 - trunk/payloads/libpayload/i386
by svn＠coreboot.org 11 May '08

11 May '08

Author: uwe Date: 2008-05-11 18:13:24 +0200 (Sun, 11 May 2008) New Revision: 3298 Modified: trunk/payloads/libpayload/i386/sysinfo.c Log: Fix the build when serial console support is disabled (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/i386/sysinfo.c =================================================================== --- trunk/payloads/libpayload/i386/sysinfo.c 2008-05-11 15:51:31 UTC (rev 3297) +++ trunk/payloads/libpayload/i386/sysinfo.c 2008-05-11 16:13:24 UTC (rev 3298) @@ -35,7 +35,11 @@ */ struct sysinfo_t lib_sysinfo = { .cpu_khz = 200, +#ifdef CONFIG_SERIAL_CONSOLE .ser_ioport = CONFIG_SERIAL_IOBASE, +#else + .ser_ioport = 0x3f8, +#endif }; void lib_get_sysinfo(void)

1 0

r3297 - trunk/payloads/coreinfo
by svn＠coreboot.org 11 May '08

11 May '08

Author: uwe Date: 2008-05-11 17:51:31 +0200 (Sun, 11 May 2008) New Revision: 3297 Modified: trunk/payloads/coreinfo/Makefile Log: Quickfix to repair 'make clean; make menuconfig' (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/coreinfo/Makefile =================================================================== --- trunk/payloads/coreinfo/Makefile 2008-05-10 23:40:51 UTC (rev 3296) +++ trunk/payloads/coreinfo/Makefile 2008-05-11 15:51:31 UTC (rev 3297) @@ -65,7 +65,7 @@ all: prepare $(TARGET) -$(TARGET): $(OBJS) +$(TARGET): $(src)/.config $(OBJS) $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) -o $@ $(OBJS) $(Q)printf " STRIP $(subst $(shell pwd)/,,$(@))\n" @@ -85,7 +85,7 @@ $(Q)mkdir -p $(obj)/util/kconfig/lxdialog clean: - $(Q)rm -rf build/util build/*.conf build/*.cmd build/*.elf build/*.o + $(Q)rm -rf build/*.elf build/*.o distclean: clean $(Q)rm -rf build

1 0

ADLO for buildrom
by Myles Watson 11 May '08

11 May '08

This patch adds ADLO to buildrom using the gcc ported BOCHS BIOS. It boots Windows XP in QEMU. It still needs as86 to be installed because I didn't port the loader yet. Other things like making the loader understand the coreboot information to get the RAM map would be nice too. I'm attaching the ELF headers, since svn diff doesn't include binary files. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

10 61

GRUB2 Questions
by Joe 10 May '08

10 May '08

Hello, Are there any plans to load GRUB2's grub.cfg from a hard disk. This would make it editable to the end user. I think it is kind of important for a Multiboot Loader. Also is there any status update on GRUB2 booting UHCI? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

6 20

[PATCH] flashrom: Improve SPI abstraction
by Carl-Daniel Hailfinger 10 May '08

10 May '08

Improve flashrom SPI abstraction, second step. This paves the way to have a fully generic generic_spi_command without knowledge about any SPI controller. The third step would be calling SPI controller functions via a function pointer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich9/spi.c =================================================================== --- flashrom-ich9/spi.c (Revision 3294) +++ flashrom-ich9/spi.c (Arbeitskopie) @@ -179,13 +179,13 @@ whereas the IT8716F splits commands internally into address and non-address commands with the address in inverse wire order. That's why the register ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_command(uint16_t port, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +static int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; int i; do { - busy = inb(port) & 0x80; + busy = inb(it8716f_flashport) & 0x80; } while (busy); if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", @@ -194,27 +194,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], port + 1); + outb(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], port + 1); - outb(writearr[1], port + 7); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 4); + outb(writearr[2], it8716f_flashport + 3); + outb(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); - outb(writearr[4], port + 7); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 4); + outb(writearr[2], it8716f_flashport + 3); + outb(writearr[3], it8716f_flashport + 2); + outb(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -226,15 +226,15 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); + outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { - busy = inb(port) & 0x80; + busy = inb(it8716f_flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) { - readarr[i] = inb(port + 5 + i); + readarr[i] = inb(it8716f_flashport + 5 + i); } } @@ -244,7 +244,7 @@ int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (it8716f_flashport) - return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr); + return it8716f_spi_command(writecnt, readcnt, writearr, readarr); printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; }

2 2

r3296 - trunk/util/flashrom
by svn＠coreboot.org 10 May '08

10 May '08

Author: hailfinger Date: 2008-05-11 01:40:51 +0200 (Sun, 11 May 2008) New Revision: 3296 Modified: trunk/util/flashrom/spi.c Log: Improve flashrom SPI abstraction, second step. This paves the way to have a fully generic generic_spi_command without knowledge about any SPI controller. The third step would be calling SPI controller functions via a function pointer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-05-10 23:07:52 UTC (rev 3295) +++ trunk/util/flashrom/spi.c 2008-05-10 23:40:51 UTC (rev 3296) @@ -179,13 +179,13 @@ whereas the IT8716F splits commands internally into address and non-address commands with the address in inverse wire order. That's why the register ordering in case 4 and 5 may seem strange. */ -static int it8716f_spi_command(uint16_t port, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +static int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; int i; do { - busy = inb(port) & 0x80; + busy = inb(it8716f_flashport) & 0x80; } while (busy); if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", @@ -194,27 +194,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], port + 1); + outb(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], port + 1); - outb(writearr[1], port + 7); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 4); + outb(writearr[2], it8716f_flashport + 3); + outb(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], port + 1); - outb(writearr[1], port + 4); - outb(writearr[2], port + 3); - outb(writearr[3], port + 2); - outb(writearr[4], port + 7); + outb(writearr[0], it8716f_flashport + 1); + outb(writearr[1], it8716f_flashport + 4); + outb(writearr[2], it8716f_flashport + 3); + outb(writearr[3], it8716f_flashport + 2); + outb(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -226,15 +226,15 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); + outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { - busy = inb(port) & 0x80; + busy = inb(it8716f_flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) { - readarr[i] = inb(port + 5 + i); + readarr[i] = inb(it8716f_flashport + 5 + i); } } @@ -244,7 +244,7 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { if (it8716f_flashport) - return it8716f_spi_command(it8716f_flashport, writecnt, readcnt, writearr, readarr); + return it8716f_spi_command(writecnt, readcnt, writearr, readarr); printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); return 1; }

1 0

← Newer
1
...
24
25
26
27
28
29
30
...
39
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2008