coreboot March 2008

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r3146 - trunk/util/flashrom
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: uwe Date: 2008-03-15 00:55:58 +0100 (Sat, 15 Mar 2008) New Revision: 3146 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/flashrom.c Log: Re-add code erroneously removed in r3140. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-03-14 23:32:03 UTC (rev 3145) +++ trunk/util/flashrom/flash.h 2008-03-14 23:55:58 UTC (rev 3146) @@ -33,6 +33,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { + const char *vendor; const char *name; /* With 32bit manufacture_id and model_id we can cover IDs up to * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-03-14 23:32:03 UTC (rev 3145) +++ trunk/util/flashrom/flashchips.c 2008-03-14 23:55:58 UTC (rev 3146) @@ -26,202 +26,107 @@ #endif struct flashchip flashchips[] = { - {"Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, - probe_29f040b, erase_29f040b, write_29f040b}, - {"Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, - probe_29f040b, erase_29f040b, write_29f040b}, - {"Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024, - probe_29f040b, erase_29f040b, write_29f040b}, - {"AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, - probe_jedec, erase_chip_jedec, write_jedec}, - {"At29C040A", ATMEL_ID, AT_29C040A, 512, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"At29C020", ATMEL_ID, AT_29C020, 256, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"At49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"At49F002(N)T",ATMEL_ID, AT_49F002NT, 256, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, - {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, - probe_29f002, erase_29f002, write_29f002}, - {"MX25L4005", MX_ID, MX_25L4005, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"MX25L8005", MX_ID, MX_25L8005, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"MX25L3205", MX_ID, MX_25L3205, 4096, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, - probe_jedec, erase_chip_jedec, write_jedec}, - {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, - probe_28sf040, erase_28sf040, write_28sf040}, - {"SST39SF010A", SST_ID, SST_39SF010, 128, 4096, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"SST39SF020A", SST_ID, SST_39SF020, 256, 4096, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"SST39SF040", SST_ID, SST_39SF040, 512, 4096, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"SST39VF020", SST_ID, SST_39VF020, 256, 4096, - probe_jedec, erase_chip_jedec, write_39sf020}, + /******************************************************************************************************************************************************************************************************/ + /* Vendor Chip Vendor ID Chip ID TODO TODO Probe function Erase function Write function Read function */ + /******************************************************************************************************************************************************************************************************/ + {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, + {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, + {"AMD", "Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, + {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "At29C040A", ATMEL_ID, AT_29C040A, 512, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "At29C020", ATMEL_ID, AT_29C020, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "At49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "At49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, + {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, + {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, + {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, probe_28sf040, erase_28sf040, write_28sf040}, + {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, + {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, // assume similar to 004B, ignoring data sheet - {"SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, - - {"SST49LF040", SST_ID, SST_49LF040, 512, 4096, - probe_jedec, erase_49lf040, write_49lf040}, - {"SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, - probe_jedec, erase_49lf040, write_49lf040}, - {"SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, - probe_jedec, erase_49lf040, write_49lf040}, - {"SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, - {"SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, - {"SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, - {"SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024 , - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, - {"SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024 , - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024 , - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024 , - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"Pm49FL002", PMC_ID_NOPREFIX, PMC_49FL002, 256, 16 * 1024, - probe_jedec, erase_chip_jedec, write_49fl004}, - {"Pm49FL004", PMC_ID_NOPREFIX, PMC_49FL004, 512, 64 * 1024, - probe_jedec, erase_chip_jedec, write_49fl004}, - {"Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"W29C011", WINBOND_ID, W_29C011, 128, 128, - probe_jedec, erase_chip_jedec, write_jedec}, - {"W29C040P", WINBOND_ID, W_29C040P, 512, 256, - probe_jedec, erase_chip_jedec, write_jedec}, - {"W29C020C", WINBOND_ID, W_29C020C, 256, 128, - probe_jedec, erase_chip_jedec, write_jedec}, - {"W29EE011", WINBOND_ID, W_29C011, 128, 128, - probe_w29ee011,erase_chip_jedec, write_jedec}, - {"W49F002U", WINBOND_ID, W_49F002U, 256, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"W49V002A", WINBOND_ID, W_49V002A, 256, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, - probe_jedec, erase_chip_jedec, write_39sf020}, - {"W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, - {"M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, - probe_82802ab, erase_82802ab, write_82802ab}, - {"M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, - {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, - probe_29f040b, erase_29f040b, write_29f040b}, - {"M25P05-A", ST_ID, ST_M25P05A, 64, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P10-A", ST_ID, ST_M25P10A, 128, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P20", ST_ID, ST_M25P20, 256, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P40", ST_ID, ST_M25P40, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P80", ST_ID, ST_M25P80, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P16", ST_ID, ST_M25P16, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P32", ST_ID, ST_M25P32, 4096, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P64", ST_ID, ST_M25P64, 8192, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"M25P128", ST_ID, ST_M25P128, 16384, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"82802ab", INTEL_ID, 173, 512, 64 * 1024, - probe_82802ab, erase_82802ab, write_82802ab}, - {"82802ac", INTEL_ID, 172, 1024, 64 * 1024, - probe_82802ab, erase_82802ab, write_82802ab}, - {"F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, - probe_jedec, erase_chip_jedec, write_49f002}, + {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF040", SST_ID, SST_49LF040, 512, 4096, probe_jedec, erase_49lf040, write_49lf040}, + {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, probe_jedec, erase_49lf040, write_49lf040}, + {"SST", "SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, probe_jedec, erase_49lf040, write_49lf040}, + {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, + {"SST", "SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, + {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, + {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, + {"PMC", "Pm49FL002", PMC_ID_NOPREFIX,PMC_49FL002, 256, 16 * 1024, probe_jedec, erase_chip_jedec, write_49fl004}, + {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_49fl004}, + {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, probe_jedec, erase_chip_jedec, write_jedec}, + {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, probe_jedec, erase_chip_jedec, write_jedec}, + {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, + {"Winbond", "W29EE011", WINBOND_ID, W_29C011, 128, 128, probe_w29ee011, erase_chip_jedec, write_jedec}, + {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond/N.", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Winbond/N.", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Winbond/N.", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Winbond/N.", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, + {"ST", "M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, + {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, + {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, + {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"Intel", "82802ab", INTEL_ID, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, + {"Intel", "82802ac", INTEL_ID, 172, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, + {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, probe_jedec, erase_chip_jedec, write_49f002}, #ifndef DISABLE_DOC - {"MD-2802 (M-Systems DiskOnChip Millennium Module)", - MSYSTEMS_ID, MSYSTEMS_MD2802,8, 8 * 1024, - probe_md2802, erase_md2802, write_md2802, read_md2802}, + {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, probe_md2802, erase_md2802, write_md2802, read_md2802}, #endif - {"LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, - probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, - {"S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, - probe_jedec, erase_chip_jedec, write_49f002}, - {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, 0, 0, - probe_spi, NULL, NULL}, - {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, - probe_spi, NULL, NULL}, - {"PMC unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, - probe_spi, NULL, NULL}, - {"SST unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, - probe_spi, NULL, NULL}, - {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, - probe_spi, NULL, NULL}, + {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, + {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"EON", "unknown SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, + {"Macronix", "unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, + {"PMC", "unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, + {"SST", "unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, + {"ST", "unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, {NULL,} }; Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-03-14 23:32:03 UTC (rev 3145) +++ trunk/util/flashrom/flashrom.c 2008-03-14 23:55:58 UTC (rev 3146) @@ -200,7 +200,7 @@ printf("Supported ROM chips:\n\n"); for (i = 0; flashchips[i].name != NULL; i++) - printf("%s\n", flashchips[i].name); + printf("%s %s\n", flashchips[i].vendor, flashchips[i].name); } void usage(const char *name)

1 0

Re: [coreboot] r643 - in coreboot-v3/mainboard/amd: . db800
by Peter Stuge 14 Mar '08

14 Mar '08

On Fri, Mar 14, 2008 at 10:15:03PM +0100, svn(a)coreboot.org wrote: > +config BOARD_AMD_DB800 > + bool "DB800" > + select ARCH_X86 > + select CPU_AMD_GEODELX > + select OPTION_TABLE > + select NORTHBRIDGE_AMD_GEODELX > + select SOUTHBRIDGE_AMD_CS5536 > + select SUPERIO_WINBOND_W83627HF > + select PIRQ_TABLE > + help > + AMD DB800 Geode LX development board. > + /config/("northbridge/amd/geodelx/apic"); > + /config/("northbridge/amd/geodelx/domain"); > + /config/("northbridge/amd/geodelx/pci"); > + /config/("southbridge/amd/cs5536/dts"); > + /config/("superio/winbond/w83627hf/dts"); Can we reduce this redundancy? Also, does anyone have ideas for cmos.layout for v3? OPTION_TABLE is includes the code for that, correct? (Bad name.) I want to be able to disconnect v3 completely from NVRAM and make it an optional feature. //Peter

2 1

r3145 - trunk/util/flashrom
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: linux_junkie Date: 2008-03-15 00:32:03 +0100 (Sat, 15 Mar 2008) New Revision: 3145 Modified: trunk/util/flashrom/flashchips.c Log: Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-03-14 17:20:59 UTC (rev 3144) +++ trunk/util/flashrom/flashchips.c 2008-03-14 23:32:03 UTC (rev 3145) @@ -165,7 +165,7 @@ {"M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, - probe_jedec, erase_chip_jedec, write_jedec}, + probe_82802ab, erase_82802ab, write_82802ab}, {"M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024,

1 0

lar copy patch
by Myles Watson 14 Mar '08

14 Mar '08

This patch adds copy functionality to lar via lar -L srclar.file It allows you to use payloads, bootblocks, or other entries from one lar when creating or adding to another. changes by file: util/lar/lar.c: change usage add srcarchivename parameter for create_lar and add_lar add lar_copy functionality to create_lar and add_lar add -C keep for using the same compression as srclar util/lar/lar.h: change invalid to invalid_or_keep in algo_strings util/lar/lib.c: pull out function add_entry from add_files util/lar/lib.h: add prototypes for add_entry and lar_copy change prototype for create_lar (wonder why add_lar doesn't have one) fix whitespace util/lar/stream.c: pull out helper function file_in_list_where from file_in_list add lar_copy This is a test of the copy functionality of lar. I'll use C++-style comments // here's the original lar file [myles@orangutan svn]$ build/util/lar/lar -l build/coreboot.rom normal/option_table (932 bytes @0x50);loadaddress 0x0 entry 0x0 normal/initram/segment0 (432 bytes @0x450);loadaddress 0x0 entry 0x0x42 normal/stage2/segment0 (191792 bytes, zeroes compressed to 1 bytes @0x650);loadaddress 0x0xa540 entry 0x0x2000 normal/stage2/segment1 (28172 bytes, lzma compressed to 15083 bytes @0x6b0);loadaddress 0x0x2000 entry 0x0x2000 normal/stage2/segment2 (5420 bytes, lzma compressed to 312 bytes @0x41f0);loadaddress 0x0x9000 entry 0x0x2000 bootblock (20480 bytes @0xfb000) Total size = 37688B 36KB (0x9338) //create a new 256K lar file called bootblock.rom which has the same bootblock as coreboot.rom [myles@orangutan svn]$ build/util/lar/lar -c -s 256K bootblock.rom -L build/coreboot.rom //create a new lar file with uncompressed normal/stage2 [myles@orangutan svn]$ build/util/lar/lar -c -s 256K normal_stage2.rom -L build/coreboot.rom nocompress:normal/stage2:stage2 //create a new lar file with lzma compressed normal/init [myles@orangutan svn]$ build/util/lar/lar -c -s 256K normal_init.rom -L build/coreboot.rom -C lzma normal/init //create a new lar file with normal/opt compressed the same as it was [myles@orangutan svn]$ build/util/lar/lar -c -s 256K normal_opt.rom -L build/coreboot.rom -C keep normal/opt //create a new 1M lar using the bootblock in bootblock.rom [myles@orangutan svn]$ build/util/lar/lar -c -s 1M new.rom -L bootblock.rom //add back in the components with the correct compression [myles@orangutan svn]$ build/util/lar/lar -a new.rom -L normal_opt.rom -C none normal/ [myles@orangutan svn]$ build/util/lar/lar -a new.rom -L normal_init.rom -C none normal/init //use the verbose switch to see what you're getting [myles@orangutan svn]$ build/util/lar/lar -av new.rom -L normal_stage2.rom -C lzma stage2:normal/stage2 ... adding stage2:normal/stage2 stage2:normal/stage2 (lzma) matches stage2/segment0 => normal/stage2/segment0. stage2:normal/stage2 (lzma) matches stage2/segment1 => normal/stage2/segment1. stage2:normal/stage2 (lzma) matches stage2/segment2 => normal/stage2/segment2. //diff the two files [myles@orangutan svn]$ diff new.rom build/coreboot.rom // There's no difference I think it would be nice if lar would warn you (or stop you) when you try to add a duplicate entry. Maybe that will be the next patch. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com>

3 8

Via epia
by jtd 14 Mar '08

14 Mar '08

Hi all, I have a mother board with the following 00:00.0 Host bridge: VIA Technologies, Inc. VT8623 [Apollo CLE266] 00:01.0 PCI bridge: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] 00:08.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:0d.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) 00:10.3 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 82) 00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge 00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) 00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller (rev 50) 01:00.0 VGA compatible controller: VIA Technologies, Inc. VT8623 [Apollo CLE266] integrated CastleRock graphics (rev 03) The superio is ITE IT8705F (markings on the chip) superiotool r3127 Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x3) at 0x2e Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x3) at 0x4e Flash is a 32 pin PLCC winbond 49V002AP and is flashable by the dos prog (actually i run freedos over tftp). I already have the v2 tree installed and can compile the epia / epia-m target . Since these have vt1611 superio, how do I go about porting to my board with the rtl8139 and IT8705F. Rgds JTD

6 13

Barcelona build
by David Edrich 14 Mar '08

14 Mar '08

Is the Family 10h, Barcelona support, checked into LinuxBIOS somewhere? Is there a motherboard port that supports Barcelona CPUs? - Thanks,

2 1

r643 - in coreboot-v3/mainboard/amd: . db800
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: hailfinger Date: 2008-03-14 22:15:03 +0100 (Fri, 14 Mar 2008) New Revision: 643 Added: coreboot-v3/mainboard/amd/db800/ coreboot-v3/mainboard/amd/db800/Kconfig coreboot-v3/mainboard/amd/db800/Makefile coreboot-v3/mainboard/amd/db800/cmos.layout coreboot-v3/mainboard/amd/db800/dts coreboot-v3/mainboard/amd/db800/initram.c coreboot-v3/mainboard/amd/db800/irq_tables.h coreboot-v3/mainboard/amd/db800/stage1.c Modified: coreboot-v3/mainboard/amd/Kconfig Log: AMD DB800 support, ported from v2. Tested on real hardware, some weirdness remains, probably related to IRQ routing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/mainboard/amd/Kconfig =================================================================== --- coreboot-v3/mainboard/amd/Kconfig 2008-03-13 14:16:38 UTC (rev 642) +++ coreboot-v3/mainboard/amd/Kconfig 2008-03-14 21:15:03 UTC (rev 643) @@ -23,6 +23,18 @@ prompt "Mainboard model" depends on VENDOR_AMD +config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + AMD DB800 Geode LX development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -36,5 +48,6 @@ endchoice +source "mainboard/amd/db800/Kconfig" source "mainboard/amd/norwich/Kconfig" Copied: coreboot-v3/mainboard/amd/db800/Kconfig (from rev 630, coreboot-v3/mainboard/amd/norwich/Kconfig) =================================================================== --- coreboot-v3/mainboard/amd/db800/Kconfig (rev 0) +++ coreboot-v3/mainboard/amd/db800/Kconfig 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the default mainboard name. + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + # TODO: Fix PCI ID. + default 0x1022 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem vendor ID. + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + # TODO: Fix PCI ID. + default 0x2323 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem device ID. + Copied: coreboot-v3/mainboard/amd/db800/Makefile (from rev 630, coreboot-v3/mainboard/amd/norwich/Makefile) =================================================================== --- coreboot-v3/mainboard/amd/db800/Makefile (rev 0) +++ coreboot-v3/mainboard/amd/db800/Makefile 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Copied: coreboot-v3/mainboard/amd/db800/cmos.layout (from rev 630, coreboot-v3/mainboard/artecgroup/dbe61/cmos.layout) =================================================================== --- coreboot-v3/mainboard/amd/db800/cmos.layout (rev 0) +++ coreboot-v3/mainboard/amd/db800/cmos.layout 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Copied: coreboot-v3/mainboard/amd/db800/dts (from rev 630, coreboot-v3/mainboard/pcengines/alix1c/dts) =================================================================== --- coreboot-v3/mainboard/amd/db800/dts (rev 0) +++ coreboot-v3/mainboard/amd/db800/dts 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; + }; + ioport@46 { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + }; + }; +}; Copied: coreboot-v3/mainboard/amd/db800/initram.c (from rev 630, coreboot-v3/mainboard/amd/norwich/initram.c) =================================================================== --- coreboot-v3/mainboard/amd/db800/initram.c (rev 0) +++ coreboot-v3/mainboard/amd/db800/initram.c 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <northbridge/amd/geodelx/raminit.h> + +/* #include <device/smbus.h> + * TODO: figure out how smbus functions should be done. See smbus_ops.c + */ +extern int smbus_read_byte(u16 device, u8 address); + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +u8 spd_read_byte(u16 device, u8 address) +{ + u8 spdbyte; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + spdbyte = smbus_read_byte(device, address); + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); + + return spdbyte; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the AMD DB800 development platform. + * It might seem that you could somehow do these functions in, e.g., the cpu + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} Copied: coreboot-v3/mainboard/amd/db800/irq_tables.h (from rev 630, coreboot-v3/mainboard/pcengines/alix1c/irq_tables.h) =================================================================== --- coreboot-v3/mainboard/amd/db800/irq_tables.h (rev 0) +++ coreboot-v3/mainboard/amd/db800/irq_tables.h 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,81 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <pirq_routing.h> + +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * AMD DB800 interrupt wiring. + * + * Devices are: + * + * FIXME + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, + } +}; Copied: coreboot-v3/mainboard/amd/db800/stage1.c (from rev 630, coreboot-v3/mainboard/pcengines/alix1c/stage1.c) =================================================================== --- coreboot-v3/mainboard/amd/db800/stage1.c (rev 0) +++ coreboot-v3/mainboard/amd/db800/stage1.c 2008-03-14 21:15:03 UTC (rev 643) @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +}

1 0

[PATCH 5/5] Intel 3100, version 3: Intel 3100 development kit mainboard
by Ed Swierk 14 Mar '08

14 Mar '08

This patch implements support for the Intel 3100 Development Kit mainboard, aka "Mt. Arvon". Also attached is the output of lspci -tnvn, lspci -vv, and lspci -xxxx. --Ed

3 4

[PATCH 4/5] Intel 3100, version 3: northbridge and RAM controller support
by Ed Swierk 14 Mar '08

14 Mar '08

This patch implements support for the Intel 3100 integrated northbridge and RAM controller. This is largely based on the existing Intel E7520/E7525 code. --Ed

2 4

[PATCH 3/5] Intel 3100, version 3
by Ed Swierk 14 Mar '08

14 Mar '08

This patch implements support for Intel 3100 integrated southbridge devices. This is largely based on the existing Intel 6300esb code. --Ed

3 5

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coreboot March 2008