coreboot March 2008

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r3138 - trunk/util/flashrom
by svn＠coreboot.org 13 Mar '08

13 Mar '08

Author: uwe Date: 2008-03-13 19:41:07 +0100 (Thu, 13 Mar 2008) New Revision: 3138 Modified: trunk/util/flashrom/board_enable.c Log: Also print the required -m option in --list-supported output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-03-13 12:43:31 UTC (rev 3137) +++ trunk/util/flashrom/board_enable.c 2008-03-13 18:41:07 UTC (rev 3138) @@ -506,8 +506,16 @@ printf("\nSupported mainboards (this list is not exhaustive!):\n\n"); - for (i = 0; board_pciid_enables[i].name != NULL; i++) - printf("%s\n", board_pciid_enables[i].name); + for (i = 0; board_pciid_enables[i].name != NULL; i++) { + if (board_pciid_enables[i].lb_vendor != NULL) { + printf("%s (-m %s:%s)\n", board_pciid_enables[i].name, + board_pciid_enables[i].lb_vendor, + board_pciid_enables[i].lb_part); + } else { + printf("%s (autodetected)\n", + board_pciid_enables[i].name); + } + } printf("\nSee also: http://coreboot.org/Flashrom\n"); }

1 0

r642 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 13 Mar '08

13 Mar '08

Author: uwe Date: 2008-03-13 15:16:38 +0100 (Thu, 13 Mar 2008) New Revision: 642 Modified: coreboot-v3/northbridge/amd/geodelx/domain coreboot-v3/northbridge/amd/geodelx/geodelink.h coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/northbridge/amd/geodelx/geodelxinit.c coreboot-v3/northbridge/amd/geodelx/grphinit.c coreboot-v3/northbridge/amd/geodelx/raminit.c coreboot-v3/northbridge/amd/geodelx/vsmsetup.c Log: Cosmetic fixes, coding style issues, added comments (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/northbridge/amd/geodelx/domain =================================================================== --- coreboot-v3/northbridge/amd/geodelx/domain 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/domain 2008-03-13 14:16:38 UTC (rev 642) @@ -22,7 +22,7 @@ { device_operations = "geodelx_north_domain"; - /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "0"; + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "0"; }; Modified: coreboot-v3/northbridge/amd/geodelx/geodelink.h =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-03-13 14:16:38 UTC (rev 642) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef GEODELINK_H -#define GEODELINK_H +#ifndef NORTHBRIDGE_AMD_GEODE_GEODELINK_H +#define NORTHBRIDGE_AMD_GEODE_GEODELINK_H struct gliutable { unsigned long desc_name; @@ -75,4 +75,4 @@ static const struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; -#endif /* GEODELINK_H */ +#endif /* NORTHBRIDGE_AMD_GEODE_GEODELINK_H */ Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-03-13 14:16:38 UTC (rev 642) @@ -43,7 +43,6 @@ { } - /** * TODO. * @@ -67,8 +66,8 @@ systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); systop += 4 * 1024; /* 4K */ } else { - systop = - (((sizeram() - nb_dm->geode_video_mb) * 1024) - SMM_SIZE) * 1024; + systop = (((sizeram() - nb_dm->geode_video_mb) * 1024) + - SMM_SIZE) * 1024; } return systop; @@ -82,10 +81,7 @@ */ static void geodelx_northbridge_init(struct device *dev) { - /* struct msr msr; */ - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - enable_shadow(dev); } @@ -162,7 +158,7 @@ ram_resource(dev, idx++, 0, 640); /* 1 MB .. (Systop - 1 MB) (in KB) */ ram_resource(dev, idx++, 1024, - (get_systop(nb_dm)/1024) - 1024); + (get_systop(nb_dm) / 1024) - 1024); } phase4_assign_resources(&dev->link[0]); @@ -189,7 +185,7 @@ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); -// northbridge_init_early(); + /* northbridge_init_early(); */ chipsetinit(); printk(BIOS_SPEW, "Before VSA:\n"); @@ -198,7 +194,7 @@ do_vsmbios(); printk(BIOS_SPEW, "After VSA:\n"); /* print_conf(); */ -printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); graphics_init((u8)nb_dm->geode_video_mb); pci_set_method(dev); } @@ -254,9 +250,10 @@ .ops_pci_bus = &pci_cf8_conf1, }; -/** Operations for when the northbridge is running a PCI device. */ -/** Note that phase3 scan is done in the domain, - * and MUST NOT be done here too +/** + * Operations for when the northbridge is running a PCI device. + * + * Note that phase3 scan is done in the domain, and MUST NOT be done here too. */ struct device_operations geodelx_north_pci = { .id = {.type = DEVICE_ID_PCI, Modified: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -25,7 +25,6 @@ #include <amd_geodelx.h> #include "geodelink.h" - static struct msrinit clock_gating_default[] = { {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}}, @@ -204,6 +203,7 @@ static void SMMGL1Init(const struct gliutable *gl) { struct msr msr; + printk(BIOS_DEBUG, "%s:\n", __FUNCTION__); msr.hi = gl->hi; @@ -219,9 +219,10 @@ } /** - * Set up all GeodeLink interfaces. Iterate over the table until done. + * Set up all GeodeLink interfaces. * - * Case out on the link type, and call the appropriate function. + * Iterate over the table until done. Case out on the link type, + * and call the appropriate function. * * @param gl A GeodeLink table descriptor. */ @@ -288,7 +289,8 @@ * translates to a base of 0x00100000 and top of 0xffbf0000 * base of 1M and top of around 256M. */ - /* we have to create a page-aligned (4KB page) address + + /* We have to create a page-aligned (4KB page) address * for base and top. * So we need a high page aligned addresss (pah) and * low page aligned address (pal) pah is from msr.hi @@ -319,10 +321,11 @@ msr.lo, msr.hi); wrmsr(GLPCI_RC2, msr); - /* This is done elsewhere already, but it does no harm to do + /* + * This is done elsewhere already, but it does no harm to do * it more than once. - */ - /* Write serialize memory hole to PCI. Need to to unWS when + * + * Write serialize memory hole to PCI. Need to to unWS when * something is shadowed regardless of cachablility. */ msr.lo = 0x021212121; /* Cache disabled and write serialized. */ @@ -708,7 +711,6 @@ printk(BIOS_DEBUG, "L2 cache enabled\n"); } - /** * Set up all LX cache registers, L1, L2, and x86. */ @@ -767,8 +769,8 @@ /* Set ROM cache properties for runtime. */ msr = rdmsr(CPU_RCONF_DEFAULT); - msr.hi &= ~(0xFF << 24); // clear ROMRC - msr.hi |= ROMRC_RCONF_SAFE << 24; // set WS, CD, WP + msr.hi &= ~(0xFF << 24); /* Clear ROMRC. */ + msr.hi |= ROMRC_RCONF_SAFE << 24; /* Set WS, CD, WP. */ wrmsr(CPU_RCONF_DEFAULT, msr); } Modified: coreboot-v3/northbridge/amd/geodelx/grphinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -23,9 +23,11 @@ #include <console.h> #include <statictree.h> - /* - * This function mirrors the Graphics_Init routine in GeodeROM. - */ +/** + * This function mirrors the Graphics_Init routine in GeodeROM. + * + * @param video_mb Size of the video RAM in 2 MB chunks. + */ void graphics_init(u8 video_mb) { u16 wClassIndex, wData, res; @@ -34,7 +36,7 @@ printk(BIOS_DEBUG, "Graphics init...\n"); /* Call SoftVG with the main configuration parameters. */ - /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ + /* NOTE: SoftVG expects the memory size to be given in 2MB blocks. */ wClassIndex = (VRC_VG << 8) + VG_CONFIG; @@ -48,13 +50,12 @@ * PLL Reference Clock Bypass(0) 0, Default */ - /* Video RAM has to be given in 2MB chunks - * the value is read @ 7:1 (looks like video_mb & ~1) - * so we can add the real value in megabytes. + /* Video RAM has to be given in 2MB chunks. + * The value is read @ 7:1 (looks like video_mb & ~1) + * so we can add the real value in megabytes. */ - - wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | - VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); vr_write(wClassIndex, wData); res = vr_read(wClassIndex); Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-03-13 14:16:38 UTC (rev 642) @@ -36,17 +36,15 @@ u8 spd_read_byte(u16 device, u8 address); /** - * Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port, - * to ensure the message is visible. - * + * Halt and Catch Fire. Print an error, then loop, sending NULLs on + * serial port, to ensure the message is visible. */ - void hcf(void) { printk(BIOS_EMERG, "DIE\r\n"); - /* this guarantees we flush the UART fifos (if any) and also - * ensures that things, in general, keep going so no debug output - * is lost + + /* This guarantees we flush the UART FIFOs (if any) and also ensures + * that things, in general, keep going so no debug output is lost. */ while (1) printk(BIOS_EMERG, "\r"); @@ -97,12 +95,12 @@ } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT; - /*; Field: DIMM size - *; EEPROM byte usage: (3) Number of Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks + /* Field: DIMM size + * EEPROM byte usage: (3) Number of Row Addresses + * (4) Number of Column Addresses + * (5) Number of DIMM Banks + * (31) Module Bank Density + * Size = Module Density * Module Banks */ banner(BIOS_DEBUG, "SPDNUMROWS"); @@ -228,7 +226,7 @@ printk(BIOS_DEBUG, "ddr max speed is %d\n", speed); /* Current speed > max speed? */ if (geode_link_speed() > speed) { - printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed\n"); + printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink speed.\n"); post_code(POST_PLL_MEM_FAIL); hlt(); } @@ -562,7 +560,7 @@ { struct msr msr; - /* Set Timing Control */ + /* Set Timing Control. */ msr = rdmsr(MC_CF1017_DATA); msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT); if (geode_link_speed() < 334) @@ -571,7 +569,7 @@ msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT); wrmsr(MC_CF1017_DATA, msr); - /* Set Refresh Staggering */ + /* Set Refresh Staggering. */ msr = rdmsr(MC_CF07_DATA); msr.lo &= ~0xF0; msr.lo |= 0x40; /* Set refresh to 4 SDRAM clocks. */ @@ -610,8 +608,8 @@ /* Check that the memory is not overclocked. */ check_ddr_max(dimm0, dimm1); - /* Size the DIMMS. - * This is gross. It is an artifact of our move to parametes instead of + /* Size the DIMMs. + * This is gross. It is an artifact of our move to parameters instead of * #defines. FIXME! The fix is trivial but I want to see it work first. */ post_code(POST_MEM_SETUP3); @@ -623,7 +621,7 @@ post_code(POST_MEM_SETUP5); set_cas(dimm0, dimm1); - /* Set all the other latencies here (tRAS, tRP...). */ + /* Set all the other latencies here (tRAS, tRP, ...). */ set_latencies(dimm0, dimm1); /* Set Extended Mode Registers. */ @@ -788,9 +786,8 @@ *ptr = (unsigned long)i; } - /* SWAPSiF for PBZ 4112 (Errata 34) - * Check for failed DLL settings now that we have done a - * memory write. + /* SWAPSiF for PBZ 4112 (Errata 34). + * Check for failed DLL settings now that we have done a memory write. */ msr = rdmsr(GLCP_DELAY_CONTROLS); if ((msr.lo & 0x7FF) == 0x104) { @@ -798,7 +795,7 @@ * count flag (depending on where it counts from etc). */ - /* The we are about to perform clears the PM_SSC + /* The operation we are about to perform clears the PM_SSC * register in the CS5536 so will need to store the S3 * resume flag in NVRAM otherwise it would do a normal boot. */ Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-03-13 13:31:16 UTC (rev 641) +++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-03-13 14:16:38 UTC (rev 642) @@ -1,27 +1,30 @@ /* - * Copyright (C) 2000 Erik Arjan Hendriks - * Copyright (C) 2000 Scyld Computing Corporation - * Copyright (C) 2001 University of California. LA-CC Number 01-67. - * Copyright (C) 2005 Nick.Barker9(a)btinternet.com - * Copyright (C) 2007 coresystems GmbH + * This file is part of the coreboot project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2000 Erik Arjan Hendriks + * Copyright (C) 2000 Scyld Computing Corporation + * Copyright (C) 2001 University of California. LA-CC Number 01-67. + * Copyright (C) 2005 Nick.Barker9(a)btinternet.com + * Copyright (C) 2007 coresystems GmbH * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * * LA-CC is the Los Alamos Control and Compliance Number, see also: * http://supply.lanl.gov/property/customs/eximguide/default.shtml */ + #include <types.h> #include <console.h> #include <device/device.h> @@ -31,82 +34,93 @@ #include <amd_geodelx.h> #include <lar.h> -#define VSA2_BUFFER 0x60000 +#define VSA2_BUFFER 0x60000 #define VSA2_ENTRY_POINT 0x60020 - -/* The address arguments to this function are PHYSICAL ADDRESSES */ +/** + * TODO. + * + * The address arguments to this function are PHYSICAL ADDRESSES! + * + * @param smm TODO. + * @param sysm TODO. + */ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm) { u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; u16 entryLo = (VSA2_ENTRY_POINT & 0xffff); __asm__ __volatile__( - // paranoia -- does ecx get saved? not sure. This is - // the easiest safe thing to do. + /* Paranoia -- does ecx get saved? not sure. This is + * the easiest safe thing to do. + */ " pushal \n" - /* save the stack */ + /* Save the stack. */ " mov %%esp, __stack \n" " jmp 1f \n" "__stack: .long 0 \n" "1:\n" - /* get devfn into %%ecx */ + /* Get devfn into %%ecx. */ " movl %%esp, %%ebp \n" - /* Get the smm and sysm args into ecx and edx */ + /* Get the smm and sysm args into ecx and edx. */ " movl %0, %%ecx \n" " movl %1, %%edx \n" - /* load 'our' gdt */ + /* Load 'our' gdt. */ " lgdt %%cs:__mygdtaddr \n" - /* This configures CS properly for real mode. */ + /* This configures CS properly for real mode. */ " ljmp $0x28, $__rms_16bit\n" "__rms_16bit: \n" " .code16 \n" /* 16 bit code from here on... */ - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ + /* Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ " mov $0x30, %%ax \n" " mov %%ax, %%ds \n" " mov %%ax, %%es \n" " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n" - /* Turn off protection (bit 0 in CR0) */ + /* Turn off protection (bit 0 in CR0). */ " movl %%cr0, %%eax \n" " andl $0xFFFFFFFE, %%eax \n" " movl %%eax, %%cr0 \n" - /* Now really going into real mode */ + /* Now really going into real mode. */ " ljmp $0, $__rms_real\n" "__rms_real: \n" - /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. + /* Put the stack at the end of page zero. + * That way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. */ - /* Setup a stack */ + /* Setup a stack. */ " mov $0x0, %%ax \n" " mov %%ax, %%ss \n" " movl $0x1000, %%eax \n" " movl %%eax, %%esp \n" - /* Dump zeros in the other segregs */ + /* Dump zeros in the other segregs. */ " mov %%ax, %%es \n" - /* FixMe: Big real mode for gs, fs? */ + /* FIXME: Big real mode for gs, fs? */ " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov $0x40, %%ax \n" " mov %%ax, %%ds \n" - //" mov %%cx, %%ax \n" + /* " mov %%cx, %%ax \n" */ " movl %0, %%ecx \n" " movl %1, %%edx \n" - /* call the VSA2 entry point address */ + /* Call the VSA2 entry point address. */ " lcall %2, %3\n" - /* if we got here, just about done. - * Need to get back to protected mode */ + /* If we got here, just about done. + * Need to get back to protected mode. + */ " movl %%cr0, %%eax \n" " orl $0x0000001, %%eax\n" /* PE = 1 */ " movl %%eax, %%cr0 \n" - /* Now that we are in protected mode jump to a 32 bit code segment. */ + /* Now that we are in protected mode, + * jump to a 32 bit code segment. + */ " data32 ljmp $0x10, $vsmrestart\n" "vsmrestart:\n" " .code32\n" @@ -116,7 +130,7 @@ " mov %%ax, %%fs \n" " mov %%ax, %%gs \n" " mov %%ax, %%ss \n" - /* restore proper gdt */ + /* Restore proper gdt. */ " lgdt %%cs:gdtarg \n" ".globl vsm_exit \n" "vsm_exit: \n" @@ -129,7 +143,7 @@ __asm__(".text\n" "real_mode_switch_end:\n"); extern char real_mode_switch_end[]; -// andrei: some VSA virtual register helpers: raw read and MSR read +/* andrei: Some VSA virtual register helpers: raw read and MSR read. */ u32 VSA_vrRead(u16 classIndex) { @@ -167,46 +181,44 @@ { unsigned char *buf; int i; - struct mem_file archive; - struct mem_file file; + struct mem_file archive, file; printk(BIOS_ERR, "do_vsmbios\n"); - /* clear vsm bios data area */ - for (i = 0x400; i < 0x500; i++) { + /* Clear VSM BIOS data area. */ + for (i = 0x400; i < 0x500; i++) *(volatile unsigned char *)i = 0; - } init_archive(&archive); - if (find_file(&archive, "blob/vsa", &file)){ + if (find_file(&archive, "blob/vsa", &file)) die("FATAL: NO VSA found!\n"); - } - if (process_file(&file, (void *)VSA2_BUFFER)) { + if (process_file(&file, (void *)VSA2_BUFFER)) die("FATAL: Processing /blob/vsa failed\n"); - } buf = (unsigned char *)VSA2_BUFFER; - printk(BIOS_DEBUG, "buf ilen %d real len %uld\n", file.len, file.reallen); + printk(BIOS_DEBUG, "buf ilen %d real len %uld\n", + file.len, file.reallen); printk(BIOS_DEBUG, "buf %p *buf %d buf[256k] %d\n", - buf, buf[0], buf[SMM_SIZE * 1024]); + buf, buf[0], buf[SMM_SIZE * 1024]); printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n", - buf[0x20], buf[0x21], buf[0x22], buf[0x23]); - /* check for post code at start of vsainit.bin. If you don't see it, - don't bother. */ + buf[0x20], buf[0x21], buf[0x22], buf[0x23]); + /* Check for POST code at start of vsainit.bin. If you don't see it, + * don't bother. + */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) { die("FATAL: no vsainit.bin signature, skipping!\n"); } - /* ecx gets smm, edx gets sysm */ + /* ecx gets smm, edx gets sysm. */ printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n"); real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM); - /* restart timer 1 */ + /* Restart Timer 1. */ outb(0x56, 0x43); outb(0x12, 0x41); - // check that VSA is running OK + /* Check that VSA is running OK. */ if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n"); else

1 0

r3137 build service
by coreboot information 13 Mar '08

13 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3137 to the coreboot source repository and caused the following changes: Change Log: Drop 82802ab.c as it is identical to sharplhf00l04.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3137&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3137&device=rm4100&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r641 - coreboot-v3/mainboard/emulation/qemu-x86
by svn＠coreboot.org 13 Mar '08

13 Mar '08

Author: myles Date: 2008-03-13 14:31:16 +0100 (Thu, 13 Mar 2008) New Revision: 641 Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig Log: This updates mainboard/emulation/qemu-x86/defconfig since Kconfig has changed. It's trivial. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-03-13 13:22:44 UTC (rev 640) +++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-03-13 13:31:16 UTC (rev 641) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # coreboot version: 3.0.0 -# Wed Feb 6 13:55:31 2008 +# Thu Mar 13 07:13:17 2008 # # @@ -24,15 +24,17 @@ CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1976 CONFIG_BOARD_EMULATION_QEMU_X86=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set -# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +CONFIG_COREBOOT_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set -CONFIG_COREBOOT_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set -CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_COREBOOT_ROMSIZE_KB=256 CONFIG_ARCH_X86=y CONFIG_ARCH="x86" CONFIG_CPU_I586=y CONFIG_OPTION_TABLE=y +CONFIG_CARBASE=0x8f000 +CONFIG_CARSIZE=0x1000 # # Compression @@ -65,6 +67,7 @@ # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_CONSOLE_BUFFER=y # # Devices @@ -75,6 +78,10 @@ # CONFIG_PCI_OPTION_ROM_RUN_NONE is not set # CONFIG_MULTIPLE_VGA_INIT is not set # CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set + +# +# Power management +# CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y CONFIG_SUPERIO_WINBOND_W83627HF=y @@ -83,6 +90,6 @@ # # Payload # -# CONFIG_PAYLOAD_PREPARSE_ELF is not set +# CONFIG_PAYLOAD_ELF_LOADER is not set # CONFIG_PAYLOAD_ELF is not set CONFIG_PAYLOAD_NONE=y

1 0

LAR TODO
by Carl-Daniel Hailfinger 13 Mar '08

13 Mar '08

I'd like to use this thread to collect TODO items for LAR. My current list is rather short, but that does not mean it is easy to complete these tasks. - "Unparse" parsed ELF so you get an ELF back when unpacking a LAR containing parsed ELF file. Reason: See mails on the list for the last few days. - "List holes" mode. Reason: To be able to "zerofill" the LAR, we must know where to fill. - Ability to specify where files should end up in the LAR (beginning of free space, end of free space, fixed address). Reason: Some machines can only access part of the flash directly, so shadowing/copying is needed for the inaccessible parts. That can only be done after RAM init, thereby requiring normal/initram and fallback/initram to end up in the directly accessible window. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 26

r640 - in coreboot-v3: . arch/x86
by svn＠coreboot.org 13 Mar '08

13 Mar '08

Author: myles Date: 2008-03-13 14:22:44 +0100 (Thu, 13 Mar 2008) New Revision: 640 Modified: coreboot-v3/Kconfig coreboot-v3/arch/x86/Makefile coreboot-v3/arch/x86/stage1.c Log: This patch is a hopefully less controversial version of a previous patch which removed the ELF loader from coreboot v3. This adds a Kconfig option PAYLOAD_ELF_LOADER which builds the loader into v3. In order to make it a little safer, I changed PAYLOAD_PREPARSE_ELF to PAYLOAD_NO_PREPARSE_ELF and made that option depend on PAYLOAD_ELF_LOADER so that no one adds an unparsed ELF without the loader. One part that was strange to me was that I first tried adding elfboot.o and archelfboot.o to the beginning of the list of object files. I added them to the end of the list instead. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-03-13 03:02:33 UTC (rev 639) +++ coreboot-v3/Kconfig 2008-03-13 13:22:44 UTC (rev 640) @@ -92,6 +92,12 @@ menu "Payload" +config PAYLOAD_ELF_LOADER + bool "Include ELF payload loader" + default n + help + This option allows an unparsed ELF paylaod to be added and loaded. + choice prompt "Payload type" default PAYLOAD_NONE @@ -125,10 +131,10 @@ help The path and filename of the ELF executable file to use as payload. -config PAYLOAD_PREPARSE_ELF - bool "Pre-parse ELF file and convert ELF segments to LAR entries" - depends PAYLOAD_ELF - default y +config PAYLOAD_NO_PREPARSE_ELF + bool "Add ELF without parsing and converting to LAR entries" + depends PAYLOAD_ELF && PAYLOAD_ELF_LOADER + default n help Until now, coreboot has used ELF for the payload. There are many problems with this, not least being the inefficiency -- the ELF has @@ -142,7 +148,7 @@ flashed the FLASH and rebooted the machine. Boot time is really not the time you want to find out your ELF payload is broken. - With this option, coreboot will direct lar to break each ELF + Without this option, coreboot will direct lar to break each ELF segment into a LAR entry. ELF will not be used at all. Note that (for now) coreboot is not backward compatible -- if you put an ELF payload in, coreboot can not parse it. We hope to remove ELF Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-03-13 03:02:33 UTC (rev 639) +++ coreboot-v3/arch/x86/Makefile 2008-03-13 13:22:44 UTC (rev 640) @@ -105,11 +105,17 @@ # initram module and the various stages and payload files. # -STAGE0_LIB_OBJ = uart8250.o mem.o elfboot.o lar.o delay.o vtxprintf.o \ + +STAGE0_LIB_OBJ = uart8250.o mem.o lar.o delay.o vtxprintf.o \ vsprintf.o console.o string.o $(DECOMPRESSORS) -STAGE0_ARCH_X86_OBJ = stage1.o serial.o archelfboot.o speaker.o \ +STAGE0_ARCH_X86_OBJ = stage1.o serial.o speaker.o \ udelay_io.o mc146818rtc.o post_code.o +ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y) +STAGE0_LIB_OBJ += elfboot.o +STAGE0_ARCH_X86_OBJ += archelfboot.o +endif + ifeq ($(CONFIG_CPU_I586),y) STAGE0_CAR_OBJ = stage0_i586.o else @@ -122,10 +128,10 @@ endif endif -ifeq ($(CONFIG_PAYLOAD_PREPARSE_ELF), y) +ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y) + PARSEELF = +else PARSEELF = -e -else - PARSEELF = endif STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \ Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-03-13 03:02:33 UTC (rev 639) +++ coreboot-v3/arch/x86/stage1.c 2008-03-13 13:22:44 UTC (rev 640) @@ -28,10 +28,12 @@ #include <mc146818rtc.h> #include <cpu.h> +#ifdef CONFIG_PAYLOAD_ELF_LOADER /* ah, well, what a mess! This is a hard code. FIX ME but how? * By getting rid of ELF ... */ #define UNCOMPRESS_AREA (0x400000) +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ /* these prototypes should go into headers */ void uart_init(void); @@ -86,6 +88,8 @@ return; } + +#ifdef CONFIG_PAYLOAD_ELF_LOADER /* until we get rid of elf */ int legacy(struct mem_file *archive, char *name, void *where, struct lb_memory *mem) { @@ -101,6 +105,7 @@ printk(BIOS_ERR, "elfboot_mem returns %d\n", ret); return -1; } +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ /* * This function is called from assembler code with its argument on the @@ -110,7 +115,9 @@ { int ret; struct mem_file archive, result; +#ifdef CONFIG_PAYLOAD_ELF_LOADER int elfboot_mem(struct lb_memory *mem, void *where, int size); +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ void *entry; /* we can't statically init this hack. */ @@ -202,9 +209,11 @@ printk(BIOS_DEBUG, "Stage2 code done.\n"); +#ifdef CONFIG_PAYLOAD_ELF_LOADER ret = find_file(&archive, "normal/payload", &result); if (! ret) legacy(&archive, "normal/payload", (void *)UNCOMPRESS_AREA, mem); +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ entry = load_file_segments(&archive, "normal/payload"); if (entry != (void*)-1) {

1 0

booting xen from coreboot
by Mikhail Savchenko 13 Mar '08

13 Mar '08

Trying to boot xen from coreboot, using filo as payloader and mbootpack for getting bzImage with xen and xenolinux, but always getting error, that my loader not multiboot. Also, trying to use grub as payloader, but cann't understand how setup it right. Can anybody assist with solution of booting xen with coreboot?

2 1

r3137 - trunk/util/flashrom
by svn＠coreboot.org 13 Mar '08

13 Mar '08

Author: hailfinger Date: 2008-03-13 13:43:31 +0100 (Thu, 13 Mar 2008) New Revision: 3137 Removed: trunk/util/flashrom/82802ab.c Modified: trunk/util/flashrom/Makefile trunk/util/flashrom/flashchips.c trunk/util/flashrom/sharplhf00l04.c Log: Drop 82802ab.c as it is identical to sharplhf00l04.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Deleted: trunk/util/flashrom/82802ab.c =================================================================== --- trunk/util/flashrom/82802ab.c 2008-03-13 02:21:41 UTC (rev 3136) +++ trunk/util/flashrom/82802ab.c 2008-03-13 12:43:31 UTC (rev 3137) @@ -1,186 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2000 Silicon Integrated System Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Datasheet: - * - Name: Intel 82802AB/82802AC Firmware Hub (FWH) - * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm - * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf - * - Order number: 290658-004 - */ - -#include <stdio.h> -#include <stdint.h> -#include "flash.h" - -// I need that Berkeley bit-map printer -void print_82802ab_status(uint8_t status) -{ - printf("%s", status & 0x80 ? "Ready:" : "Busy:"); - printf("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:"); - printf("%s", status & 0x20 ? "BE ERROR:" : "BE OK:"); - printf("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:"); - printf("%s", status & 0x8 ? "VP ERR:" : "VPP OK:"); - printf("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:"); - printf("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:"); -} - -int probe_82802ab(struct flashchip *flash) -{ - volatile uint8_t *bios = flash->virtual_memory; - uint8_t id1, id2; - -#if 0 - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0x90; -#endif - - *bios = 0xff; - myusec_delay(10); - *bios = 0x90; - myusec_delay(10); - - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); - - /* Leave ID mode */ - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; - - myusec_delay(10); - - printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2); - - if (id1 != flash->manufacture_id || id2 != flash->model_id) - return 0; - - map_flash_registers(flash); - - return 1; -} - -uint8_t wait_82802ab(volatile uint8_t *bios) -{ - uint8_t status; - uint8_t id1, id2; - - *bios = 0x70; - if ((*bios & 0x80) == 0) { // it's busy - while ((*bios & 0x80) == 0) ; - } - - status = *bios; - - // put another command to get out of status register mode - - *bios = 0x90; - myusec_delay(10); - - id1 = *(volatile uint8_t *)bios; - id2 = *(volatile uint8_t *)(bios + 0x01); - - // this is needed to jam it out of "read id" mode - *(volatile uint8_t *)(bios + 0x5555) = 0xAA; - *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; - *(volatile uint8_t *)(bios + 0x5555) = 0xF0; - - return status; -} - -int erase_82802ab_block(struct flashchip *flash, int offset) -{ - volatile uint8_t *bios = flash->virtual_memory + offset; - volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; - uint8_t status; - - // clear status register - *bios = 0x50; - //printf("Erase at %p\n", bios); - // clear write protect - //printf("write protect is at %p\n", (wrprotect)); - //printf("write protect is 0x%x\n", *(wrprotect)); - *(wrprotect) = 0; - //printf("write protect is 0x%x\n", *(wrprotect)); - - // now start it - *(volatile uint8_t *)(bios) = 0x20; - *(volatile uint8_t *)(bios) = 0xd0; - myusec_delay(10); - // now let's see what the register is - status = wait_82802ab(flash->virtual_memory); - //print_82802ab_status(status); - printf("DONE BLOCK 0x%x\n", offset); - - return 0; -} - -int erase_82802ab(struct flashchip *flash) -{ - int i; - unsigned int total_size = flash->total_size * 1024; - - printf("total_size is %d; flash->page_size is %d\n", - total_size, flash->page_size); - for (i = 0; i < total_size; i += flash->page_size) - erase_82802ab_block(flash, i); - printf("DONE ERASE\n"); - - return 0; -} - -void write_page_82802ab(volatile uint8_t *bios, uint8_t *src, - volatile uint8_t *dst, int page_size) -{ - int i; - - for (i = 0; i < page_size; i++) { - /* transfer data from source to destination */ - *dst = 0x40; - *dst++ = *src++; - wait_82802ab(bios); - } -} - -int write_82802ab(struct flashchip *flash, uint8_t *buf) -{ - int i; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; - volatile uint8_t *bios = flash->virtual_memory; - - erase_82802ab(flash); - if (*bios != 0xff) { - printf("ERASE FAILED\n"); - return -1; - } - printf("Programming page: "); - for (i = 0; i < total_size / page_size; i++) { - printf("%04d at address: 0x%08x", i, i * page_size); - write_page_82802ab(bios, buf + i * page_size, - bios + i * page_size, page_size); - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - } - printf("\n"); - protect_jedec(bios); - - return 0; -} Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-03-13 02:21:41 UTC (rev 3136) +++ trunk/util/flashrom/Makefile 2008-03-13 12:43:31 UTC (rev 3137) @@ -22,7 +22,7 @@ OBJS = chipset_enable.o board_enable.o udelay.o jedec.o sst28sf040.o \ am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \ - 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \ + msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \ sst_fwhub.o layout.o cbtable.o flashchips.o flashrom.o \ sharplhf00l04.o w29ee011.o spi.o Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-03-13 02:21:41 UTC (rev 3136) +++ trunk/util/flashrom/flashchips.c 2008-03-13 12:43:31 UTC (rev 3137) @@ -192,10 +192,10 @@ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P128", ST_ID, ST_M25P128, 16384, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, - {"82802ab", 137, 173, 512, 64 * 1024, - probe_82802ab, erase_82802ab, write_82802ab}, - {"82802ac", 137, 172, 1024, 64 * 1024, - probe_82802ab, erase_82802ab, write_82802ab}, + {"82802ab", INTEL_ID, 173, 512, 64 * 1024, + probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, + {"82802ac", INTEL_ID, 172, 1024, 64 * 1024, + probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, {"F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, probe_jedec, erase_chip_jedec, write_49f002}, #ifndef DISABLE_DOC Modified: trunk/util/flashrom/sharplhf00l04.c =================================================================== --- trunk/util/flashrom/sharplhf00l04.c 2008-03-13 02:21:41 UTC (rev 3136) +++ trunk/util/flashrom/sharplhf00l04.c 2008-03-13 12:43:31 UTC (rev 3137) @@ -18,6 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * Datasheet: + * - Name: Intel 82802AB/82802AC Firmware Hub (FWH) + * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm + * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf + * - Order number: 290658-004 + */ + #include <stdio.h> #include <stdlib.h> #include "flash.h"

1 0

flashrom and PM49FL004/2
by Nikolay Petukhov 13 Mar '08

13 Mar '08

Hi, all. I have PCISA-LX-800 board (AMD LX800 + CS5536) http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX. The flashrom detect flash device on this board, hier flashrom output: ... Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). ... But the flashrom has problems with write and erasing operations to this flash device. The data-sheet on PM49FL004/2 say that: This flash device can work in two modes: LPC and FWH. On this board flash device be in FWH mode (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d) Also data-sheet on PM49FL004/2 say that: In FWH mode are available Block Locking Registers and in default flash is locked for write/erasing. This patch add unlocking operation PM49FL004/2 before write/erasing operation. Signed-off-by: Nikolay Petukhov <nikolay.petukhov at gmail.com> -- Nikolay

2 1

FILO: read time of LPC flash
by Nikolay Petukhov 13 Mar '08

13 Mar '08

Hi, all. Here is simple measure time of reading memory device. #include <stdio.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <fcntl.h> #include <sys/mman.h> #include <sys/time.h> int main(int argc, char *argv[]) { int fd_mem; volatile char *pchar; volatile int *pint; char *buffer; int *buffer_int; struct timeval t1, t2; long time_transfer; int i; int size; if (argc != 2) { fprintf(stderr, "Usage: %s size Kb\n", argv[0]); return 0; } size = atoi (argv[1]); if (!size || size > 2048) size = 512; size *= 1024; if (getuid()) { fprintf(stderr, "Run me as root, I need access to /dev/mem.\n"); } fd_mem = open("/dev/mem", O_RDWR); if (fd_mem < 0) { perror("Could not open /dev/mem:"); exit(1); } pchar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t) (0xFFFFFFFF - size + 1)); if (pchar == MAP_FAILED) { perror("Can't mmap registers using /dev/mem"); exit(1); } buffer = (char *)malloc (size); gettimeofday(&t1, NULL); memcpy (buffer, pchar, size); gettimeofday(&t2, NULL); time_transfer = (t2.tv_sec - t1.tv_sec)*1000 + (t2.tv_usec - t1.tv_usec)/1000; printf ("memcpy time_transfer %d KB for %ld ms\n", size, time_transfer); gettimeofday(&t1, NULL); for (i = 0; i < size; i++) buffer[i] = pchar[i]; gettimeofday(&t2, NULL); time_transfer = (t2.tv_sec - t1.tv_sec)*1000 + (t2.tv_usec - t1.tv_usec)/1000; printf ("char time_transfer %d KB for %ld ms\n", size, time_transfer); pint = (int *)pchar; buffer_int = (int *)buffer; gettimeofday(&t1, NULL); for (i = 0; i < size/4; i++) { buffer_int[i] = pint[i]; } gettimeofday(&t2, NULL); time_transfer = (t2.tv_sec - t1.tv_sec)*1000 + (t2.tv_usec - t1.tv_usec)/1000; printf ("int time_transfer %d KB for %ld ms\n", size, time_transfer); free (buffer); close(fd_mem); return 0; } Result of tests: 1. Board iei/pcisa-lx-800 (AMD LX800 + CS5536), flash sst49lf016c (2048 KB). ./testmem 2048 memcpy time_transfer 2097152 KB for 3478 ms char time_transfer 2097152 KB for 3592 ms int time_transfer 2097152 KB for 2086 ms ./testmem 1024 memcpy time_transfer 1048576 KB for 1740 ms char time_transfer 1048576 KB for 1795 ms int time_transfer 1048576 KB for 1041 ms ./testmem 512 memcpy time_transfer 524288 KB for 873 ms char time_transfer 524288 KB for 898 ms int time_transfer 524288 KB for 521 ms 2. Board iei/pcisa-lx-800(AMD LX800 + CS5536)), flash pm49fl004 (512 KB). ./testmem 512 memcpy time_transfer 524288 KB for 868 ms char time_transfer 524288 KB for 897 ms int time_transfer 524288 KB for 524 ms Conclusion: For large amounts of speed reading memory flash limited to memcpy () function. The FILO also use memcpy() for reading memory flash. This patch add macro READ_OVER_MEMCPY in FILO Config and some code to blockdev.c. With this patch loading time of kernel and initrd (1.9MB) redused by 1.5sec. diff -Nru filo-0.5/defconfig filo-0.5-memcpy/defconfig --- filo-0.5/defconfig 2008-01-16 19:19:17.000000000 +0500 +++ filo-0.5-memcpy/defconfig 2008-03-13 13:03:14.000000000 +0500 @@ -93,3 +93,6 @@ #DEBUG_USB = 1 #DEBUG_ELTORITO = 1 +#Read flash memory +#READ_OVER_MEMCPY=1 + diff -Nru filo-0.5/fs/blockdev.c filo-0.5-memcpy/fs/blockdev.c --- filo-0.5/fs/blockdev.c 2006-04-29 04:53:26.000000000 +0600 +++ filo-0.5-memcpy/fs/blockdev.c 2008-03-13 13:03:08.000000000 +0500 @@ -361,7 +361,21 @@ len = 512 - byte_offset; if (len > byte_len) len = byte_len; - memcpy(dest, sector_buffer + byte_offset, len); + +#ifdef READ_OVER_MEMCPY + if (dev_type == DISK_MEM) { + + int * src_int = (int *)(sector_buffer + byte_offset); + int * dest_int = (int *)dest; + int i; + + for (i = 0; i < len/4; i++) + dest_int[i] = src_int[i]; + } + else +#endif + memcpy(dest, sector_buffer + byte_offset, len); + sector++; byte_offset = 0; byte_len -= len; -- Nikolay

2 1

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coreboot March 2008