coreboot March 2008

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[PATCH 2/5] Intel 3100, version 3: SuperIO and UART support
by Ed Swierk 14 Mar '08

14 Mar '08

This patch implements support for the Intel 3100 integrated SuperIO and UART. --Ed

3 4

r3144 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3144 to the coreboot source repository and caused the following changes: Change Log: Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Ward says: This code detects the ICH8 chipset on my laptop, and it appears to use SPI. Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3144&device=serengeti_chee… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] flashrom: Prepare for ICH7/ICH8 SPI support
by Carl-Daniel Hailfinger 14 Mar '08

14 Mar '08

Testers wanted for all ICH versions! Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich7/chipset_enable.c =================================================================== --- flashrom-ich7/chipset_enable.c (Revision 3143) +++ flashrom-ich7/chipset_enable.c (Arbeitskopie) @@ -139,8 +139,8 @@ } /* - * See ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf + * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" + * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +153,10 @@ */ old = pci_read_byte(dev, bios_cntl); + printf("BIOS Lock Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS Write Enable: %sabled, ", (old & (1 << 1)) ? "en" : "dis"); + printf("BIOS_CNTL is 0x%x\n", old); + new = old | 1; if (new == old) @@ -178,6 +182,37 @@ return enable_flash_ich(dev, name, 0xdc); } +static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +{ + uint8_t old, new; + uint32_t tmp; + + /* Root Complex Base Address Register (RCBA) */ + tmp = pci_read_long(dev, 0xf0); + tmp &= 0xffffc000; + printf("Root Complex Base Address Register = 0x%x\n", tmp); + printf("GCS address = 0x%x\n", tmp + 0x3410); + /* TODO: Read the GCS */ + printf("SPIBAR = 0x%x\n", tmp + 0x3020); + /* TODO: Dump the SPI config regs */ + + old = pci_read_byte(dev, 0xdc); + printf("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + printf("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + break; + default: + printf("invalid prefetching/caching settings, "); + break; + } + return enable_flash_ich_dc(dev, name); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -524,13 +559,13 @@ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, -- http://www.hailfinger.org/

3 10

r3144 - trunk/util/flashrom
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: hailfinger Date: 2008-03-14 18:20:59 +0100 (Fri, 14 Mar 2008) New Revision: 3144 Modified: trunk/util/flashrom/chipset_enable.c Log: Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets. Functionality (except printing) should be unchanged. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Ward says: This code detects the ICH8 chipset on my laptop, and it appears to use SPI. Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-03-14 06:12:24 UTC (rev 3143) +++ trunk/util/flashrom/chipset_enable.c 2008-03-14 17:20:59 UTC (rev 3144) @@ -30,6 +30,7 @@ #include <stdlib.h> #include <sys/types.h> #include <sys/stat.h> +#include <sys/mman.h> #include <fcntl.h> #include <unistd.h> #include "flash.h" @@ -139,8 +140,8 @@ } /* - * See ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf + * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" + * http://download.intel.com/design/chipsets/datashts/30701303.pdf */ static int enable_flash_ich(struct pci_dev *dev, const char *name, int bios_cntl) @@ -153,6 +154,12 @@ */ old = pci_read_byte(dev, bios_cntl); + printf_debug("BIOS Lock Enable: %sabled, ", + (old & (1 << 1)) ? "en" : "dis"); + printf_debug("BIOS Write Enable: %sabled, ", + (old & (1 << 0)) ? "en" : "dis"); + printf_debug("BIOS_CNTL is 0x%x\n", old); + new = old | 1; if (new == old) @@ -178,6 +185,50 @@ return enable_flash_ich(dev, name, 0xdc); } +static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name) +{ + uint8_t old, new, bbs; + uint32_t tmp, gcs; + void *rcba; + + /* Root Complex Base Address Register (RCBA) */ + tmp = pci_read_long(dev, 0xf0); + tmp &= 0xffffc000; + printf_debug("Root Complex Base Address Register = 0x%x\n", tmp); + rcba = mmap(0, 0x3510, PROT_READ, MAP_SHARED, fd_mem, (off_t)tmp); + if (rcba == MAP_FAILED) { + perror("Can't mmap memory using " MEM_DEV); + exit(1); + } + printf_debug("GCS address = 0x%x\n", tmp + 0x3410); + gcs = *(volatile uint32_t *)(rcba + 0x3410); + printf_debug("GCS = 0x%x: ", gcs); + printf_debug("BIOS Interface Lock-Down: %sabled, ", + (gcs & 0x1) ? "en" : "dis"); + bbs = (gcs >> 10) & 0x3; + printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, + (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); + printf_debug("SPIBAR = 0x%x\n", tmp + 0x3020); + /* TODO: Dump the SPI config regs */ + munmap(rcba, 0x3510); + + old = pci_read_byte(dev, 0xdc); + printf_debug("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + printf_debug("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + break; + default: + printf_debug("invalid prefetching/caching settings, "); + break; + } + return enable_flash_ich_dc(dev, name); +} + static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -524,13 +575,15 @@ {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc}, + {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc_spi}, + {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc_spi}, + {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc_spi}, + {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc_spi}, + {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc_spi}, + {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich_dc_spi}, + {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc_spi}, + {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc_spi}, + {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich_dc_spi}, {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},

1 0

flashrom issues??
by joe＠smittys.pointclark.net 14 Mar '08

14 Mar '08

Hello, I am having issues with flashrom. It can read the bios ok and even verify it but when I try to write it I get this: [root@localhost util]# flashrom -w test Calibrating delay loop... OK. Found coreboot table at 0x00000530. Vendor ID: rca, part ID: rm4100 Found chipset "ICH4/ICH4-L", enabling flash write... OK. NOT FOUND rca:rm4100 M50FW080 found at physical address 0xfff00000. Flash part is M50FW080 (1024 KB). ERASE FAILED @0, val 92! After this I tried the -E option (worked good) to erase it and than tried again with no luck, same message, any ideas?? Thanks - Joe

6 48

r3143 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3143 to the coreboot source repository and caused the following changes: Change Log: Add a Config-abuild.lb for the rca/rm4100 (trivial) The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3143&device=serengeti_chee… Compilation of rca:rm4100 has been fixed If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3138 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3138 to the coreboot source repository and caused the following changes: Change Log: Also print the required -m option in --list-supported output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3138&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3138&device=rm4100&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

4 5

r3143 - trunk/coreboot-v2/targets/rca/rm4100
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: cozzie Date: 2008-03-14 07:12:24 +0100 (Fri, 14 Mar 2008) New Revision: 3143 Added: trunk/coreboot-v2/targets/rca/rm4100/Config-abuild.lb Log: Add a Config-abuild.lb for the rca/rm4100 (trivial) The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Added: trunk/coreboot-v2/targets/rca/rm4100/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/rca/rm4100/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/rca/rm4100/Config-abuild.lb 2008-03-14 06:12:24 UTC (rev 3143) @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target rca_rm4100 +mainboard rca/rm4100 + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + payload __PAYLOAD__ +end + +buildrom ./coreboot.rom ROM_SIZE "fallback" +

1 0

r3142 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3142 to the coreboot source repository and caused the following changes: Change Log: Fix broken flashrom build. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3142&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3142&device=rm4100&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3141 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3141 to the coreboot source repository and caused the following changes: Change Log: Fix up one forgotten revert in r3140. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3141&device=serengeti_chee… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3141&device=rm4100&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot March 2008