coreboot March 2008

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382 discussions

r3147 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3147 to the coreboot source repository and caused the following changes: Change Log: Following patch fixes the retrain/reset sequence which caused problem with some nVidia cards. The enable link should be enough, retrain is done there. Tested on my system. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3147&device=serengeti_chee… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3146 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3146 to the coreboot source repository and caused the following changes: Change Log: Re-add code erroneously removed in r3140. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3146&device=serengeti_chee… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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next few weeks
by ron minnich 14 Mar '08

14 Mar '08

I am on travel/vacation/whatever until the denver meeting in april. Hence, until that time, my efforts are going to be organizational and writing talks etc., with pretty much zero code. So, sorry, I'm now useless for a few weeks. I think the burning issue is the LX interrupt situation, also picking a common motherboard for k8. Just wanted to let people know why I would not be doing commits for a good long while :-) But I will sure be watching what good code you all are writing! See you in Denver, I'm looking forward to it. thanks ron

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[PATCH] v3: AMD DB800 support
by Carl-Daniel Hailfinger 14 Mar '08

14 Mar '08

This is another milestone in my quest to obsolete v2. [Patch looks strange due to a svn bug. Please let me commit, my tree will give us proper svn blame history and actually commit correctly.] Compile tested. Untested on hardware, but it should work. Marc, can you please test on real hardware? AMD DB800 support, ported from v2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig 2008-03-04 03:07:01.000000000 +0100 @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the default mainboard name. + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + # TODO: Fix PCI ID. + default 0x1022 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem vendor ID. + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + # TODO: Fix PCI ID. + default 0x2323 + depends BOARD_AMD_DB800 + help + Mainboard specific PCI subsystem device ID. + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c 2008-03-04 04:02:32.000000000 +0100 @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <northbridge/amd/geodelx/raminit.h> + +/* #include <device/smbus.h> + * TODO: figure out how smbus functions should be done. See smbus_ops.c + */ +extern int smbus_read_byte(u16 device, u8 address); + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +u8 spd_read_byte(u16 device, u8 address) +{ + u8 spdbyte; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + spdbyte = smbus_read_byte(device, address); + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbyte); + + return spdbyte; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the AMD DB800 development platform. + * It might seem that you could somehow do these functions in, e.g., the cpu + * code, but the order of operations and what those operations are is VERY + * strongly mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from initram (stage1) main!\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/stage1.c 2008-03-04 03:05:09.000000000 +0100 @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <amd_geodelx.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts 2008-03-04 04:01:49.000000000 +0100 @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; + }; + ioport@46 { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + }; + }; +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h 2008-03-04 04:02:08.000000000 +0100 @@ -0,0 +1,81 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include <pirq_routing.h> + +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * AMD DB800 interrupt wiring. + * + * Devices are: + * + * FIXME + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + + /* On-board ethernet */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, + } +}; --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/cmos.layout 2008-03-04 03:08:52.000000000 +0100 @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + --- /dev/null 2007-09-21 23:50:58.000000000 +0200 +++ LinuxBIOSv3-db800/mainboard/amd/db800/Makefile 2008-03-04 03:18:53.000000000 +0100 @@ -0,0 +1,34 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: LinuxBIOSv3-db800/mainboard/amd/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/Kconfig (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/Kconfig (Arbeitskopie) @@ -23,6 +23,18 @@ prompt "Mainboard model" depends on VENDOR_AMD +config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + help + AMD DB800 Geode LX development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86 @@ -36,5 +48,6 @@ endchoice +source "mainboard/amd/db800/Kconfig" source "mainboard/amd/norwich/Kconfig" Index: LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/amd/norwich/irq_tables.h (Arbeitskopie) @@ -17,17 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <lib.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> -#include <string.h> -#include <msr.h> -#include <io.h> #include <pirq_routing.h> -#include <amd_geodelx.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" /* Number of slots and devices in the PIR table */ #define SLOT_COUNT 6 @@ -83,13 +73,19 @@ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0x00, /* Checksum */ { - /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + /* chipset */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* slot1 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, + /* slot2 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, + /* slot3 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, + /* slot4 */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/Kconfig (Arbeitskopie) @@ -21,8 +21,8 @@ config MAINBOARD_NAME string - default amd/norwich - depends BOARD_AMD_NORWICH + default amd/db800 + depends BOARD_AMD_DB800 help This is the default mainboard name. @@ -30,7 +30,7 @@ hex # TODO: Fix PCI ID. default 0x1022 - depends BOARD_AMD_NORWICH + depends BOARD_AMD_DB800 help Mainboard specific PCI subsystem vendor ID. @@ -38,7 +38,7 @@ hex # TODO: Fix PCI ID. default 0x2323 - depends BOARD_AMD_NORWICH + depends BOARD_AMD_DB800 help Mainboard specific PCI subsystem device ID. Index: LinuxBIOSv3-db800/mainboard/amd/db800/initram.c =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/initram.c (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/initram.c (Arbeitskopie) @@ -67,7 +67,7 @@ } /** - * main for initram for the AMD Norwich development platform. + * main for initram for the AMD DB800 development platform. * It might seem that you could somehow do these functions in, e.g., the cpu * code, but the order of operations and what those operations are is VERY * strongly mainboard dependent. It's best to leave it in the mainboard code. Index: LinuxBIOSv3-db800/mainboard/amd/db800/dts =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/dts (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/dts (Arbeitskopie) @@ -19,8 +19,8 @@ */ /{ - mainboard-vendor = "PC Engines"; - mainboard-name = "ALIX1.C"; + mainboard-vendor = "AMD"; + mainboard-name = "DB800"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); @@ -45,6 +45,7 @@ /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. * See virtual PIC spec. */ enable_gpio_int_route = "0x0D0C0700"; + enable_USBP4_device = "1"; }; ioport@46 { /config/("superio/winbond/w83627hf/dts"); Index: LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h (Revision 0) +++ LinuxBIOSv3-db800/mainboard/amd/db800/irq_tables.h (Arbeitskopie) @@ -19,12 +19,14 @@ #include <pirq_routing.h> +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 4 /* Platform IRQs */ -#define PIRQA 11 -#define PIRQB 10 -#define PIRQC 11 -#define PIRQD 9 +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 /* Map */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ @@ -39,39 +41,18 @@ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ /* - * ALIX1.C interrupt wiring. + * AMD DB800 interrupt wiring. * * Devices are: * - * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31) - * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block - * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) - * 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01) - * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) - * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) - * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) - * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) - * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) + * FIXME * - * The only devices that interrupt are: - * - * What Device IRQ PIN PIN WIRED TO - * ------------------------------------------------- - * AES 00:01.2 0a 01 A A - * 3VPCI 00:0c.0 0a 01 A A - * eth0 00:0d.0 0b 01 A B - * mpci 00:0e.0 0a 01 A A - * usb 00:0f.3 0b 02 B B - * usb 00:0f.4 0b 04 D D - * usb 00:0f.5 0b 04 D D - * - * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. */ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ @@ -88,16 +69,13 @@ /* CPU */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, - /* PCI (slot 1) */ - {0x00, (0x0C << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x4, 0x0}, + /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* On-board ethernet */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, - /* Mini PCI (slot 2) */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, - - /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */ - {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + /* PCI (slot 1) */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, } }; Index: LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h =================================================================== --- LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Revision 630) +++ LinuxBIOSv3-db800/mainboard/pcengines/alix1c/irq_tables.h (Arbeitskopie) @@ -19,6 +19,8 @@ #include <pirq_routing.h> +/* Number of slots and devices in the PIR table */ +#define SLOT_COUNT 5 /* Platform IRQs */ #define PIRQA 11 @@ -71,7 +73,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, PIRQ_VERSION, - 32 + 16 * 5, /* Max. number of devices on the bus */ + 32 + 16 * SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ -- http://www.hailfinger.org/

3 16

r3145 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "linux_junkie" checked in revision 3145 to the coreboot source repository and caused the following changes: Change Log: Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3145&device=serengeti_chee… If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3148 - in trunk/coreboot-v2/src: mainboard/asus/a8v-e_se southbridge/via/vt8237r
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: ruik Date: 2008-03-15 01:26:50 +0100 (Sat, 15 Mar 2008) New Revision: 3148 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Log: Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2008-03-15 00:19:34 UTC (rev 3147) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2008-03-15 00:26:50 UTC (rev 3148) @@ -192,6 +192,7 @@ w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + enable_rom_decode(); print_info("now booting... fallback\r\n"); @@ -259,6 +260,7 @@ w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + enable_rom_decode(); print_info("now booting... real_main\r\n"); Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2008-03-15 00:19:34 UTC (rev 3147) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2008-03-15 00:26:50 UTC (rev 3148) @@ -212,3 +212,18 @@ else PRINT_DEBUG("Done\r\n"); } + +void enable_rom_decode(void) +{ + device_t dev; + + /* Bus Control and Power Management */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("SB not found\r\n"); + + /* ROM decode last 1MB FFC00000 - FFFFFFFF */ + pci_write_config8(dev, 0x41, 0x7f); +}

1 0

[PATCH] pcie fixes K8T890
by Rudolf Marek 14 Mar '08

14 Mar '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Following patch fixes the retrain/reset sequence which caused problem with some nVidia cards. The enable link should be enough, retrain is done there. Tested on my system. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFH2FsG3J9wPJqZRNURAiD9AJ93M+aNPAtg9ur/+gDVE7jVaZULxACeLV2v xiSvzd4KRws1+D+0RdyGyaE= =4ZV6 -----END PGP SIGNATURE-----

3 3

r3147 - trunk/coreboot-v2/src/southbridge/via/k8t890
by svn＠coreboot.org 14 Mar '08

14 Mar '08

Author: ruik Date: 2008-03-15 01:19:34 +0100 (Sat, 15 Mar 2008) New Revision: 3147 Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c Log: Following patch fixes the retrain/reset sequence which caused problem with some nVidia cards. The enable link should be enough, retrain is done there. Tested on my system. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c 2008-03-14 23:55:58 UTC (rev 3146) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_pcie.c 2008-03-15 00:19:34 UTC (rev 3147) @@ -41,8 +41,6 @@ * pci_write_config8(dev, 0xe2, 0x0); * pci_write_config8(dev, 0xe3, 0x92); */ - /* Disable scrambling bit 6 to 1. */ - pci_write_config8(dev, 0xc0, 0x43); /* Set replay timer limit. */ pci_write_config8(dev, 0xb1, 0xf0); @@ -62,18 +60,6 @@ reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg & ~0x10); - /* Retrain link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x20); - - reg = pci_read_config8(dev, 0x3e); - reg |= 0x40; /* Bus reset. */ - pci_write_config8(dev, 0x3e, reg); - - reg = pci_read_config8(dev, 0x3e); - reg &= ~0x40; /* Clear reset. */ - pci_write_config8(dev, 0x3e, reg); - dump_south(dev); } @@ -97,18 +83,6 @@ reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg & ~0x10); - /* Retrain. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x20); - - reg = pci_read_config8(dev, 0x3e); - reg |= 0x40; /* Bus reset. */ - pci_write_config8(dev, 0x3e, reg); - - reg = pci_read_config8(dev, 0x3e); - reg &= ~0x40; /* Clear reset. */ - pci_write_config8(dev, 0x3e, reg); - dump_south(dev); }

1 0

Re: [coreboot] r3146 - trunk/util/flashrom
by joe＠smittys.pointclark.net 14 Mar '08

14 Mar '08

Quoting svn(a)coreboot.org: > Author: uwe > Date: 2008-03-15 00:55:58 +0100 (Sat, 15 Mar 2008) > New Revision: 3146 > > Modified: > trunk/util/flashrom/flash.h > trunk/util/flashrom/flashchips.c > trunk/util/flashrom/flashrom.c > Log: > Re-add code erroneously removed in r3140. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > I like how you formatted flashchips.c nice work Uwe. Thanks - Joe

1 0

Re: [coreboot] r3146 - trunk/util/flashrom
by Carl-Daniel Hailfinger 14 Mar '08

14 Mar '08

Hi Uwe, who acked the original change? I fear the new formatting is too wide even for my full-screen xterm and it will certainly become worse once we add a "supported" flag. I would have NACKed the patch, but I didn't see it on the list (probably because my spam filter acts up lately). Can we revert this? Regards, Carl-Daniel On 15.03.2008 00:55, svn(a)coreboot.org wrote: > Author: uwe > Date: 2008-03-15 00:55:58 +0100 (Sat, 15 Mar 2008) > New Revision: 3146 > > Modified: > trunk/util/flashrom/flash.h > trunk/util/flashrom/flashchips.c > trunk/util/flashrom/flashrom.c > Log: > Re-add code erroneously removed in r3140. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > > > Modified: trunk/util/flashrom/flashchips.c > =================================================================== > --- trunk/util/flashrom/flashchips.c 2008-03-14 23:32:03 UTC (rev 3145) > +++ trunk/util/flashrom/flashchips.c 2008-03-14 23:55:58 UTC (rev 3146) > @@ -26,202 +26,107 @@ > #endif > > struct flashchip flashchips[] = { > - {"Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, > - probe_29f040b, erase_29f040b, write_29f040b}, > - {"Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, > - probe_29f040b, erase_29f040b, write_29f040b}, > - {"Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024, > - probe_29f040b, erase_29f040b, write_29f040b}, > - {"AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"At29C040A", ATMEL_ID, AT_29C040A, 512, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"At29C020", ATMEL_ID, AT_29C020, 256, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"At49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"At49F002(N)T",ATMEL_ID, AT_49F002NT, 256, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, > - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, > - {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, > - probe_29f002, erase_29f002, write_29f002}, > - {"MX25L4005", MX_ID, MX_25L4005, 512, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"MX25L8005", MX_ID, MX_25L8005, 1024, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"MX25L3205", MX_ID, MX_25L3205, 4096, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, > - probe_28sf040, erase_28sf040, write_28sf040}, > - {"SST39SF010A", SST_ID, SST_39SF010, 128, 4096, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"SST39SF020A", SST_ID, SST_39SF020, 256, 4096, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"SST39SF040", SST_ID, SST_39SF040, 512, 4096, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"SST39VF020", SST_ID, SST_39VF020, 256, 4096, > - probe_jedec, erase_chip_jedec, write_39sf020}, > + /******************************************************************************************************************************************************************************************************/ > + /* Vendor Chip Vendor ID Chip ID TODO TODO Probe function Erase function Write function Read function */ > + /******************************************************************************************************************************************************************************************************/ > + {"AMD", "Am29F040B", AMD_ID, AM_29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, > + {"AMD", "Am29LV040B", AMD_ID, AM_29LV040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, > + {"AMD", "Am29F016D", AMD_ID, AM_29F016D, 2048, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, > + {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Atmel", "At29C040A", ATMEL_ID, AT_29C040A, 512, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Atmel", "At29C020", ATMEL_ID, AT_29C020, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Atmel", "At49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Atmel", "At49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, > + {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, > + {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Spansion", "S25FL016A", SPANSION_ID, SPANSION_S25FL016A, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"SST", "SST25VF040B", SST_ID, SST_25VF040B, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"SST", "SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"SST", "SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, > + {"SST", "SST28SF040A", SST_ID, SST_28SF040, 512, 256, probe_28sf040, erase_28sf040, write_28sf040}, > + {"SST", "SST39SF010A", SST_ID, SST_39SF010, 128, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"SST", "SST39SF020A", SST_ID, SST_39SF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"SST", "SST39SF040", SST_ID, SST_39SF040, 512, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"SST", "SST39VF020", SST_ID, SST_39VF020, 256, 4096, probe_jedec, erase_chip_jedec, write_39sf020}, > // assume similar to 004B, ignoring data sheet > - {"SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, > - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > - > - {"SST49LF040", SST_ID, SST_49LF040, 512, 4096, > - probe_jedec, erase_49lf040, write_49lf040}, > - {"SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, > - probe_jedec, erase_49lf040, write_49lf040}, > - {"SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, > - probe_jedec, erase_49lf040, write_49lf040}, > - {"SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, > - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > - {"SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, > - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > - {"SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, > - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > - {"SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024 , > - probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > - {"SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, > - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > - {"SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024 , > - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > - {"SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024 , > - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > - {"SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024 , > - probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > - {"Pm49FL002", PMC_ID_NOPREFIX, PMC_49FL002, 256, 16 * 1024, > - probe_jedec, erase_chip_jedec, write_49fl004}, > - {"Pm49FL004", PMC_ID_NOPREFIX, PMC_49FL004, 512, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_49fl004}, > - {"Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"W29C011", WINBOND_ID, W_29C011, 128, 128, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"W29C040P", WINBOND_ID, W_29C040P, 512, 256, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"W29C020C", WINBOND_ID, W_29C020C, 256, 128, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"W29EE011", WINBOND_ID, W_29C011, 128, 128, > - probe_w29ee011,erase_chip_jedec, write_jedec}, > - {"W49F002U", WINBOND_ID, W_49F002U, 256, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"W49V002A", WINBOND_ID, W_49V002A, 256, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, > - probe_jedec, erase_chip_jedec, write_39sf020}, > - {"W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, > - probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, > - {"M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, > - probe_82802ab, erase_82802ab, write_82802ab}, > - {"M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, > - probe_jedec, erase_chip_jedec, write_jedec}, > - {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, > - probe_29f040b, erase_29f040b, write_29f040b}, > - {"M25P05-A", ST_ID, ST_M25P05A, 64, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P10-A", ST_ID, ST_M25P10A, 128, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P20", ST_ID, ST_M25P20, 256, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P40", ST_ID, ST_M25P40, 512, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P80", ST_ID, ST_M25P80, 1024, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P16", ST_ID, ST_M25P16, 2048, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P32", ST_ID, ST_M25P32, 4096, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P64", ST_ID, ST_M25P64, 8192, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"M25P128", ST_ID, ST_M25P128, 16384, 256, > - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > - {"82802ab", INTEL_ID, 173, 512, 64 * 1024, > - probe_82802ab, erase_82802ab, write_82802ab}, > - {"82802ac", INTEL_ID, 172, 1024, 64 * 1024, > - probe_82802ab, erase_82802ab, write_82802ab}, > - {"F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, > - probe_jedec, erase_chip_jedec, write_49f002}, > + {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > + {"SST", "SST49LF040", SST_ID, SST_49LF040, 512, 4096, probe_jedec, erase_49lf040, write_49lf040}, > + {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, probe_jedec, erase_49lf040, write_49lf040}, > + {"SST", "SST49LF080A", SST_ID, SST_49LF080A, 1024, 4096, probe_jedec, erase_49lf040, write_49lf040}, > + {"SST", "SST49LF002A/B", SST_ID, SST_49LF002A, 256, 16 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > + {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > + {"SST", "SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > + {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, > + {"SST", "SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > + {"SST", "SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > + {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > + {"SST", "SST49LF160C", SST_ID, SST_49LF160C, 2048, 4 * 1024, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, > + {"PMC", "Pm49FL002", PMC_ID_NOPREFIX,PMC_49FL002, 256, 16 * 1024, probe_jedec, erase_chip_jedec, write_49fl004}, > + {"PMC", "Pm49FL004", PMC_ID_NOPREFIX,PMC_49FL004, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_49fl004}, > + {"PMC", "Pm25LV512", PMC_ID, PMC_25LV512, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"PMC", "Pm25LV010", PMC_ID, PMC_25LV010, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"PMC", "Pm25LV020", PMC_ID, PMC_25LV020, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"PMC", "Pm25LV040", PMC_ID, PMC_25LV040, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"PMC", "Pm25LV080B", PMC_ID, PMC_25LV080B, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"PMC", "Pm25LV016B", PMC_ID, PMC_25LV016B, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Winbond", "W29C011", WINBOND_ID, W_29C011, 128, 128, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Winbond", "W29C040P", WINBOND_ID, W_29C040P, 512, 256, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Winbond", "W29C020C", WINBOND_ID, W_29C020C, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, > + {"Winbond", "W29EE011", WINBOND_ID, W_29C011, 128, 128, probe_w29ee011, erase_chip_jedec, write_jedec}, > + {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, > + {"Winbond/N.", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Winbond/N.", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Winbond/N.", "W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Winbond/N.", "W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, > + {"ST", "M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, > + {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, > + {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, > + {"ST", "M25P05-A", ST_ID, ST_M25P05A, 64, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P10-A", ST_ID, ST_M25P10A, 128, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P20", ST_ID, ST_M25P20, 256, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P40", ST_ID, ST_M25P40, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P80", ST_ID, ST_M25P80, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P16", ST_ID, ST_M25P16, 2048, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P32", ST_ID, ST_M25P32, 4096, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P64", ST_ID, ST_M25P64, 8192, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, > + {"Intel", "82802ab", INTEL_ID, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, > + {"Intel", "82802ac", INTEL_ID, 172, 1024, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, > + {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, probe_jedec, erase_chip_jedec, write_49f002}, > #ifndef DISABLE_DOC > - {"MD-2802 (M-Systems DiskOnChip Millennium Module)", > - MSYSTEMS_ID, MSYSTEMS_MD2802,8, 8 * 1024, > - probe_md2802, erase_md2802, write_md2802, read_md2802}, > + {"M-Systems", "MD-2802", MSYSTEMS_ID, MSYSTEMS_MD2802, 8, 8 * 1024, probe_md2802, erase_md2802, write_md2802, read_md2802}, > #endif > - {"LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, > - probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, > - {"S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, > - probe_jedec, erase_chip_jedec, write_49f002}, > - {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID, 0, 0, > - probe_spi, NULL, NULL}, > - {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, > - probe_spi, NULL, NULL}, > - {"PMC unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, > - probe_spi, NULL, NULL}, > - {"SST unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, > - probe_spi, NULL, NULL}, > - {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, > - probe_spi, NULL, NULL}, > + {"Sharp", "LHF00L04", SHARP_ID, SHARP_LHF00L04, 1024, 64 * 1024, probe_lhf00l04, erase_lhf00l04, write_lhf00l04}, > + {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, probe_jedec, erase_chip_jedec, write_49f002}, > + {"EON", "unknown SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, > + {"Macronix", "unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, > + {"PMC", "unknown SPI chip", PMC_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, > + {"SST", "unknown SPI chip", SST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, > + {"ST", "unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, > {NULL,} > }; > > -- http://www.hailfinger.org/

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coreboot March 2008