coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

r3151 build service
by coreboot information 15 Mar '08

15 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3151 to the coreboot source repository and caused the following changes: Change Log: remove nasty warning that happened due to our vendor detection mechanism. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3151&device=serengeti_chee… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3151 - trunk/util/flashrom
by svn＠coreboot.org 15 Mar '08

15 Mar '08

Author: stepan Date: 2008-03-16 00:41:19 +0100 (Sun, 16 Mar 2008) New Revision: 3151 Modified: trunk/util/flashrom/flashrom.c Log: remove nasty warning that happened due to our vendor detection mechanism. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-03-15 16:30:39 UTC (rev 3150) +++ trunk/util/flashrom/flashrom.c 2008-03-15 23:41:19 UTC (rev 3151) @@ -129,9 +129,12 @@ */ if (getpagesize() > size) { + /* + * if a flash size of 0 is mapped, we map a single page + * so we can probe in that area whether we know the + * vendor at least. + */ size = getpagesize(); - printf("WARNING: size: %d -> %ld (page size)\n", - flash->total_size * 1024, (unsigned long)size); } bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,

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r3150 build service
by coreboot information 15 Mar '08

15 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3150 to the coreboot source repository and caused the following changes: Change Log: fix typo Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3150&device=serengeti_chee… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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RCA RM4100 Build Tutorial
by joe＠smittys.pointclark.net 15 Mar '08

15 Mar '08

Hello, I added a Build Tutorial to the wiki: http://www.coreboot.org/RCA_RM4100_Build_Tutorial and linked it to the Supported Motherboards page. I am going to send some users from my website to try it out. Some of the info may be redundent but it is meant for a coreboot newby? Does it look like newby material? Thanks - Joe

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r3150 - trunk/util/mptable
by svn＠coreboot.org 15 Mar '08

15 Mar '08

Author: stepan Date: 2008-03-15 17:30:39 +0100 (Sat, 15 Mar 2008) New Revision: 3150 Modified: trunk/util/mptable/mptable.c Log: fix typo Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/mptable/mptable.c =================================================================== --- trunk/util/mptable/mptable.c 2008-03-15 12:26:12 UTC (rev 3149) +++ trunk/util/mptable/mptable.c 2008-03-15 16:30:39 UTC (rev 3150) @@ -425,7 +425,7 @@ if (verbose) puts( SEP_LINE2 ); - printf( "/* generatred by MPTable, version %d.%d.%d*/\n", VMAJOR, VMINOR, VDELTA ); + printf( "/* generated by MPTable, version %d.%d.%d*/\n", VMAJOR, VMINOR, VDELTA ); printf("/* as modified by RGM for coreboot */\n"); write_code(preamble);

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r3149 build service
by coreboot information 15 Mar '08

15 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3149 to the coreboot source repository and caused the following changes: Change Log: BIOS_SPEW is log level 9. There is nothing beyound that line. (Thus the patch is trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3149&device=serengeti_chee… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3149 - in trunk/coreboot-v2/targets: amd/db800 amd/norwich amd/serengeti_cheetah_fam10 artecgroup/dbe61 dell/s1850 digitallogic/adl855pc digitallogic/msm586seg digitallogic/msm800sev olpc/rev_a pcengines/alix1c technologic/ts5300 via/epia
by svn＠coreboot.org 15 Mar '08

15 Mar '08

Author: stepan Date: 2008-03-15 13:26:12 +0100 (Sat, 15 Mar 2008) New Revision: 3149 Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb trunk/coreboot-v2/targets/amd/norwich/Config.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb trunk/coreboot-v2/targets/dell/s1850/Config.lb trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb trunk/coreboot-v2/targets/olpc/rev_a/Config.lb trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb Log: BIOS_SPEW is log level 9. There is nothing beyound that line. (Thus the patch is trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/amd/db800/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -34,8 +34,8 @@ # option ROM_SIZE=256*1024-36*1024 option FALLBACK_SIZE=ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 # option DEFAULT_CONSOLE_LOGLEVEL = 4 # option MAXIMUM_CONSOLE_LOGLEVEL = 4 Modified: trunk/coreboot-v2/targets/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/amd/norwich/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -34,8 +34,8 @@ #option ROM_SIZE=256*1024-36*1024 option FALLBACK_SIZE=ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 #option DEFAULT_CONSOLE_LOGLEVEL = 4 #option MAXIMUM_CONSOLE_LOGLEVEL = 4 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -25,9 +25,9 @@ target serengeti_cheetah_fam10 mainboard amd/serengeti_cheetah_fam10 # Request this level of debugging output - option DEFAULT_CONSOLE_LOGLEVEL=11 + option DEFAULT_CONSOLE_LOGLEVEL=9 # At a maximum only compile in this level of debugging - option MAXIMUM_CONSOLE_LOGLEVEL=11 + option MAXIMUM_CONSOLE_LOGLEVEL=9 # 1024KB ROM option ROM_SIZE=1024*1024 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -25,9 +25,9 @@ target serengeti_cheetah_fam10 mainboard amd/serengeti_cheetah_fam10 # Request this level of debugging output - option DEFAULT_CONSOLE_LOGLEVEL=11 + option DEFAULT_CONSOLE_LOGLEVEL=9 # At a maximum only compile in this level of debugging - option MAXIMUM_CONSOLE_LOGLEVEL=11 + option MAXIMUM_CONSOLE_LOGLEVEL=9 # 512KB ROM option ROM_SIZE=512*1024 Modified: trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -23,8 +23,8 @@ option FALLBACK_SIZE = ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0Fallback" Modified: trunk/coreboot-v2/targets/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/targets/dell/s1850/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/dell/s1850/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -2,8 +2,8 @@ mainboard dell/s1850 option ROM_SIZE=1024*1024 -option MAXIMUM_CONSOLE_LOGLEVEL=10 -option DEFAULT_CONSOLE_LOGLEVEL=10 +option MAXIMUM_CONSOLE_LOGLEVEL=9 +option DEFAULT_CONSOLE_LOGLEVEL=9 romimage "normal" option USE_FALLBACK_IMAGE=0 Modified: trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/digitallogic/adl855pc/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -4,8 +4,8 @@ target adl855pc mainboard digitallogic/adl855pc -option DEFAULT_CONSOLE_LOGLEVEL=10 -option MAXIMUM_CONSOLE_LOGLEVEL=10 +option DEFAULT_CONSOLE_LOGLEVEL=9 +option MAXIMUM_CONSOLE_LOGLEVEL=9 romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 Modified: trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -3,8 +3,8 @@ -option DEFAULT_CONSOLE_LOGLEVEL=10 -option MAXIMUM_CONSOLE_LOGLEVEL=10 +option DEFAULT_CONSOLE_LOGLEVEL=9 +option MAXIMUM_CONSOLE_LOGLEVEL=9 option CONFIG_COMPRESS=0 __COMPRESSION__ Modified: trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/digitallogic/msm800sev/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -17,8 +17,8 @@ option FALLBACK_SIZE = ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=".0Fallback" Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.1M.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -11,8 +11,8 @@ option ROM_SIZE=(1024*1024)-(64*1024) option FALLBACK_SIZE=ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.SPI.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -12,8 +12,8 @@ option ROM_SIZE=(1024*1024)-(64*1024)-(64*1024) option FALLBACK_SIZE=ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 Modified: trunk/coreboot-v2/targets/olpc/rev_a/Config.lb =================================================================== --- trunk/coreboot-v2/targets/olpc/rev_a/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/olpc/rev_a/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -8,8 +8,8 @@ option ROM_SIZE=512*1024-64*1024 option FALLBACK_SIZE=ROM_SIZE -option DEFAULT_CONSOLE_LOGLEVEL = 11 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=32*1024 Modified: trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb =================================================================== --- trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/pcengines/alix1c/Config.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -14,7 +14,7 @@ option FALLBACK_SIZE = ROM_SIZE option DEFAULT_CONSOLE_LOGLEVEL = 3 -option MAXIMUM_CONSOLE_LOGLEVEL = 11 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE = 1 Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -1,8 +1,8 @@ target technologic_ts5300 mainboard technologic/ts5300 -option DEFAULT_CONSOLE_LOGLEVEL=10 -option MAXIMUM_CONSOLE_LOGLEVEL=10 +option DEFAULT_CONSOLE_LOGLEVEL=9 +option MAXIMUM_CONSOLE_LOGLEVEL=9 option CONFIG_COMPRESS=0 __COMPRESSION__ Modified: trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb 2008-03-15 00:26:50 UTC (rev 3148) +++ trunk/coreboot-v2/targets/via/epia/Config.512kflash.linuxtiny.lb 2008-03-15 12:26:12 UTC (rev 3149) @@ -6,8 +6,8 @@ option ROM_SIZE=512*1024 option FALLBACK_SIZE=ROM_SIZE -option MAXIMUM_CONSOLE_LOGLEVEL=10 -option DEFAULT_CONSOLE_LOGLEVEL=10 +option MAXIMUM_CONSOLE_LOGLEVEL=9 +option DEFAULT_CONSOLE_LOGLEVEL=9 romimage "fallback" option USE_FALLBACK_IMAGE=1

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[PATCH] extend the VT8237R ROM decode
by Rudolf Marek 15 Mar '08

15 Mar '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFH2Fx83J9wPJqZRNURAkueAJ9+1lSy8QMFXZwVptPmFEx8V31H6ACgiBHh SFuUJVOcaCIh6SlmWXAcaBM= =7DlI -----END PGP SIGNATURE-----

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Re: [coreboot] .. Re: Via epia
by jtd 15 Mar '08

15 Mar '08

On Friday 14 March 2008 10:48 pm, Uwe Hermann wrote: > > Please feel free post a patch for the board in early stages, > doesn't have to fully work, yet. It's usually better to get > feedback early, that'll reduce the time until the code gets > committed. > > Is this the VIA iDot PC3500E board btw? Please post some more info > on the board, e.g. lspci -tvnn, superiotool -dV for reference. lspci -tvnn -[0000:00]-+-00.0 VIA Technologies, Inc. VT8623 [Apollo CLE266] [1106:3123] +-01.0-[0000:01]----00.0 VIA Technologies, Inc. VT8623 [Apollo CLE266] integrated CastleRock graphics [1106:3122] +-0d.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8235 ISA Bridge [1106:3177] +-11.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] \-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] relevant parts of superiotool -dV Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x3) at 0x2e Register dump: idx 07 20 21 22 23 24 val 03 87 05 03 00 01 def NA 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 0a def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 80 0c 08 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 00 00 00 00 10 00 00 2f 00 00 01 00 00 00 00 00 2f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Found ITE IT8705F/AF / IT8700F (id=0x8705, rev=0x3) at 0x4e Register dump: idx 07 20 21 22 23 24 val 08 87 05 03 00 01 def NA 87 05 00 00 NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 03 f8 04 00 LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 64 65 70 74 f0 val 01 03 78 07 78 00 80 07 03 0a def 00 03 78 07 78 00 80 07 03 03 LDN 0x04 (Environment controller) idx 2b 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 00 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (GPIO) idx 25 26 27 28 29 2a 60 61 62 63 64 65 70 71 72 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d8 d9 da f0 f1 f2 f5 f6 f7 f8 f9 fa fb fc fd fe ff val 00 00 00 00 80 0c 08 00 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 00 00 00 00 10 00 00 2f 00 00 01 00 00 00 00 00 2f 00 def 00 00 00 ff e0 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x06 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x07 (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 -- Rgds JTD

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r3148 build service
by coreboot information 14 Mar '08

14 Mar '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3148 to the coreboot source repository and caused the following changes: Change Log: Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3148&device=serengeti_chee… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot March 2008