coreboot December 2008

coreboot@coreboot.org

77 participants
330 discussions

can AAI be used in flashrom?
by Bao, Zheng 25 Dec '08

25 Dec '08

The AAI (Auto Address Increment Programming) command (0xAD) can be found in SST25VF080B. I am wondering if it is available in every SPI chip. If yes, the SB600 pragramming would be much faster than doing it one byte at a time. I tested on my board with SB600. I don't make a patch because I am not sure I can do that. Zheng int sb600_spi_write(struct flashchip *flash, uint8_t *buf) { int rc = 0, i; int total_size = flash->total_size * 1024; uint8_t cmd[8] = {0xAD, 0x00, 0x00, 0x00}; /* Erase first */ printf("Erasing flash before programming... "); flash->erase(flash); printf("done.\n"); cmd[4] = buf[0]; cmd[5] = buf[1]; spi_disable_blockprotect(); spi_write_enable(); sb600_spi_command(6, 0, cmd, 0); printf("Programming flash"); for (i = 2, buf += 2; i < total_size; i+=2, buf+=2) { /* spi_byte_program(i, *buf); */ cmd[1] = buf[0]; cmd[2] = buf[1]; sb600_spi_command(3, 0, cmd, 0); /* wait program complete. */ if (i % 0x8000 == 0) printf("."); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) ; } printf(" done.\n"); spi_write_disable(); return rc; }

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Re: [coreboot] coreboot Digest, Vol 46, Issue 179
by JasonZhao＠viatech.com.cn 25 Dec '08

25 Dec '08

> On Wed, Dec 24, 2008 at 12:16:14AM +0100, Rudolf Marek wrote: > >> The K8M890 BIOS needs int 0x15 0x5f18 to write to scratch register for > >> a driver the memory size of framebuffer and also the memory speed. The > >> X.org openchrome driver as well Unichrome driver needs that. > [...] > > diff --git a/src/vgahooks.c b/src/vgahooks.c > > index 7c229ba..86050fd 100644 > > --- a/src/vgahooks.c > > +++ b/src/vgahooks.c > [...] > > + bdf = pci_find_device(PCI_VENDOR_ID_VIA, 0x3336); /* K8M890 supported > so far */ > [...] > > + bdf = pci_find_device(PCI_VENDOR_ID_AMD, > PCI_DEVICE_ID_AMD_K8_NB_MEMCTL); /* get the memory speed */ > I had added some very similar code on my VX800 port, except the location of pci register that get speed of DDR2(mine is 0x90). I add those code in both vgahook.c of Seabios and vgabios.c of Coreboot > I thought the code would be vga chip dependent. However, it looks > like it depends on both the chipset and vga chip. Yes chipset dependency > It's going to be hard to maintain cpu and chipset specific features in > SeaBIOS. I wonder if we can find an alternative. I also wonder. > Can you provide more details on what you're seeing? The VGA BIOS is > calling int 155f18 and then populating a register in the vga card's > pci config space? If so, could coreboot populate the register > directly? Maybe 155f is VGABIOS dependent? Yesterday, I test two different VGABIOS on my VX800 board for my coreboot code. First one is extracted from legacy bios on board, which doesn't play with my 155fcallback(s3 resume fails). Second one (I don't know where it is from), however, seems work fine. > -Kevin

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Do it! Notebooks/laptops users need that
by ahmed ahmedov 25 Dec '08

25 Dec '08

Hello, Thas is the first and important step for me, to get my notebook out from restriction... i Have HP notebook and BIOS sucks! Booting VISTA ..I dont use it...peace of crap... I have Ubuntu 8.10 and WinXP but I realy want to use my noteboook without error for 104 Device when i change my wireless adapter, or another hard drive, RAM or new processor.... really that can make revolution for Laptops/Notebooks Users. Make the BEST. here is my Note book info: --------[ EVEREST Ultimate Edition ]------------------------------------------------------------------------------------ Version EVEREST Benchmark Module Homepage Report Type Report Wizard Computer Generator Operating System Microsoft Windows XP Professional 5.1.2600 (WinXP Retail) Date 2008-12-25 Time 01:33 --------[ Summary ]----------------------------------------------------------------------------------------------------- Computer: Computer Type ACPI Uniprocessor PC (Mobile) Operating System Microsoft Windows XP Professional OS Service Pack Service Pack 3 Internet Explorer 6.0.2900.5512 DirectX 4.09.00.0904 (DirectX 9.0c) Computer Name User Name Logon Domain Date / Time 2008-12-25 / 01:33 Motherboard: CPU Type Mobile Intel Celeron 550, 2000 MHz (15 x 133) Motherboard Name Hewlett-Packard HP 550 Motherboard Chipset Intel Crestline GLE960 System Memory 1015 MB (DDR2-667 DDR2 SDRAM) DIMM3: Ramaxel Tech. RMN1150EC48D7F-667 1 GB DDR2-667 DDR2 SDRAM (5-5-5-15 @ 333 MHz) (4-4-4-12 @ 266 MHz) BIOS Type Compaq (08/20/08) Display: Video Adapter Mobile Intel(R) 965 Express Chipset Family (384 MB) Video Adapter Mobile Intel(R) 965 Express Chipset Family (384 MB) 3D Accelerator Intel GMA X3100 Monitor Samsung 154AT07-H01 [15.4" LCD] Monitor Samsung 154AT07-H01 [15.4" LCD] Monitor Samsung 154AT07-H01 [15.4" LCD] Multimedia: Audio Adapter Analog Devices AD1981HD @ Intel 82801HBM ICH8M - High Definition Audio Controller Storage: IDE Controller Intel(R) ICH8M 3 port Serial ATA Storage Controller - 2828 Storage Controller A9H7X3M3 IDE Controller Storage Controller NERO IMAGEDRIVE SCSI Controller Storage Controller SCSI/RAID Host Controller Disk Drive Hitachi HTS543212L9A300 (120 GB, 5400 RPM, SATA-II) Disk Drive Multi Flash Reader USB Device (988 MB, USB) Optical Drive BR0117O YBN241J SCSI CdRom Device Optical Drive TSSTcorp CDDVDW TS-L632N Optical Drive ZYVY FOTYRS5EZC5 SCSI CdRom Device SMART Hard Disks Status OK Partitions: C: (NTFS) 99472 MB (8932 MB free) Total Size 99472 MB (8932 MB free) Input: Keyboard HID Keyboard Device Keyboard Standard 101/102-Key or Microsoft Natural PS/2 Keyboard Mouse HID-compliant mouse Mouse Synaptics PS/2 Port TouchPad Network: Primary IP Address 5.123.250.2 Primary MAC Address Network Adapter Broadcom 4xxx 802.11g (192.168.0.101) Network Adapter Hamachi Network Interface - Wireless Intermediate Driver (5.123.250.2) Network Adapter Intel(R) 82562GT 10/100 Network Connection Modem Agere Systems HDA Modem Peripherals: Printer Adobe PDF Printer HP Deskjet F2200 series Printer Microsoft Office Document Image Writer Printer Microsoft XPS Document Writer Printer PDF Complete USB1 Controller Broadcom BCM4310 USB Controller USB1 Controller Intel 82801HBM ICH8M - USB Universal Host Controller USB1 Controller Intel 82801HBM ICH8M - USB Universal Host Controller USB1 Controller Intel 82801HBM ICH8M - USB Universal Host Controller USB1 Controller Intel 82801HBM ICH8M - USB Universal Host Controller USB2 Controller Intel 82801HBM ICH8M - USB2 Enhanced Host Controller USB2 Controller Intel 82801HBM ICH8M - USB2 Enhanced Host Controller USB Device SoC PC-Camera USB Device USB Human Interface Device USB Device USB Mass Storage Device Battery Microsoft AC Adapter Battery Microsoft ACPI-Compliant Control Method Battery DMI: DMI BIOS Vendor Hewlett-Packard DMI BIOS Version 68MVU Ver. F.02 DMI System Manufacturer Hewlett-Packard DMI System Product HP 550 DMI System Version F.02 DMI System Serial Number DMI System UUID DMI Motherboard Manufacturer Hewlett-Packard DMI Motherboard Product 3618 DMI Motherboard Version KBC Version 12.00 DMI Motherboard Serial Number DMI Chassis Manufacturer Hewlett-Packard DMI Chassis Version DMI Chassis Serial Number DMI Chassis Asset Tag DMI Chassis Type Notebook --------[ Debug - PCI ]------------------------------------------------------------------------------------------------- B00 D00 F00: Intel GLE960/GME965 Chipset - Memory Controller Hub Offset 000: 86 80 10 2A 06 00 90 20 0C 00 00 06 00 00 00 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 Offset 040: 01 90 D9 FE 00 00 00 00 01 40 D9 FE 00 00 00 00 Offset 050: 00 00 30 00 19 03 00 00 00 00 00 00 00 00 00 00 Offset 060: 05 00 00 F8 00 00 00 00 01 80 D9 FE 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 01 10 00 00 00 00 00 00 Offset 080: 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 10 11 11 01 00 13 11 00 FF 03 00 00 00 1A B8 00 Offset 0A0: 08 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 60 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 04 01 00 00 Offset 0E0: 09 00 0A 91 B1 EC 00 73 C4 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 90 0F 06 00 10 00 00 00 B00 D02 F00: Intel GLE960/GME965 Chipset - Integrated Graphics 0 Offset 000: 86 80 12 2A 07 00 90 00 0C 00 00 03 00 00 80 00 Offset 010: 04 00 40 E4 00 00 00 00 0C 00 00 D0 00 00 00 00 Offset 020: 01 40 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 90 00 00 00 00 00 00 00 10 01 00 00 Offset 040: 00 00 00 00 48 00 00 00 09 00 0A 91 B1 EC 00 73 Offset 050: C4 00 30 00 19 00 00 00 00 00 00 00 00 00 80 3F Offset 060: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 05 D0 00 00 D8 04 06 A9 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 01 01 01 01 00 00 00 00 40 01 00 00 Offset 0D0: 01 00 23 00 00 00 01 01 01 01 00 94 34 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 Offset 0F0: 01 02 34 07 FF 00 00 00 90 0F 06 00 00 54 7C 3F B00 D02 F01: Intel GLE960/GME965 Chipset - Integrated Graphics 1 Offset 000: 86 80 13 2A 07 00 90 00 0C 00 80 03 00 00 80 00 Offset 010: 04 00 50 E4 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 D0 00 00 00 00 00 00 00 00 00 00 00 Offset 040: 00 00 00 00 48 00 00 00 09 00 0A 91 B1 EC 00 73 Offset 050: C4 00 30 00 19 00 00 00 00 00 00 00 00 00 80 3F Offset 060: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 01 01 01 01 00 00 00 00 40 01 00 00 Offset 0D0: 01 00 23 00 00 00 01 01 01 01 00 94 34 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 Offset 0F0: 01 02 34 07 FF 00 00 00 90 0F 06 00 00 00 00 00 B00 D19 F00: Intel 82562GT 10/100 Network Connection Offset 000: 86 80 C4 10 07 00 10 00 03 00 00 02 00 00 00 00 Offset 010: 00 00 60 E4 00 00 62 E4 21 40 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 D8 30 Offset 030: 00 00 00 00 C8 00 00 00 00 00 00 00 16 01 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 01 D0 22 C8 00 20 00 04 Offset 0D0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B00 D1A F00: Intel 82801HBM ICH8M - USB Universal Host Controller Offset 000: 86 80 34 28 05 00 80 02 03 00 03 0C 00 00 80 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 41 40 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 00 00 00 00 00 00 00 00 10 01 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 2F 00 00 00 00 00 00 00 00 01 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1A F07: Intel 82801HBM ICH8M - USB2 Enhanced Host Controller Offset 000: 86 80 3A 28 06 00 90 02 03 20 03 0C 00 00 00 00 Offset 010: 00 10 62 E4 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 50 00 00 00 00 00 00 00 12 03 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 01 58 C2 C9 00 00 00 00 0A 00 A0 20 00 00 00 00 Offset 060: 20 20 E1 00 00 00 00 00 01 00 00 00 00 00 00 C0 Offset 070: 00 00 C7 03 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 AA FF 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 88 85 40 00 86 0F 06 00 0A 17 02 20 B00 D1B F00: Intel 82801HBM ICH8M - High Definition Audio Controller Offset 000: 86 80 4B 28 06 00 10 00 03 00 03 04 10 00 00 00 Offset 010: 04 40 62 E4 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 50 00 00 00 00 00 00 00 10 01 00 00 Offset 040: 01 00 00 03 07 00 00 00 00 00 00 00 00 80 00 00 Offset 050: 01 60 42 C8 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 10 00 91 00 C0 0F 00 00 00 08 10 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1C F00: Intel 82801HBM ICH8M - PCI Express Root Port 1 Offset 000: 86 80 3F 28 07 00 10 00 03 00 04 06 10 00 81 00 Offset 010: 00 00 00 00 00 00 00 00 00 08 08 00 F0 00 00 20 Offset 020: F0 FF 00 00 F1 FF 01 00 00 00 00 00 00 00 00 00 Offset 030: 00 00 00 00 40 00 00 00 00 00 00 00 10 01 04 00 Offset 040: 10 80 41 00 C0 8F 00 00 00 00 10 00 11 4C 11 01 Offset 050: 00 00 01 10 60 05 10 00 00 00 40 00 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 0D A0 00 00 3C 10 18 36 00 00 00 00 00 00 00 00 Offset 0A0: 01 00 02 C8 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 Offset 0E0: 00 0F C7 00 06 07 08 00 31 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1C F01: Intel 82801HBM ICH8M - PCI Express Root Port 2 Offset 000: 86 80 41 28 07 00 10 00 03 00 04 06 10 00 81 00 Offset 010: 00 00 00 00 00 00 00 00 00 10 10 00 F0 00 00 00 Offset 020: 00 E4 00 E4 F1 FF 01 00 00 00 00 00 00 00 00 00 Offset 030: 00 00 00 00 40 00 00 00 00 00 00 00 11 02 04 00 Offset 040: 10 80 41 01 C0 8F 00 00 00 00 10 00 11 2C 11 02 Offset 050: 43 00 11 30 60 08 11 00 00 00 40 01 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 0D A0 00 00 3C 10 18 36 00 00 00 00 00 00 00 00 Offset 0A0: 01 00 02 C8 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 11 88 00 00 00 00 Offset 0E0: 00 0F C7 00 06 07 08 00 33 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1C F04: Intel 82801HBM ICH8M - PCI Express Root Port 5 Offset 000: 86 80 47 28 07 00 10 00 03 00 04 06 10 00 81 00 Offset 010: 00 00 00 00 00 00 00 00 00 28 28 00 20 30 00 20 Offset 020: 00 E0 F0 E3 F1 FF 01 00 00 00 00 00 00 00 00 00 Offset 030: 00 00 00 00 40 00 00 00 00 00 00 00 10 01 04 00 Offset 040: 10 80 41 01 C0 8F 00 00 00 00 10 00 11 4C 11 05 Offset 050: 00 00 01 10 60 08 29 00 09 00 00 00 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 0D A0 00 00 3C 10 18 36 00 00 00 00 00 00 00 00 Offset 0A0: 01 00 02 C8 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 11 C8 00 00 00 00 Offset 0E0: 00 0F C7 00 06 07 08 00 31 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1D F00: Intel 82801HBM ICH8M - USB Universal Host Controller Offset 000: 86 80 30 28 05 00 80 02 03 00 03 0C 00 00 80 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 61 40 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 00 00 00 00 00 00 00 00 14 01 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 2F 00 00 00 00 00 00 00 00 01 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1D F01: Intel 82801HBM ICH8M - USB Universal Host Controller Offset 000: 86 80 31 28 05 00 80 02 03 00 03 0C 00 00 00 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 81 40 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 00 00 00 00 00 00 00 00 15 02 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 2F 00 00 00 00 00 00 00 00 01 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1D F02: Intel 82801HBM ICH8M - USB Universal Host Controller Offset 000: 86 80 32 28 05 00 80 02 03 00 03 0C 00 00 00 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: A1 40 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 00 00 00 00 00 00 00 00 12 03 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 2F 00 00 00 00 00 00 00 00 01 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1D F07: Intel 82801HBM ICH8M - USB2 Enhanced Host Controller Offset 000: 86 80 36 28 06 00 90 02 03 20 03 0C 00 00 00 00 Offset 010: 00 80 62 E4 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 50 00 00 00 00 00 00 00 14 01 00 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 01 58 C2 C9 00 00 00 00 0A 00 A0 20 00 00 00 00 Offset 060: 20 20 9F 00 00 00 00 00 01 00 00 00 00 00 00 C0 Offset 070: 00 00 DD 3F 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 AA FF 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 88 85 40 00 86 0F 06 00 0A 17 02 20 B00 D1E F00: Intel 82801HBM I/O Controller Hub 8 (ICH8M) Offset 000: 86 80 48 24 07 01 10 00 F3 01 04 06 00 00 01 00 Offset 010: 00 00 00 00 00 00 00 00 00 02 02 20 F0 00 80 22 Offset 020: F0 FF 00 00 F1 FF 01 00 00 00 00 00 00 00 00 00 Offset 030: 00 00 00 00 50 00 00 00 00 00 00 00 FF 00 06 00 Offset 040: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 Offset 050: 0D 00 00 00 3C 10 18 36 00 00 00 00 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1F F00: Intel 82801HBM ICH8M-DO - LPC Bridge Offset 000: 86 80 15 28 07 00 10 02 03 00 01 06 00 00 80 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 E0 00 00 00 00 00 00 00 00 00 00 00 Offset 040: 01 10 00 00 80 00 00 00 01 11 00 00 10 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 80 80 80 80 92 00 00 00 80 80 80 80 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 10 00 00 3C 01 05 7C 00 00 00 00 00 00 00 00 00 Offset 090: E9 02 04 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 24 06 00 00 E1 00 03 00 13 1C 0B 00 00 03 00 00 Offset 0B0: 00 00 F0 00 00 00 00 00 04 A0 62 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 33 22 11 00 67 45 00 00 00 C0 00 00 00 00 00 00 Offset 0E0: 09 00 0C 10 20 02 4C C3 64 00 00 00 00 00 00 00 Offset 0F0: 01 00 D9 FE 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1F F02: Intel 82801HBM ICH8M - 3-port SATA Controller Offset 000: 86 80 28 28 05 00 B0 02 03 80 01 01 00 00 00 00 Offset 010: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 Offset 020: C1 40 00 00 D1 40 00 00 00 00 00 00 3C 10 18 36 Offset 030: 00 00 00 00 70 00 00 00 00 00 00 00 0A 02 00 00 Offset 040: 07 A3 07 A3 00 00 00 00 01 00 01 00 00 00 00 00 Offset 050: 00 00 00 00 11 10 00 00 00 00 00 00 00 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 01 00 03 40 08 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 02 00 05 81 80 01 00 40 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 0D 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B00 D1F F03: Intel 82801HBM ICH8M - SMBus Controller Offset 000: 86 80 3E 28 01 00 80 02 03 00 05 0C 00 00 00 00 Offset 010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 01 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 030: 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 Offset 040: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 060: 03 04 04 00 00 00 08 08 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 86 0F 06 00 00 00 00 00 B10 D00 F00: Broadcom BCM4310 USB Controller Offset 000: E4 14 15 43 06 00 10 00 01 00 80 02 10 00 00 00 Offset 010: 04 00 00 E4 00 00 00 00 00 00 00 00 00 00 00 00 Offset 020: 00 00 00 00 00 00 00 00 00 00 00 00 3C 10 7D 13 Offset 030: 00 00 00 00 40 00 00 00 00 00 00 00 11 01 00 00 Offset 040: 01 58 03 06 08 40 00 00 00 00 00 00 00 00 00 00 Offset 050: 00 00 00 00 00 00 00 00 09 E8 78 00 09 00 00 00 Offset 060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 080: 00 10 00 18 00 00 00 00 01 00 00 00 03 00 00 00 Offset 090: 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 Offset 0A0: 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 Offset 0B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 0D0: 10 00 01 00 A0 8F 40 08 00 00 09 00 11 6C 03 00 Offset 0E0: 43 00 11 10 00 00 00 00 05 D0 80 00 00 00 00 00 Offset 0F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI-8086-2A10: Intel i965M/ME MCHBAR Offset C00: 31 03 00 00 01 01 01 01 00 80 00 00 00 00 00 00 Offset C10: 00 00 00 00 10 00 8B 34 00 00 00 00 00 00 00 00 Offset C20: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset C30: 00 00 00 00 00 00 00 00 B8 0B 3D 0C 00 00 00 00 Offset C40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset C50: 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 Offset C60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset C70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset C80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset C90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CA0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CB0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CC0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CD0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CE0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset CF0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI-8086-2A10: Intel i965M/ME MCHBAR Offset 1000: 72 00 93 00 00 04 6F 00 6F 00 00 00 00 6F 6E 00 Offset 1010: 17 22 00 80 00 00 00 00 83 00 00 00 99 83 00 00 Offset 1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1040: 7F 00 01 00 00 00 FF 00 FF 00 00 40 40 00 00 00 Offset 1050: 00 00 00 80 00 00 00 00 80 00 00 00 99 80 00 00 Offset 1060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1070: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1080: 0E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10E0: 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 Offset 10F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI-8086-2A10: Intel i965M/ME MCHBAR Offset 1200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Offset 1210: 41 08 91 2C 42 80 80 01 50 10 1C 22 01 41 84 00 Offset 1220: 50 28 0C 39 22 00 85 62 00 68 00 00 00 00 00 00 Offset 1230: 0A 02 00 40 00 18 0F 00 00 10 00 0F 00 00 00 00 PCI-8086-2A10: Intel i965M/ME MCHBAR Offset 1300: 20 00 20 00 20 00 20 00 03 00 09 00 03 00 00 00 Offset 1310: 41 08 91 2C 42 80 80 01 50 10 1C 22 01 42 84 00 Offset 1320: 50 28 0C 39 32 00 85 62 00 68 00 00 00 00 00 00 Offset 1330: 0A 02 00 40 00 18 0E B1 00 10 00 0E 00 00 00 00 --------[ Debug - Video BIOS ]------------------------------------------------------------------------------------------ C000:0000 U.w.[.000000000000.".5!.@...00IBM VGA Compatible BIOS. .Z.j.x... C000:0040 PCIR...*................................t.............\......... C000:0080 ...................................d......d......d.....0d......d C000:00C0 ......d......d......d.....0d......d.....0d......d......d......d. C000:0100 .....d.....0d......d......d.....0$......$......d.......... ....` C000:0140 ".......N... ....@............ ...88.......... .1X. (.........V. C000:0180 .1X. .P.......... .0X. @........d..@A.&0..6.......... A. 0.`.. C000:01C0 .......$.`A.(00`........0*..Q.*@0p.........4..Q.*@...........=.. C000:0200 Q.0@@.........H?@0b.2@@..........O@0b.2@@..........Y@0b.2@@..... C000:0240 ....h[..r.<P...........t..r.<P..........0.6..2.l..4....8....:... C000:0280 .<.D..A.6..C.l..E....I....K....M.D..P 6..R l..T ...X ...Z ...\ D C000:02C0 ..`....a....b ...c....d....e ...f....g....h ...i....j....k ...l. C000:0300 ...m....n ...o....p....q ....................................... C000:0340 ........................................................For Eval C000:0380 uation Use Only....(........c-'(.+.............................. C000:03C0 ...................(........c-'(.+.............................. --------[ Debug - Unknown ]--------------------------------------------------------------------------------------------- PnP SYN0159: Synaptics PS/2 Port TouchPad [NoDB] ------------------------------------------------------------------------------------------------------------------------ The names of actual companies and products mentioned herein may be the trademarks of their respective owners. -- Using Opera's revolutionary e-mail client: http://www.opera.com/mail/

1 0

Re: [coreboot] [RFC] Error out on implicit declarations
by Bao, Zheng 24 Dec '08

24 Dec '08

Carl-Daniel, Can you acked-by these patches for implicit declaration? Zheng -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng Sent: Monday, December 22, 2008 10:15 AM To: Coreboot Cc: Li, Maggie Subject: [coreboot] FW: [RFC] Error out on implicit declarations I have modified the patch. The changes are limited to board and southbridge code. Zheng Signed-off-by: Maggie Li Maggie.li(a)amd.com Reviewed-by: Zheng bao <Zheng.bao(a)amd.com>

3 11

r3844 - in trunk/coreboot-v2/src/mainboard/amd: dbm690t pistachio
by svn＠coreboot.org 24 Dec '08

24 Dec '08

Author: hailfinger Date: 2008-12-24 19:23:00 +0100 (Wed, 24 Dec 2008) New Revision: 3844 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/pistachio/fadt.c trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c Log: Fix AMD Pistachio implicit declarations in the same way as with AMD DBM690T. Remove trailing whitespace. Signed-off-by: Zheng Bao <Zheng.bao(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-24 17:58:44 UTC (rev 3843) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-24 18:23:00 UTC (rev 3844) @@ -35,7 +35,7 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, +extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -246,16 +246,16 @@ get_ide_dma66(); set_thermal_config(); } - + int add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", +#if (CONFIG_GFXUMA == 1) + printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", uma_memory_start, uma_memory_size); - lb_add_memory_range(mem, LB_MEM_RESERVED, + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_start, uma_memory_size); #endif } Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/fadt.c 2008-12-24 17:58:44 UTC (rev 3843) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/fadt.c 2008-12-24 18:23:00 UTC (rev 3844) @@ -25,8 +25,9 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include <../southbridge/amd/sb600/sb600.h> -extern void pm_iowrite(u8 reg, u8 value); /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ /* pm_base should be got from bar2 of rs690. Here I compact ACPI Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2008-12-24 17:58:44 UTC (rev 3843) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2008-12-24 18:23:00 UTC (rev 3844) @@ -25,19 +25,16 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <../southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7475_ADDRESS 0x2E #define SMBUS_IO_BASE 0x1000 -extern u8 pm_ioread(u8 reg); -extern void pm_iowrite(u8 reg, u8 value); -extern u8 pm2_ioread(u8 reg); -extern void pm2_iowrite(u8 reg, u8 value); extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, +extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); #define ADT7475_read_byte(address) \ @@ -332,10 +329,10 @@ /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", +#if (CONFIG_GFXUMA == 1) + printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", uma_memory_start, uma_memory_size); - lb_add_memory_range(mem, LB_MEM_RESERVED, + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_start, uma_memory_size); #endif }

1 0

r3843 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org 24 Dec '08

24 Dec '08

Author: hailfinger Date: 2008-12-24 18:58:44 +0100 (Wed, 24 Dec 2008) New Revision: 3843 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c Log: Fix implicit declarations in the AMD DBM690T target by using the right header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Zheng Bao <Zheng.bao(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c 2008-12-23 18:29:50 UTC (rev 3842) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c 2008-12-24 17:58:44 UTC (rev 3843) @@ -25,6 +25,8 @@ #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include <../southbridge/amd/sb600/sb600.h> /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-23 18:29:50 UTC (rev 3842) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-12-24 17:58:44 UTC (rev 3843) @@ -25,6 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <../southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7461_ADDRESS 0x4C @@ -34,6 +35,8 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, + uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \

1 0

SB600 flashrom hang
by Carl-Daniel Hailfinger 24 Dec '08

24 Dec '08

Hi, on my Asus M2A-VM, latest flashrom hangs while trying to access SB600 SPI. flashrom -V Calibrating delay loop... 365M loops per second, 100 myus = 83 us. OK. No coreboot table found. Found chipset "ATI(AMD) SB600", enabling flash write... SPI base address is at 0x0 OK. Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0x0, id2 0x0, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0x0, id2 0x0, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x0, id2 0x0 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x0, id2 0x0 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0x0, id2 0x0, id1 parity violation Probing for Atmel AT25DF021, 256 KB: sb600_spi_command, cmd=9f, writecnt=0, readcnt=3 --------it hangs here--------------- The mainboard does not have a SPI chip. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 6

Flashrom live CD
by George M. Garner Jr. 24 Dec '08

24 Dec '08

This page refers to a FlashROM Live CD. http://www.coreboot.org/Flashrom_Live_CD. Is there an ISO that can be downloaded or is this something that I have to build myself? Some of the content on the page seems to suggest that there is a pre-packaged ISO. But I don't see a link. Thanks, George.

2 1

r1087 - in coreboot-v3: arch/x86/via mainboard/jetway mainboard/jetway/j7f2 northbridge/via/cn700 southbridge/via/vt8237
by svn＠coreboot.org 24 Dec '08

24 Dec '08

Author: cozzie Date: 2008-12-24 00:44:39 +0100 (Wed, 24 Dec 2008) New Revision: 1087 Modified: coreboot-v3/arch/x86/via/c7.c coreboot-v3/mainboard/jetway/Kconfig coreboot-v3/mainboard/jetway/j7f2/dts coreboot-v3/northbridge/via/cn700/cn700.h coreboot-v3/northbridge/via/cn700/initram.c coreboot-v3/northbridge/via/cn700/pci_domain.c coreboot-v3/northbridge/via/cn700/stage1.c coreboot-v3/southbridge/via/vt8237/Makefile coreboot-v3/southbridge/via/vt8237/lpc.c coreboot-v3/southbridge/via/vt8237/stage1.c coreboot-v3/southbridge/via/vt8237/vt8237.c Log: This patch fixes a few small problems and gets cn700 to read from an IDE disk and attempt to boot a linux kernel. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: coreboot-v3/arch/x86/via/c7.c =================================================================== --- coreboot-v3/arch/x86/via/c7.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/arch/x86/via/c7.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -89,7 +89,7 @@ (int)((msr.lo >> 8) & 0xff), (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff)); - printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo); + printk(BIOS_DEBUG, " msr.lo = %x, msr.hi = %x\n", msr.lo, msr.hi); /* Wait while CPU is busy */ cnt = 0; @@ -109,7 +109,7 @@ new = current; switch (model) { case 10: // model A - for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { + for (i = 0; i <= ARRAY_SIZE(c7a_speed_translation); i += 2) { if ((c7a_speed_translation[i] == current) && ((c7a_speed_translation[i + 1] & 0xff00) == (msr.hi & 0xff00))) { @@ -118,7 +118,7 @@ } break; case 13: // model D - for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { + for (i = 0; i <= ARRAY_SIZE(c7d_speed_translation); i += 2) { if ((c7d_speed_translation[i] == current) && ((c7d_speed_translation[i + 1] & 0xff00) == (msr.hi & 0xff00))) { @@ -203,8 +203,8 @@ /* Set up Memory Type Range Registers */ //these don't exist yet - //x86_setup_mtrrs(36); - //x86_mtrr_check(); + x86_setup_mtrrs(36); + x86_mtrr_check(); /* Enable the local cpu apics */ //setup_lapic(); Modified: coreboot-v3/mainboard/jetway/Kconfig =================================================================== --- coreboot-v3/mainboard/jetway/Kconfig 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/mainboard/jetway/Kconfig 2008-12-23 23:44:39 UTC (rev 1087) @@ -28,6 +28,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237 select SUPERIO_FINTEK_F71805F + select PIRQ_TABLE help Jetway J7F2-Series board. endchoice Modified: coreboot-v3/mainboard/jetway/j7f2/dts =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-23 23:44:39 UTC (rev 1087) @@ -43,8 +43,8 @@ /{ mainboard_vendor = "Jetway"; mainboard_name = "J7F2"; - mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */ - mainboard_pci_subsystem_device = "0xbeef"; /* TODO */ + subsystem_vendor = "0xdead"; /* TODO */ + subsystem_device = "0xbeef"; /* TODO */ cpus { /config/("arch/x86/via/c7.dts"); }; @@ -66,23 +66,33 @@ /* How do I represent the bus and pci devices hanging here? */ pci@1,0 { /config/("northbridge/via/cn700/pci.dts"); - pci@0,1 { + pci@0,0 { /config/("northbridge/via/cn700/vga.dts"); }; }; - pci@f,0 {}; - pci@10,0 { + pci@f,0 { /config/("southbridge/via/vt8237/sata.dts"); }; - pci@10,1 { + pci@f,1 { /config/("southbridge/via/vt8237/ide.dts"); + ide0_enable = "1"; + ide1_enable = "0"; + ide0_80pin_cable = "1"; + ide1_80pin_cable = "0"; }; + pci@10,0 { }; + pci@10,1 { }; + pci@10,2 { }; + pci@10,3 { }; + pci@10,4 { }; pci@11,0 { /config/("southbridge/via/vt8237/lpc.dts"); + ioport@4e { + /config/("superio/fintek/f71805f/dts"); + com2enable = "1"; + }; }; - ioport@4e { - /config/("superio/fintek/f71805f/dts"); - com2enable = "1"; - }; + pci@11,5 { }; + pci@12,0 { }; }; }; Modified: coreboot-v3/northbridge/via/cn700/cn700.h =================================================================== --- coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-23 23:44:39 UTC (rev 1087) @@ -34,12 +34,12 @@ void ddr2_sdram_enable(struct board_info *); /* VGA stuff */ -#define SR_INDEX 0x3c4 -#define SR_DATA 0x3c5 -#define CRTM_INDEX 0x3b4 -#define CRTM_DATA 0x3b5 -#define CRTC_INDEX 0x3d4 -#define CRTC_DATA 0x3d5 +#define SR_INDEX 0x3c4 +#define SR_DATA 0x3c5 +#define CRTM_INDEX 0x3b4 +#define CRTM_DATA 0x3b5 +#define CRTC_INDEX 0x3d4 +#define CRTC_DATA 0x3d5 /* Memory Controller Registers */ #define RANK0_END 0x40 Modified: coreboot-v3/northbridge/via/cn700/initram.c =================================================================== --- coreboot-v3/northbridge/via/cn700/initram.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/initram.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -232,11 +232,11 @@ * TODO: #if and option in Kconfig */ /* Set WR=5 and RFC */ - //pci_conf1_write_config8(dev->d0f3, 0x61, 0x94); + pci_conf1_write_config8(dev->d0f3, 0x61, 0x94); /* Set CAS=5 */ - //pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a); - //pci_conf1_write_config8(dev->d0f3, 0x63, 0x00); - //pci_conf1_write_config8(dev->d0f3, 0x64, 0x88); + pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a); + pci_conf1_write_config8(dev->d0f3, 0x63, 0x00); + pci_conf1_write_config8(dev->d0f3, 0x64, 0x88); /* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for BL=4) */ pci_conf1_write_config8(dev->d0f3, 0x6c, 0xc8); @@ -404,7 +404,7 @@ spd_data = check_timing(spd_data, 5, 20); reg8 = pci_conf1_read_config8(dev->d0f3, 0x62); - if ((spd_data - 10) > (reg8 >> 4)) + if ((spd_data - 5) > (reg8 >> 4)) { reg8 &= 0x0f; reg8 |= ((spd_data -10) << 4); Modified: coreboot-v3/northbridge/via/cn700/pci_domain.c =================================================================== --- coreboot-v3/northbridge/via/cn700/pci_domain.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/pci_domain.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -86,8 +86,8 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); - + /* * Once the register value is not zero, the RAM size is * this register's value multiply 64 * 1024 * 1024. @@ -108,11 +108,12 @@ } /* Report the memory regions. */ idx = 10; - /* TODO: Hole needed? */ - ram_resource(dev, idx++, 0, 640); /* First 640k */ + + ram_resource(dev, idx++, 0, 640); /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ - ram_resource(dev, idx++, 768, - (tolmk - 768 - (CONFIG_CN700_VIDEO_MB * 1024))); + /* TODO: shadow ram needs to be controlled via dts */ + ram_resource(dev, idx++, 1024, + (tolmk - 1024 - (CONFIG_CN700_VIDEO_MB * 1024))); phase4_assign_resources(&dev->link[0]); } @@ -129,5 +130,3 @@ .phase6_init = 0, .ops_pci_bus = &pci_cf8_conf1, }; - - Modified: coreboot-v3/northbridge/via/cn700/stage1.c =================================================================== --- coreboot-v3/northbridge/via/cn700/stage1.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/stage1.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -24,59 +24,6 @@ #include <config.h> #include "cn700.h" -static void enable_shadow_ram(void) -{ - u8 shadowreg; - - printk(BIOS_DEBUG, "Enabling shadow ram\n"); - /* Enable shadow ram as normal dram */ - /* 0xc0000-0xcffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); - /* 0xd0000-0xdffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); - /* 0xe0000-0xeffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); - - /* 0xf0000-0xfffff */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); - - /* Do it again for the vlink controller */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); -} - -static void enable_vlink(void) -{ - printk(BIOS_DEBUG, "Enabling Via V-Link\n"); - - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); - //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); - - /* This has to be done last, I think */ - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); -} - /** * Configure the bus between the cpu and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers @@ -92,6 +39,7 @@ static void c7_cpu_setup(void) { u32 dev = PCI_BDF(0, 0, 2); + u8 reg8; /* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ @@ -114,6 +62,13 @@ * 110/111 : Reserved * bits 4:0: Reserved */ + + reg8 = pci_conf1_read_config8(dev, 0x57); + reg8 &= (0x7 << 5); + //reg8 |= (0x4 << 5); + reg8 |= (0x3 << 5); + pci_conf1_write_config8(dev, 0x57, reg8); + /* CPU Miscellaneous Control */ pci_conf1_write_config8(dev, 0x59, 0x44); /* Write Policy */ @@ -179,7 +134,5 @@ pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1); pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1); - enable_shadow_ram(); - enable_vlink(); c7_cpu_setup(); } Modified: coreboot-v3/southbridge/via/vt8237/Makefile =================================================================== --- coreboot-v3/southbridge/via/vt8237/Makefile 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/Makefile 2008-12-23 23:44:39 UTC (rev 1087) @@ -25,4 +25,9 @@ $(src)/southbridge/via/vt8237/ide.c \ $(src)/southbridge/via/vt8237/sata.c +ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/irq_tables.c endif + + +endif Modified: coreboot-v3/southbridge/via/vt8237/lpc.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -230,44 +230,34 @@ { u8 enables, byte; + /* Enable the RTC. */ + byte = pci_read_config8(dev, 0x51); + byte |= (1 << 3); + pci_write_config8(dev, 0x51, byte); + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; pci_write_config8(dev, PCI_COMMAND, byte); /* Enable the internal I/O decode. */ - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); + byte = pci_read_config8(dev, 0x6C); + byte |= 0x80; + pci_write_config8(dev, 0x6C, byte); /* - * ROM decode - * bit range - * 7 000E0000h-000EFFFFh - * 6 FFF00000h-FFF7FFFFh - * 5 FFE80000h-FFEFFFFFh - * 4 FFE00000h-FFE7FFFFh - * 3 FFD80000h-FFDFFFFFh - * 2 FFD00000h-FFD7FFFFh - * 1 FFC80000h-FFCFFFFFh - * 0 FFC00000h-FFC7FFFFh - * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. - */ - pci_write_config8(dev, 0x41, 0x7f); - - /* * Set bit 6 of 0x40 (I/O recovery time). * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so * that PCI interrupts can be properly marked as level triggered. */ - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); + byte = pci_read_config8(dev, 0x40); + byte |= 0x44; + pci_write_config8(dev, 0x40, byte); /* Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf8; - pci_write_config8(dev, 0x42, enables); + byte = pci_read_config8(dev, 0x42); + byte |= 0xf8; + pci_write_config8(dev, 0x42, byte); /* Delay transaction control */ pci_write_config8(dev, 0x43, 0xb); @@ -294,16 +284,14 @@ /* Enable serial IRQ, 6PCI clocks. */ pci_write_config8(dev, 0x52, 0x9); - /* Power management setup */ + /* Power Management setup. */ setup_pm(dev); - /* Enable the RTC. */ - enables = pci_read_config8(dev, 0x51); - enables |= (1 << 3); - pci_write_config8(dev, 0x51, enables); - /* Start the RTC. */ rtc_init(0); + + /* Initialize ISA DMA. */ + isa_dma_init(); } static void vt8237_read_resources(struct device *dev) @@ -314,6 +302,8 @@ struct resource *res; pci_dev_read_resources(dev); + +#ifdef VT8237_APIC_FIXED /* Fixed APIC resource */ res = new_resource(dev, 0x44); /* Possible breakage */ @@ -324,6 +314,7 @@ res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif } /** @@ -342,10 +333,10 @@ struct southbridge_via_vt8237_lpc_config *sb = (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration; - u8 regval; - if (sb->enable_keyboard) { + u8 regval; + /* Enable PS/2 mouse, Keyboard, and KBC Config */ regval = pci_read_config8(dev, 0x51); regval |= (1 << 2)|(1 << 1)|1; @@ -359,7 +350,7 @@ { vt8237_common_init(dev); pci_routing_fixup(dev); - setup_ioapic(dev); + //setup_ioapic(dev); setup_i8259(); init_keyboard(dev); } @@ -448,7 +439,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = vt8237r_init, + //.phase3_chip_setup_dev = vt8237r_init, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, Modified: coreboot-v3/southbridge/via/vt8237/stage1.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -155,8 +155,9 @@ */ void enable_smbus(u16 smbus_io_base) { - u32 dev; + u32 dev = PCI_BDF(0, 17, 0); +#if 0 /* Power management controller */ pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, &dev); @@ -178,6 +179,7 @@ printk(BIOS_DEBUG, "VT8237R Power management controller found " "at 0x%x\n", dev); } +#endif /* 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp @@ -201,37 +203,15 @@ inb(smbus_io_base + SMBHSTCTL); } -/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it - * as early as possible. Move back to stage2 later */ -static void sata_stage1(void) -{ - u32 dev; - u8 reg; - - pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev); - - printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); - - /* Class IDE Disk */ - reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL); - reg &= 0x7f; /* Sub Class Write Protect off */ - pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); - - /* Change the device class to SATA from RAID. */ - pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1); - reg |= 0x80; /* Sub Class Write Protect on */ - pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); -} - void vt8237_stage1(u16 smbus_io_base) { - u32 dev; - u32 ide_dev; + u32 dev = PCI_BDF(0, 17, 0); + //u32 ide_dev; printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n"); - pci_conf1_find_device(0x1106, 0x3227, &dev); - pci_conf1_find_device(0x1106, 0x0571, &ide_dev); + //pci_conf1_find_device(0x1106, 0x3227, &dev); + //pci_conf1_find_device(0x1106, 0x0571, &ide_dev); /* Disable GP3 timer, or else the system reboots when it runs out. * Datasheets say this is disabled by default, they're wrong. */ @@ -248,12 +228,12 @@ pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97 pci_conf1_write_config8(dev, 0x51, 0x1f); - pci_conf1_write_config8(dev, 0x58, 0x60); - pci_conf1_write_config8(dev, 0x59, 0x80); - pci_conf1_write_config8(dev, 0x5b, 0x08); + //pci_conf1_write_config8(dev, 0x58, 0x60); + //pci_conf1_write_config8(dev, 0x59, 0x80); + //pci_conf1_write_config8(dev, 0x5b, 0x08); /* Make it respond to IO space */ - pci_conf1_write_config8(ide_dev, 0x04, 0x07); + //pci_conf1_write_config8(ide_dev, 0x04, 0x07); /* Compatibility mode addresses */ //pci_conf1_write_config32(ide_dev, 0x10, 0); @@ -264,9 +244,9 @@ /* Native mode base address */ //pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1); - pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3 - pci_conf1_write_config8(ide_dev, 0x41, 0xf2); - pci_conf1_write_config8(ide_dev, 0x42, 0x09); + //pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3 + //pci_conf1_write_config8(ide_dev, 0x41, 0xf2); + //pci_conf1_write_config8(ide_dev, 0x42, 0x09); //sata_stage1(); enable_smbus(smbus_io_base); Modified: coreboot-v3/southbridge/via/vt8237/vt8237.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/vt8237.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -38,14 +38,14 @@ const u8 func = dev->path.pci.devfn & 0x7; const u8 device = dev->path.pci.devfn >> 3; const int d16_index[6] = {12, 13, 10, 8, 9, 7}; - + printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n", device, func); if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA) return; - + lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0)); sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8; sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51);

1 0

[PATCH] YABEL: add PMM functionality
by Pattrick Hueper 23 Dec '08

23 Dec '08

Hi, i am trying to reimplement the functionality, that IBM did not opensource of YABEL. This patch adds PMM (POST Memory Manager) functionality Since i dont have a board for coreboot available at the moment, i cannot test this code, it is written to follow the PMM Spec 1.01 I have included a pmm_test function that tests the code, so it should be functional, but i cannot give any guarantees... i just would like to add the code, as long as i still remember the pitfalls i found already. Cheers, Patty Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> --- util/x86emu/Makefile | 1 + util/x86emu/yabel/biosemu.c | 15 ++ util/x86emu/yabel/pmm.c | 384 +++++++++++++++++++++++++++++++++++++++++++ util/x86emu/yabel/pmm.h | 39 +++++ 4 files changed, 439 insertions(+), 0 deletions(-) create mode 100644 util/x86emu/yabel/pmm.c create mode 100644 util/x86emu/yabel/pmm.h diff --git a/util/x86emu/Makefile b/util/x86emu/Makefile index b50b3b4..02f9f98 100644 --- a/util/x86emu/Makefile +++ b/util/x86emu/Makefile @@ -29,6 +29,7 @@ ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_YABEL),y) BIOSEMU_SRC = biosemu.c debug.c device.c mem.c io.c interrupt.c #TODO: add vbe.c, currently not needed... #BIOSEMU_SRC +=vbe.c +BIOSEMU_SRC +=pmm.c #PH: TODO: remove the compat files?? BIOSEMU_SRC += compat/functions.c X86EMU_INCLUDE += -I $(src)/util/x86emu/yabel diff --git a/util/x86emu/yabel/biosemu.c b/util/x86emu/yabel/biosemu.c index cc11c0f..ebeb9af 100644 --- a/util/x86emu/yabel/biosemu.c +++ b/util/x86emu/yabel/biosemu.c @@ -26,6 +26,7 @@ #include "mem.h" #include "interrupt.h" #include "device.h" +#include "pmm.h" #include <rtas.h> @@ -209,6 +210,20 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad X86EMU_setupPioFuncs(&my_pio_funcs); X86EMU_setupMemFuncs(&my_mem_funcs); + //setup PMM struct in BIOS_DATA_SEGMENT, offset 0x0 + u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + if (pmm_length <= 0) { + printf ("\nYABEL: Warning: PMM Area could not be setup. PMM not available (%x)\n", + pmm_length); + return 0; + } else { + CHECK_DBG(DEBUG_PMM) { + /* test the PMM */ + pmm_test(); + /* and clean it again by calling pmm_setup... */ + pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + } + } // setup the CPU M.x86.R_AH = bios_device.bus; M.x86.R_AL = bios_device.devfn; diff --git a/util/x86emu/yabel/pmm.c b/util/x86emu/yabel/pmm.c new file mode 100644 index 0000000..771482e --- /dev/null +++ b/util/x86emu/yabel/pmm.c @@ -0,0 +1,384 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ + +#include <x86emu/x86emu.h> +#include <x86emu/prim_ops.h> +#include <string.h> + +#include "biosemu.h" +#include "pmm.h" +#include "debug.h" +#include "device.h" + + +/* this struct is used to remember which PMM spaces + * have been assigned. MAX_PMM_AREAS defines how many + * PMM areas we can assign. + * All areas are assigned in PMM_CONV_SEGMENT + */ +typedef struct { + u32 handle; /* handle that is returned to PMM caller */ + u32 offset; /* in PMM_CONV_SEGMENT */ + u32 length; /* length of this area */ +} pmm_allocation_t; + +#define MAX_PMM_AREAS 10 + +/* array to store the above structs */ +static pmm_allocation_t pmm_allocation_array[MAX_PMM_AREAS]; + +/* index into pmm_allocation_array */ +static u32 curr_pmm_allocation_index = 0; + +/* This function is used to setup the PMM struct in virtual memory + * at a certain offset, the length of the PMM struct is returned */ +u8 +pmm_setup(u16 segment, u16 offset) +{ + /* setup the PMM structure */ + pmm_information_t *pis = (pmm_information_t *) (M.mem_base + (((u32) segment) << 4) + offset); + memset(pis, 0, sizeof(pmm_information_t)); + /* set signature to $PMM */ + pis->signature[0] = '$'; + pis->signature[1] = 'P'; + pis->signature[2] = 'M'; + pis->signature[3] = 'M'; + /* revision as specified */ + pis->struct_rev = 0x01; + /* internal length, excluding code */ + pis->length = ((void *) &(pis->code) - (void *) &(pis->signature)); + /* the code to be executed, pointed to by entry_point_offset */ + pis->code[0] = 0xCD; /* INT */ + pis->code[1] = PMM_INT_NUM; /* my selfdefined PMM INT number */ + pis->code[2] = 0xCB; /* RETF */ + /* set the entry_point_offset, it should point to pis->code, segment is the segment of + * this struct. Since pis->length is the length of the struct excluding code, offset+pis->length + * points to the code... it's that simple ;-) + */ + out32le(&(pis->entry_point_offset), (u32) segment << 16 | (u32) (offset + pis->length)); + /* checksum calculation */ + u8 i; + u8 checksum = 0; + for (i = 0; i < pis->length; i++) { + checksum += *(((u8 *) pis) + i); + } + pis->checksum = ((u8) 0) - checksum; + CHECK_DBG(DEBUG_PMM) { + DEBUG_PRINTF_PMM("PMM Structure:\n"); + dump((void *) pis, sizeof(pmm_information_t)); + } + return sizeof(pmm_information_t); +} + +/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point + * is executed, it must handle all PMM requests + */ +void +pmm_handleInt() +{ + u32 rval = 0; + u16 function, flags; + u32 handle, length; + u32 i, j; + u32 buffer; + /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * according to the PMM Spec "the flags and all registers, except DX and AX + * are preserved across calls to PMM" + * so we save M.x86 and in :exit label we restore it, however, this means that no + * returns must be used in this function, any exit must use goto exit! + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + */ + X86EMU_regs backup_regs = M.x86; + pop_long(); /* pop the return address, this is already saved in INT handler, we don't need + to remember this. */ + function = pop_word(); + switch (function) { + case 0: + /* function pmmAllocate */ + length = pop_long(); + length *= 16; /* length is passed in "paragraphs" of 16 bytes each */ + handle = pop_long(); + flags = pop_word(); + DEBUG_PRINTF_PMM("%s: pmmAllocate: Length: %x, Handle: %x, Flags: %x\n", __FUNCTION__, length, handle, flags); + if ((flags & 0x1) != 0) { + /* request to allocate in conventional memory */ + if (curr_pmm_allocation_index >= MAX_PMM_AREAS) { + printf("%s: pmmAllocate: Maximum Number of allocatable areas reached (%d), cannot allocate more memory!\n", + __FUNCTION__, MAX_PMM_AREAS); + rval = 0; + goto exit; + } + /* some ROMs seem to be confused by offset 0, so lets start at 0x100 */ + u32 next_offset = 0x100; + pmm_allocation_t *pmm_alloc = &(pmm_allocation_array[curr_pmm_allocation_index]); + if (curr_pmm_allocation_index != 0) { + /* we have already allocated... get the new next_offset + * from the previous pmm_allocation_t */ + next_offset = pmm_allocation_array[curr_pmm_allocation_index - 1].offset + + pmm_allocation_array[curr_pmm_allocation_index - 1].length; + } + DEBUG_PRINTF_PMM("%s: next_offset: 0x%x\n", __FUNCTION__, next_offset); + if (length == 0) { + /* largest possible block size requested, we have on segment + * to allocate, so largest possible is segment size (0xFFFF) + * minus next_offset + */ + rval = 0xFFFF - next_offset; + goto exit; + } + u32 align = 0; + if (((flags & 0x4) != 0) && (length > 0)) { + /* align to least significant bit set in length param */ + u8 lsb = 0; + while (((length >> lsb) & 0x1) == 0) { + lsb++; + } + align = 1 << lsb; + } + /* always align at least to paragraph (16byte) boundary + * hm... since the length is always in paragraphs, we cannot + * align outside of paragraphs anyway... so this check might + * be unnecessary...*/ + if (align < 0x10) { + align = 0x10; + } + DEBUG_PRINTF_PMM("%s: align: 0x%x\n", __FUNCTION__, align); + if ((next_offset & (align - 1)) != 0) { + /* not yet aligned... align! */ + next_offset += align; + next_offset &= ~(align - 1); + } + if ((next_offset + length) > 0xFFFF) { + rval = 0; + printf("%s: pmmAllocate: Not enough memory available for allocation!\n", __FUNCTION__); + goto exit; + } + curr_pmm_allocation_index++; + /* remember the values in pmm_allocation_array */ + pmm_alloc->handle = handle; + pmm_alloc->offset = next_offset; + pmm_alloc->length = length; + /* return the 32bit "physical" address, i.e. combination of segment and offset */ + rval = ((u32) (PMM_CONV_SEGMENT << 16)) | next_offset; + DEBUG_PRINTF_PMM("%s: pmmAllocate: allocated memory at %x\n", __FUNCTION__, rval); + } else { + rval = 0; + printf("%s: pmmAllocate: allocation in extended memory not supported!\n", __FUNCTION__); + } + goto exit; + case 1: + /* function pmmFind */ + handle = pop_long(); /* the handle to lookup */ + DEBUG_PRINTF_PMM("%s: pmmFind: Handle: %x\n", __FUNCTION__, handle); + i = 0; + for (i = 0; i < curr_pmm_allocation_index; i++) { + if (pmm_allocation_array[i].handle == handle) { + DEBUG_PRINTF_PMM("%s: pmmFind: found allocated memory at %x\n", __FUNCTION__, rval); + /* return the 32bit "physical" address, i.e. combination of segment and offset */ + rval = ((u32) (PMM_CONV_SEGMENT << 16)) | pmm_allocation_array[i].offset; + } + } + if (rval == 0) { + DEBUG_PRINTF_PMM("%s: pmmFind: handle (%x) not found!\n", __FUNCTION__, handle); + } + goto exit; + case 2: + /* function pmmDeallocate */ + buffer = pop_long(); + /* since argument is the address of the PMM block (including the segment, + * we need to remove the segment to get the offset + */ + buffer = buffer ^ ((u32) PMM_CONV_SEGMENT << 16); + DEBUG_PRINTF_PMM("%s: pmmDeallocate: PMM segment offset: %x\n", __FUNCTION__, buffer); + i = 0; + /* rval = 0 means we deallocated the buffer, so set it to 1 in case we dont find it and + * thus cannot deallocate + */ + rval = 1; + for (i = 0; i < curr_pmm_allocation_index; i++) { + DEBUG_PRINTF_PMM("%d: %x\n", i, pmm_allocation_array[i].handle); + if (pmm_allocation_array[i].offset == buffer) { + /* we found the requested buffer, rval = 0 */ + rval = 0; + DEBUG_PRINTF_PMM("%s: pmmDeallocate: found allocated memory at index: %d\n", __FUNCTION__, i); + /* copy the remaining elements in pmm_allocation_array one position up */ + j = i; + for (; j < curr_pmm_allocation_index; j++) { + pmm_allocation_array[j] = pmm_allocation_array[j + 1]; + } + /* move curr_pmm_allocation_index one up, too */ + curr_pmm_allocation_index--; + /* finally clean last element */ + pmm_allocation_array[curr_pmm_allocation_index].handle = 0; + pmm_allocation_array[curr_pmm_allocation_index].offset = 0; + pmm_allocation_array[curr_pmm_allocation_index].length = 0; + break; + } + } + if (rval != 0) { + DEBUG_PRINTF_PMM("%s: pmmDeallocate: offset (%x) not found, cannot deallocate!\n", __FUNCTION__, buffer); + } + goto exit; + default: + /* invalid/unimplemented function */ + printf("%s: invalid PMM function (0x%04x) called!\n", __FUNCTION__, function); + /* PMM spec says if function is invalid, return 0xFFFFFFFF */ + rval = 0xFFFFFFFF; + goto exit; + } + exit: + /* exit handler of this function, restore registers, put return value in DX:AX */ + M.x86 = backup_regs; + M.x86.R_DX = (u16) ((rval >> 16) & 0xFFFF); + M.x86.R_AX = (u16) (rval & 0xFFFF); + CHECK_DBG(DEBUG_PMM) { + DEBUG_PRINTF_PMM("%s: dump of pmm_allocation_array:\n", __FUNCTION__); + for (i = 0; i < MAX_PMM_AREAS; i++) { + DEBUG_PRINTF_PMM("%d:\n\thandle: %x\n\toffset: %x\n\tlength: %x\n", + i, pmm_allocation_array[i].handle, pmm_allocation_array[i].offset, pmm_allocation_array[i].length); + } + } + return; +} + +/* This function tests the pmm_handleInt() function above. */ +void +pmm_test(void) { + u32 handle, length, addr; + u16 function, flags; + /*-------------------- Test simple allocation/find/deallocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 16; /* in 16byte paragraphs, so we allocate 256 bytes... */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: found memory at: %04x:%04x (expected: %08x)\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX, addr); + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + /*-------------------- Test aligned allocation/deallocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 257; /* in 16byte paragraphs, so we allocate 4KB + 16 bytes... */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + function = 0; /* pmmAllocate */ + handle = 0xf00d4b0b; + length = 128; /* in 16byte paragraphs, so we allocate 2KB... */ + flags = 0x5; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + /* the address should be aligned to 0x800, so probably it is at offset 0x1800... */ + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + handle = 0xdeadbeef; + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + /*-------------------- Test out of memory allocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 0; /* length zero means, give me the largest possible block */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + length = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + length /= 16; /* length in paragraphs */ + DEBUG_PRINTF_PMM("%s: largest possible length: %08x\n", __FUNCTION__, length); + function = 0; /* pmmAllocate */ + flags = 0x1; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + function = 0; /* pmmAllocate */ + length = 1; + handle = 0xf00d4b0b; + flags = 0x1; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + /* this should fail, so 0x0 should be returned */ + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x expected: 0000:0000\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + handle = 0xdeadbeef; + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32)M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", __FUNCTION__, M.x86.R_DX, M.x86.R_AX); +} diff --git a/util/x86emu/yabel/pmm.h b/util/x86emu/yabel/pmm.h new file mode 100644 index 0000000..b3d34ad --- /dev/null +++ b/util/x86emu/yabel/pmm.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ + +#ifndef _YABEL_PMM_H_ +#define _YABEL_PMM_H_ + +#include <types.h> + +/* PMM Structure see PMM Spec Version 1.01 Chapter 3.1.1 (search web for specspmm101.pdf) */ +typedef struct { + u8 signature[4]; + u8 struct_rev; + u8 length; + u8 checksum; + u32 entry_point_offset; + u8 reserved[5]; + /* code is not part of the speced PMM struct, however, since i cannot put the + * handling in of PMM in the virtual memory (i dont want to hack it together + * in x86 assembly ;-)) this code array is pointed to by entry_point_offset, + * in code there is only a INT call and a RETF, thus every PMM call will issue + * a PMM INT (only defined in YABEL, see interrupt.c) and the INT Handler + * will do the actual PMM work. + */ + u8 code[3]; +} __attribute__ ((__packed__)) pmm_information_t; + +/* This function is used to setup the PMM struct in virtual memory + * at a certain offset */ +u8 pmm_setup(u16 segment, u16 offset); + +/* This is the INT Handler mentioned above, it will be called by my special PMM INT */ +void pmm_handleInt(void); + +void pmm_test(void); + +#endif // _YABEL_PMM_H -- 1.6.0.4

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coreboot December 2008