coreboot December 2008

coreboot@coreboot.org

77 participants
330 discussions

r3841 - in trunk/coreboot-v2/src/mainboard/asus: a8v-e_se m2v-mx_se
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: ruik Date: 2008-12-23 19:05:24 +0100 (Tue, 23 Dec 2008) New Revision: 3841 Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/dsdt.asl trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl Log: Following patch fixes error code 12 in Windows XP and Vista. The function field of _PRT entry must be always 0xffff (any function). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-By: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/dsdt.asl 2008-12-23 17:34:15 UTC (rev 3840) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/dsdt.asl 2008-12-23 18:05:24 UTC (rev 3841) @@ -63,8 +63,8 @@ Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, - Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ - Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2008-12-23 17:34:15 UTC (rev 3840) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2008-12-23 18:05:24 UTC (rev 3841) @@ -90,8 +90,8 @@ /* PCI Routing Table */ Name (_PRT, Package () { - Package (0x04) { 0x000F0000, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */ - Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },

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r3840 - in trunk/coreboot-v2/src: arch/i386/include/arch include mainboard/asus/m2v-mx_se
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: ruik Date: 2008-12-23 18:34:15 +0100 (Tue, 23 Dec 2008) New Revision: 3840 Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/include/stdlib.h trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/fadt.c Log: The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2008-12-23 17:34:15 UTC (rev 3840) @@ -285,7 +285,7 @@ u32 x_firmware_waking_vector_l; u32 x_firmware_waking_vector_h; u8 version; - u8 resv[33]; + u8 resv[31]; } __attribute__ ((packed)) acpi_facs_t; /* These are implemented by the target port */ Modified: trunk/coreboot-v2/src/include/stdlib.h =================================================================== --- trunk/coreboot-v2/src/include/stdlib.h 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/include/stdlib.h 2008-12-23 17:34:15 UTC (rev 3840) @@ -5,6 +5,9 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c 2008-12-23 17:34:15 UTC (rev 3840) @@ -6,7 +6,7 @@ * * Copyright (C) 2004 Stefan Reinauer <stepan(a)openbios.org> * Copyright (C) 2005 Nick Barker <nick.barker9(a)btinternet.com> - * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License v2 as published by @@ -32,6 +32,7 @@ #include <../../../southbridge/via/k8t890/k8t890.h> extern unsigned char AmlCode[]; +extern unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) { @@ -91,6 +92,8 @@ acpi_madt_t *madt; acpi_fadt_t *fadt; acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ @@ -113,6 +116,10 @@ /* We explicitly add these tables later on: */ printk_debug("ACPI: * FACS\n"); + + /* we should align FACS to 64B as per ACPI specs */ + + current = ALIGN(current, 64); facs = (acpi_facs_t *) current; current += sizeof(acpi_facs_t); acpi_create_facs(facs); @@ -158,6 +165,24 @@ current += srat->header.length; acpi_add_table(rsdt, srat); + /* SLIT */ + printk_debug("ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdt,slit); + + /* SSDT */ + printk_debug("ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode_ssdt)->length; + memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length); + update_ssdt((void*)ssdt); + /* recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + acpi_add_table(rsdt,ssdt); + printk_info("ACPI: done.\n"); return current; } Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-12-23 17:34:15 UTC (rev 3840) @@ -299,7 +299,6 @@ enable_fid_change(); print_debug("after enable_fid_change\r\n"); - /* FIXME does not work yet */ init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/dsdt.asl 2008-12-23 17:34:15 UTC (rev 3840) @@ -22,6 +22,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { + Include ("amdk8_util.asl") + + /* Define the main processor.*/ Scope (\_PR) { @@ -47,9 +50,45 @@ Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + /* PCI Routing Table */ - /* aaa */ Name (_PRT, Package () { Package (0x04) { 0x000F0000, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */ Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/fadt.c 2008-12-23 17:20:46 UTC (rev 3839) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/fadt.c 2008-12-23 17:34:15 UTC (rev 3840) @@ -75,10 +75,10 @@ fadt->day_alrm = 0x7d; fadt->mon_alrm = 0x7e; fadt->century = 0x32; - /* fixme 5 - 10 */ - fadt->iapc_boot_arch = 0x1; + /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ + fadt->iapc_boot_arch = 0xb; /* fixme */ - fadt->flags = 0x4a5; + fadt->flags = 0xa5; fadt->reset_reg.space_id = 0; fadt->reset_reg.bit_width = 0;

1 0

RS690 HT init
by Carl-Daniel Hailfinger 23 Dec '08

23 Dec '08

Hi, it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional? The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit(). /***************************************** * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ static void rs690_htinit() { /* * About HT, it has been done in enumerate_ht_chain(). */ device_t k8_f0; u32 reg; u8 k8_ht_freq; k8_f0 = PCI_DEV(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz * 0100b = 600Mhz * 0101b = 800Mhz * 0110b = 1Ghz * 1111b = 1Ghz ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); } As you can see, we only read the K8 HT speed. I have created a patch which tests if the K8 HT speed is 1 GHz and sets NB_CFG_Q_F1000_800 bit 0 in that case. But this can fail if the processor has more than one HT link. My idea was to look at RS690 HT link configuration instead because it has only one HT link. There is another problem because rs690_htinit() is called before optimize_link_incoherent_ht(). The new link speed is only known after optimize_link_incoherent_ht(). Calling rs690_htinit() too early has no effect. I call rs690_htinit() again after optimize_link_incoherent_ht(). What do you think? Regards, Carl-Daniel Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -175,8 +175,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq; k8_f0 = PCI_DEV(0, 0x18, 0); @@ -196,6 +197,16 @@ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + if ((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) { + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_info("rs690_ht_init NB_CFG_Q_F1000_800=%x\n", reg8); + if (!(reg8 & 0x1)) { + printk_info("rs690_ht_init setting bit 0 in NB_CFG_Q_F1000_800 to allow 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } + } } /******************************************************* Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); -- http://www.hailfinger.org/

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r3839 - in trunk/coreboot-v2/src: mainboard/amd/dbm690t mainboard/amd/pistachio southbridge/amd/rs690
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: hailfinger Date: 2008-12-23 18:20:46 +0100 (Tue, 23 Dec 2008) New Revision: 3839 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c Log: Handle RS690 quirks for 1 GHz noncoherent HyperTransport. The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Bao, Zheng says: As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. This patch has been tested on dbm690t which HT link works on 800Mhz. Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2008-12-23 17:16:11 UTC (rev 3838) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2008-12-23 17:20:46 UTC (rev 3839) @@ -210,6 +210,7 @@ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2008-12-23 17:16:11 UTC (rev 3838) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2008-12-23 17:20:46 UTC (rev 3839) @@ -213,6 +213,7 @@ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); post_code(0x06); Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c 2008-12-23 17:16:11 UTC (rev 3838) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c 2008-12-23 17:20:46 UTC (rev 3839) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -175,8 +176,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq; k8_f0 = PCI_DEV(0, 0x18, 0); @@ -195,7 +197,22 @@ ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); + /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set. + * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set. + */ + if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) { + printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) { + printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); + reg8 &= ~0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } } /******************************************************* @@ -462,7 +479,6 @@ break; } - rs690_htinit(); k8_optimization(); rs690_por_init(nb_dev); }

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Re: [coreboot] [RFC] Error out on implicit declarations
by Carl-Daniel Hailfinger 23 Dec '08

23 Dec '08

On 23.12.2008 08:57, Bao, Zheng wrote: > Acked-by: Zheng Bao <Zheng.bao(a)amd.com> > Thanks, committed in r3878. Regards, Carl-Daniel > > -----Original Message----- > From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] > Sent: Tuesday, December 23, 2008 10:50 AM > To: Bao, Zheng > Cc: coreboot(a)coreboot.org > Subject: Re: [coreboot] [RFC] Error out on implicit declarations > > Hi Zheng, > > I have found a shorter way to fix the power_limit_encoding warnings. > What do you think? > > Regards, > Carl-Daniel > > Remove a unneccessary typedef from acpi_tables.c in the AMD Pistachio > and DBM690T targets. > > Signed-off-by: Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> > -- http://www.hailfinger.org/

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r3838 - in trunk/coreboot-v2/src/mainboard/amd: dbm690t pistachio
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: hailfinger Date: 2008-12-23 18:16:11 +0100 (Tue, 23 Dec 2008) New Revision: 3838 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c Log: Remove a unneccessary typedef from acpi_tables.c in the AMD Pistachio and DBM690T targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Zheng Bao <Zheng.bao(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2008-12-23 02:22:07 UTC (rev 3837) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2008-12-23 17:16:11 UTC (rev 3838) @@ -133,7 +133,7 @@ u32 *v; struct cpuid_result cpuid1; - typedef struct power_limit_encoding { + struct power_limit_encoding { u8 socket_type; u8 cmp_cap; u8 pwr_lmt; Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2008-12-23 02:22:07 UTC (rev 3837) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2008-12-23 17:16:11 UTC (rev 3838) @@ -133,7 +133,7 @@ u32 *v; struct cpuid_result cpuid1; - typedef struct power_limit_encoding { + struct power_limit_encoding { u8 socket_type; u8 cmp_cap; u8 pwr_lmt;

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Question about support: MSI K8N Neo V2.0 (MS-7030 V2.X)
by Sascha 'saigkill' Manns 23 Dec '08

23 Dec '08

Hello List, i'm new in this List. Coreboot is an very interesting Project. Yesterday i've searched in your Support List for my Board. But i've not found anything. This means, that the Board is not supported? Has anyone experience with this board? Greetings Sascha -- Sincereley yours Sascha Manns openSUSE Marketing Team (Weekly News) openSUSE Build Service Web: http://saschamanns.gulli.to Blog: http://lizards.opensuse.org/author/saigkill

3 4

VX 800 board with socket BIOS and VIA Nano
by Rudolf Marek 23 Dec '08

23 Dec '08

Hi all, Quite a new board: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=581&proname=NF77-N1… 1. VIA VX800 Chipset 2. Support VIA® Nano L2200 (65nm,FSB 800MHz,1.6GHz) processor 3. Integrated Chrome9 HC3 DX9 IGP 4. Integrated LVDS support 24-bit TFT LCD 5. Support 1 x 32-bit PCI slot 6. Support 2 x Serial ATA 2 Devices 7. Windows Vista Ready 8. Onboard Gigabit LAN 9. Support DC Fan 10. VIA VT1708B HD Audio Codec with 6-Channel 11. 170 x 170mm Mini-ITX Form Factor Seems to have socket BIOS, serial port and Fintek SIO. http://www.jetway.com.tw/jw/product_picture.asp?proid=581&proname=NF77-N1G6… Price is 17 000 ¥, thats 3 500 CZK and thats 3500/25 = 140 EUR Rudolf

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r1084 - coreboot-v3/arch/x86/intel/core2
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: rminnich Date: 2008-12-23 08:09:46 +0100 (Tue, 23 Dec 2008) New Revision: 1084 Modified: coreboot-v3/arch/x86/intel/core2/stage1.c Log: This is an emergency fix for the kontron. This fix now allows us to boot to etherboot. The fix is to replace the wbinvd with an invd. The wbinvd is a bad idea, since the cache at this point is full of tags to a location that is not backed by memory. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/intel/core2/stage1.c =================================================================== --- coreboot-v3/arch/x86/intel/core2/stage1.c 2008-12-23 06:59:04 UTC (rev 1083) +++ coreboot-v3/arch/x86/intel/core2/stage1.c 2008-12-23 07:09:46 UTC (rev 1084) @@ -82,7 +82,7 @@ " andl $0x9fffffff,%%eax \n" " movl %%eax, %%cr0 \n" - " wbinvd \n" + " invd \n" " call stage1_phase3 \n" :: [newesp] "i" (newlocation),

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r1083 - coreboot-v3/mainboard/kontron/986lcd-m
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: rminnich Date: 2008-12-23 07:59:04 +0100 (Tue, 23 Dec 2008) New Revision: 1083 Modified: coreboot-v3/mainboard/kontron/986lcd-m/initram.c Log: Quick emergency fix for unitialized variable. A number of recent changes have resulted in breaking the kontron port. I am trying to fix them. In case there is any concern about the initialization: this is a scalar auto being initialized. The initialization is done in code. I have verified this both by checking the object code and actually running it; this fix resolves a break introduced at some point. Other breakage remains: kontron now hangs here: run_file returns with 0 Done RAM init code Done printk() buffer move disable_car entry disable_car global_vars copy done disable_car global_vars pointer adjusted entering asm code now Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/kontron/986lcd-m/initram.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-12-22 17:36:06 UTC (rev 1082) +++ coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-12-23 06:59:04 UTC (rev 1083) @@ -157,7 +157,7 @@ */ int main(void) { - int boot_mode; + int boot_mode = 0; void i945_early_initialization(void); void enable_smbus(void); int fixup_i945_errata(void);

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coreboot December 2008