coreboot December 2008

coreboot@coreboot.org

77 participants
330 discussions

AML code generator
by Rudolf Marek 28 Dec '08

28 Dec '08

Hello, The Coreboot will need ACPI bytecode (AML) generotor. Right now it uses quite hackish solution. It let the compiler compile the the table, and it has hardcoded binary offsets. Check amdk8_acpi.c. It somehow works, but for ACPI P-states we will need to generate the ACPI objects at runtime. This may be necessary also for C7 and perhaps for Intel too. I wrote some proof of concept of such generator. Now it generates a skelleton for P-states and also some objects for amdk8_acpi.c how to run it: compile source touch test run it iasl -d test Examine test.dsl Works for me ;) Rudolf

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"sphinx" notebook, unknow USI 440bx...
by Andrea Bravetti 28 Dec '08

28 Dec '08

Hi all, I'm new in this list. I have an old notebook and the original BIOS has some nasty limitation (harddisk size, ram type and size, etc...) and I'm seriously interested in finding a solution... This notebook is manufactured by USI, but was sold with the name "SPHINX", and I can't find any information about the motherboard... So, this is what I know about the bios: SystemSoft MobilePRO BIOS, ambiguous version, i don't know, in different place it print different version, 1.30,1.0, 1.1, 1.17... :( Now, let's see what there is inside this notebook: # superiotool -d superiotool r3827 Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0 Register dump: idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 28 94 88 f4 02 10 ff 00 00 00 00 00 00 28 01 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 80 00 fc 00 00 de fe be 21 65 43 00 00 00 00 03 00 00 def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00 # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel PIIX4/4E/4M", enabling flash write... OK. Found chip "SST SST29EE020A" (256 KB) at physical address 0xfffc0000. # lspci 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled) (rev 02) 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00:08.0 VGA compatible controller: Neomagic Corporation NM2160 [MagicGraph 128XD] (rev 01) 00:0a.0 CardBus bridge: O2 Micro, Inc. OZ6836/6860 CardBus Controller (rev 62) 00:0a.1 CardBus bridge: O2 Micro, Inc. OZ6836/6860 CardBus Controller (rev 62) 00:0c.0 Multimedia audio controller: ESS Technology ES1968 Maestro 2 05:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet (rev 10) I know FDC37N769 is unsupported in V2, and there are other problems, but if someone want to help me we can do that. I have a dump of the current BIOS if it can help... bye, Andrea

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[PATCH] SMM handler for K8
by Rudolf Marek 27 Dec '08

27 Dec '08

Hello, This is just a technology demonstrator. Its an implementation of SMM for K8 with VT8237S. It install a SMM handler and it just supports the SMI command interface. Thats all. I'm dumping here whole patch as is to save it for future use. (It worked for me). Rudolf

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Where would I find a listing of completed ports to existing chipsets?
by Gregg Levine 27 Dec '08

27 Dec '08

Hello! I have here a legacy Intel board, it claims to be an i440FX based board, and of course these Dell systems insist they are i440GX and related family members. So my question is, where would I find a listing of completed ports to these existing chipsets? ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature was once found posting rude messages in English in the Moscow subway."

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[PATCH] SeaBIOS - vgahooks improvements
by Rudolf Marek 26 Dec '08

26 Dec '08

Hello all, The K8M890 BIOS needs int 0x15 0x5f18 to write to scratch register for a driver the memory size of framebuffer and also the memory speed. The X.org openchrome driver as well Unichrome driver needs that. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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YABEL and images in LAR files
by Myles Watson 26 Dec '08

26 Dec '08

Patty, For some devices, Coreboot has the ROM image in a section of the ROM. It copies that image to memory and passes a pointer to run_bios. Actually, right now Coreboot copies the ROMs to RAM for devices too. YABEL works when the ROM is accessible from the device (by ignoring the fact that Coreboot already copied it), but not in the case that Coreboot expects it to be run from RAM. Do you have any thoughts on how to handle this case? Thanks, Myles

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Merry Christmas!
by Bao, Zheng 26 Dec '08

26 Dec '08

Just for fun? Does it look like coreboot logo? (`. ,-, `\ `. ,;' / \`. \ ,'/ .' __ `.\ Y /.' .-' ''--.._` ` ( .' / ` , ` ' Q ' , , `._ \ | ' `-.;_' ` ; ` ` --,.._; ` , ) .' `._ , ' /_ ; ,''-,;' ``- ``-..__\``--`

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Yet another idea of an SPI flash chip programmer
by FENG Yu Ning 26 Dec '08

26 Dec '08

There are lots of flash programmer out there, but none of them (those I know about) fits my requirement well. I would like a programmer to be: * able to program SPI flash chips, * not slow (program 512k bytes in 3 mins), * with a driver whose source code is available (or not difficult to write one), * simple, and * cheap. There is one that almost does the job, http://www.malinov.com/Home/sergeys-projects/spi-flash-programmer but [0] would it be very slow? Recently I find a chip FT2232x http://www.ftdichip.com/Products/FT2232C.htm It seems that the chip's IO could be configured to work in bit-bang mode and thus able to implement as an SPI I/F. [1] I think it is easy to build a prototype programmer using this chip. Is it? [2] Is the programmer going to meet my requirement? yu ning

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porting to asus p5q (socket 775) - intel core 2 e8400
by Thomas Prochaska 25 Dec '08

25 Dec '08

hi! since i'm new to this project i don't have any clue about how to start the porting. do you have some todo or list to start similar to the v3 documentation. there it says for instance that first you have to create a few directories and so on. maybe someone can give me a few hints to get started. (i have three bios chips flashed with the newest propietary bios, an rs232 nullmodem cable and the flashrom utility now works for me ;)) regards thomas prochaska my system: o asus p5q http://www.asus.com/products.aspx?modelmenu=2&model=2164&l1=3&l2=11&l3=709&… o intel core 2 e8400 o 4 gb ddr-sdram attached are lspci, lspci -vvv

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Asus P5G-MX(945) + Intel E8200
by blink＠nm.ru 25 Dec '08

25 Dec '08

Hello for all! I'm trying to run coreboot on Asus P5G-MX(945) with Intel E8200 so i ask administrator to add some code to svn 1. coreboot-v2/src/northbridge/intel/i945/udelay.c 47 case 2: fsb = 800; break; case 0: fsb = 1067; break; case 4: fsb = 1333; break; case 6: fsb = 1600; break; 2. coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 87 { X86_VENDOR_INTEL, 0x10676 }, /* Intel E8200 */

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coreboot December 2008