Asus P5G-MX(945) + Intel E8200

Hello for all!

I'm trying to run coreboot on Asus P5G-MX(945) with Intel E8200

so i ask administrator to add some code to svn

1. coreboot-v2/src/northbridge/intel/i945/udelay.c 47

case 2:
                fsb = 800;
                break;
        case 0:
                fsb = 1067;
                break;
        case 4:
                fsb = 1333;
                break;
        case 6:
                fsb = 1600;
                break;

2. coreboot-v2/src/cpu/intel/model_6fx/model_6fx_init.c 87

{ X86_VENDOR_INTEL, 0x10676 }, /* Intel E8200 */

[Peter Stuge]

Hello!

[e-mail] wrote:
> Hello for all!
>
> I'm trying to run coreboot on Asus P5G-MX(945) with Intel E8200

Hm, this board isn't explicitly supported at the moment, but it will
be interesting to hear about your results are. How do you build
coreboot for it?
> so i ask administrator to add some code to svn

Thanks for the contribution!

In the future please send changes in unified diff format and with a
Signed-off-by line as described on

http://www.coreboot.org/Development_Guidelines

Unified diffs are easy to work with and fairly easy to read. The
easiest way to create a unified diff is to checkout from svn, make
changes and then run svn diff in the coreboot-v2 checkout directory.

I've attached a patch with your changes and my signoff, if you send
an acked-by line I'll commit it.

//Peter

Hello, Peter!

1)

v2: with my patches added, I have problem with second CPU
initialization now (see v2log)

I can skip 2nd core initialization but it's wrong.

v3: It's fail on CAR disable stage(asm code) (see v3log)

boot stops on first asm instruction "    movl    
%[newesp], %%esp
  \n"

if first asm instruction is "    call stage1_phase3      
   \n"

boot goes on next stage...

I don't know what's is the problem, mb wrong OS or GCC 
version (I
use Fedora 10)

Ron M. chaged instruction after "    movl    %[newesp], 
%%esp
\n" some days ago, so he hasn't such problem...

2) I'm not sure, but My acked-by line is

/Acked-by: JonB /

// JonB
> Hm, this board isn't explicitly supported at the
>
> moment, but it
> will
>
> be interesting to hear about your results are. How do you 
> build
> coreboot for it?
>  2) Thanks for the contribution!
>
> In the future please send changes in unified diff format 
> and with a
> Signed-off-by line as described on
>
> http://www.coreboot.org/Development_Guidelines
>
> Unified diffs are easy to work with and fairly easy to 
> read. The
> easiest way to create a unified diff is to checkout from 
> svn, make
> changes and then run svn diff in the coreboot-v2 checkout 
> directory.
>
> I've attached a patch with your changes and my signoff, 
> if you send
> an acked-by line I'll commit it.
>
> //Peter --
> coreboot mailing list: [e-mail]
> http://www.coreboot.org/mailman/listinfo/coreboot