coreboot December 2008

coreboot@coreboot.org

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330 discussions

windows XP boots with ACPI HAL
by Rudolf Marek 23 Dec '08

23 Dec '08

Hi all, I had a time and finally Windows XP boots with Coreboot + Seabios. In fact it was a clean install of WXP SP2. All went fine, windows work. I'm attaching two patches. The first (acpi-fixes2) fixes the ACPI related problems. Some of them were identified previously by Kevin. I had just solve right _CRS reporting for PCI0 (as required by windows). This is accomplished with the k8-utils.asl code from Aruma. There was some problem, which I fixed simply by deleting that section of the code. I used acpiexec from ACPICA tools to debug the ACPI code (acpica-unix-20081204/tools/acpiexec). What was the missing part? Windows requires right _CRS reporting of PCI0 bus. Windows needs to know platform independent way, how is I/O routed on PCI0 bus (and other busses). For K8 it means to read the I/O and MMIO routing registers (same as k8resdump provides) and make it ACPI object. This was perhaps done previously on Aruma board. The actual PCI regs are read in acpi-k8 in modelf and stored as SSDT table. The k8-util.asl code will construct the resources from that SSDT table. The only catch was that it orinally added for SB also a resource from TOM to PCI0_min. Which was invalid. This part was simply deleted as I did not need it and it was wrong anyway. The k8-util file is copyright by AMD but no licence. I just deleted small part so I did not added myself there. The attached patch fixes: The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. The second patch just monitors what else is needed to be able to boot SeaBIOS with ACPI and K8M890 VGA ROM. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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r3842 build service
by coreboot information 23 Dec '08

23 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3842 to the coreboot source repository and caused the following changes: Change Log: This belongs to changeset: 3840 The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:m2v-mx_se has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3841 build service
by coreboot information 23 Dec '08

23 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3841 to the coreboot source repository and caused the following changes: Change Log: Following patch fixes error code 12 in Windows XP and Vista. The function field of _PRT entry must be always 0xffff (any function). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-By: Patrick Georgi <patrick(a)georgi-clan.de> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3841&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r1086 - in coreboot-v3/util/x86emu: . yabel
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: myles Date: 2008-12-23 20:21:54 +0100 (Tue, 23 Dec 2008) New Revision: 1086 Added: coreboot-v3/util/x86emu/yabel/pmm.c coreboot-v3/util/x86emu/yabel/pmm.h Modified: coreboot-v3/util/x86emu/Makefile coreboot-v3/util/x86emu/yabel/biosemu.c coreboot-v3/util/x86emu/yabel/interrupt.c Log: Subject: [PATCH] YABEL: add PMM functionality. Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/util/x86emu/Makefile =================================================================== --- coreboot-v3/util/x86emu/Makefile 2008-12-23 19:02:44 UTC (rev 1085) +++ coreboot-v3/util/x86emu/Makefile 2008-12-23 19:21:54 UTC (rev 1086) @@ -29,6 +29,7 @@ BIOSEMU_SRC = biosemu.c debug.c device.c mem.c io.c interrupt.c #TODO: add vbe.c, currently not needed... #BIOSEMU_SRC +=vbe.c +BIOSEMU_SRC +=pmm.c #PH: TODO: remove the compat files?? BIOSEMU_SRC += compat/functions.c X86EMU_INCLUDE += -I $(src)/util/x86emu/yabel Modified: coreboot-v3/util/x86emu/yabel/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/yabel/biosemu.c 2008-12-23 19:02:44 UTC (rev 1085) +++ coreboot-v3/util/x86emu/yabel/biosemu.c 2008-12-23 19:21:54 UTC (rev 1086) @@ -26,6 +26,7 @@ #include "mem.h" #include "interrupt.h" #include "device.h" +#include "pmm.h" #include <rtas.h> @@ -56,7 +57,9 @@ u8 *rom_image; int i = 0; #ifdef DEBUG - debug_flags = DEBUG_PRINT_INT10 | DEBUG_PNP | DEBUG_PMM | DEBUG_INTR;// | DEBUG_CHECK_VMEM_ACCESS | DEBUG_MEM | DEBUG_IO;// | DEBUG_TRACE_X86EMU | DEBUG_JMP; + debug_flags = DEBUG_PRINT_INT10 | DEBUG_PNP | DEBUG_PMM | DEBUG_INTR; + // | DEBUG_CHECK_VMEM_ACCESS | DEBUG_MEM | DEBUG_IO; + // | DEBUG_TRACE_X86EMU | DEBUG_JMP; #endif if (biosmem_size < MIN_REQUIRED_VMEM_SIZE) { printf("Error: Not enough virtual memory: %x, required: %x!\n", @@ -209,6 +212,20 @@ X86EMU_setupPioFuncs(&my_pio_funcs); X86EMU_setupMemFuncs(&my_mem_funcs); + //setup PMM struct in BIOS_DATA_SEGMENT, offset 0x0 + u8 pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + if (pmm_length <= 0) { + printf ("\nYABEL: Warning: PMM Area could not be setup. PMM not available (%x)\n", + pmm_length); + return 0; + } else { + CHECK_DBG(DEBUG_PMM) { + /* test the PMM */ + pmm_test(); + /* and clean it again by calling pmm_setup... */ + pmm_length = pmm_setup(BIOS_DATA_SEGMENT, 0x0); + } + } // setup the CPU M.x86.R_AH = bios_device.bus; M.x86.R_AL = bios_device.devfn; @@ -248,8 +265,9 @@ X86EMU_exec(); DEBUG_PRINTF("done\n"); - // according to PNP BIOS Spec, Option ROMs should upon exit, return some boot device status in - // AX (see PNP BIOS Spec Section 3.3 + /* According to the PNP BIOS Spec, Option ROMs should upon exit, return + * some boot device status in AX (see PNP BIOS Spec Section 3.3 + */ DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX); #ifdef DEBUG DEBUG_PRINTF("Exit Status Decode:\n"); Modified: coreboot-v3/util/x86emu/yabel/interrupt.c =================================================================== --- coreboot-v3/util/x86emu/yabel/interrupt.c 2008-12-23 19:02:44 UTC (rev 1085) +++ coreboot-v3/util/x86emu/yabel/interrupt.c 2008-12-23 19:21:54 UTC (rev 1086) @@ -16,6 +16,7 @@ #include "mem.h" #include "device.h" #include "debug.h" +#include "pmm.h" #include <x86emu/x86emu.h> #include <x86emu/prim_ops.h> @@ -540,6 +541,13 @@ handleInt1a(); int_handled = 1; break; + case PMM_INT_NUM: + /* the selfdefined PMM INT number, this is called by the code in PMM struct, it + * is handled by pmm_handleInt() + */ + pmm_handleInt(); + int_handled = 1; + break; default: printf("Interrupt %#x (Vector: %x) not implemented\n", intNum, my_rdl(intNum * 4)); Added: coreboot-v3/util/x86emu/yabel/pmm.c =================================================================== --- coreboot-v3/util/x86emu/yabel/pmm.c (rev 0) +++ coreboot-v3/util/x86emu/yabel/pmm.c 2008-12-23 19:21:54 UTC (rev 1086) @@ -0,0 +1,437 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ + +#include <x86emu/x86emu.h> +#include <x86emu/prim_ops.h> +#include <string.h> + +#include "biosemu.h" +#include "pmm.h" +#include "debug.h" +#include "device.h" + +/* this struct is used to remember which PMM spaces + * have been assigned. MAX_PMM_AREAS defines how many + * PMM areas we can assign. + * All areas are assigned in PMM_CONV_SEGMENT + */ +typedef struct { + u32 handle; /* handle that is returned to PMM caller */ + u32 offset; /* in PMM_CONV_SEGMENT */ + u32 length; /* length of this area */ +} pmm_allocation_t; + +#define MAX_PMM_AREAS 10 + +/* array to store the above structs */ +static pmm_allocation_t pmm_allocation_array[MAX_PMM_AREAS]; + +/* index into pmm_allocation_array */ +static u32 curr_pmm_allocation_index = 0; + +/* This function is used to setup the PMM struct in virtual memory + * at a certain offset, the length of the PMM struct is returned */ +u8 pmm_setup(u16 segment, u16 offset) +{ + /* setup the PMM structure */ + pmm_information_t *pis = + (pmm_information_t *) (M.mem_base + (((u32) segment) << 4) + + offset); + memset(pis, 0, sizeof(pmm_information_t)); + /* set signature to $PMM */ + pis->signature[0] = '$'; + pis->signature[1] = 'P'; + pis->signature[2] = 'M'; + pis->signature[3] = 'M'; + /* revision as specified */ + pis->struct_rev = 0x01; + /* internal length, excluding code */ + pis->length = ((void *)&(pis->code) - (void *)&(pis->signature)); + /* the code to be executed, pointed to by entry_point_offset */ + pis->code[0] = 0xCD; /* INT */ + pis->code[1] = PMM_INT_NUM; /* my selfdefined PMM INT number */ + pis->code[2] = 0xCB; /* RETF */ + /* set the entry_point_offset, it should point to pis->code, segment is the segment of + * this struct. Since pis->length is the length of the struct excluding code, offset+pis->length + * points to the code... it's that simple ;-) + */ + out32le(&(pis->entry_point_offset), + (u32) segment << 16 | (u32) (offset + pis->length)); + /* checksum calculation */ + u8 i; + u8 checksum = 0; + for (i = 0; i < pis->length; i++) { + checksum += *(((u8 *) pis) + i); + } + pis->checksum = ((u8) 0) - checksum; + CHECK_DBG(DEBUG_PMM) { + DEBUG_PRINTF_PMM("PMM Structure:\n"); + dump((void *)pis, sizeof(pmm_information_t)); + } + return sizeof(pmm_information_t); +} + +/* handle the selfdefined interrupt, this is executed, when the PMM Entry Point + * is executed, it must handle all PMM requests + */ +void pmm_handleInt() +{ + u32 rval = 0; + u16 function, flags; + u32 handle, length; + u32 i, j; + u32 buffer; + /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + * according to the PMM Spec "the flags and all registers, except DX and AX + * are preserved across calls to PMM" + * so we save M.x86 and in :exit label we restore it, however, this means that no + * returns must be used in this function, any exit must use goto exit! + * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + */ + X86EMU_regs backup_regs = M.x86; + pop_long(); /* pop the return address, this is already saved in INT handler, we don't need + to remember this. */ + function = pop_word(); + switch (function) { + case 0: + /* function pmmAllocate */ + length = pop_long(); + length *= 16; /* length is passed in "paragraphs" of 16 bytes each */ + handle = pop_long(); + flags = pop_word(); + DEBUG_PRINTF_PMM + ("%s: pmmAllocate: Length: %x, Handle: %x, Flags: %x\n", + __FUNCTION__, length, handle, flags); + if ((flags & 0x1) != 0) { + /* request to allocate in conventional memory */ + if (curr_pmm_allocation_index >= MAX_PMM_AREAS) { + printf + ("%s: pmmAllocate: Maximum Number of allocatable areas reached (%d), cannot allocate more memory!\n", + __FUNCTION__, MAX_PMM_AREAS); + rval = 0; + goto exit; + } + /* some ROMs seem to be confused by offset 0, so lets start at 0x100 */ + u32 next_offset = 0x100; + pmm_allocation_t *pmm_alloc = + &(pmm_allocation_array[curr_pmm_allocation_index]); + if (curr_pmm_allocation_index != 0) { + /* we have already allocated... get the new next_offset + * from the previous pmm_allocation_t */ + next_offset = + pmm_allocation_array + [curr_pmm_allocation_index - 1].offset + + pmm_allocation_array + [curr_pmm_allocation_index - 1].length; + } + DEBUG_PRINTF_PMM("%s: next_offset: 0x%x\n", + __FUNCTION__, next_offset); + if (length == 0) { + /* largest possible block size requested, we have on segment + * to allocate, so largest possible is segment size (0xFFFF) + * minus next_offset + */ + rval = 0xFFFF - next_offset; + goto exit; + } + u32 align = 0; + if (((flags & 0x4) != 0) && (length > 0)) { + /* align to least significant bit set in length param */ + u8 lsb = 0; + while (((length >> lsb) & 0x1) == 0) { + lsb++; + } + align = 1 << lsb; + } + /* always align at least to paragraph (16byte) boundary + * hm... since the length is always in paragraphs, we cannot + * align outside of paragraphs anyway... so this check might + * be unnecessary...*/ + if (align < 0x10) { + align = 0x10; + } + DEBUG_PRINTF_PMM("%s: align: 0x%x\n", __FUNCTION__, + align); + if ((next_offset & (align - 1)) != 0) { + /* not yet aligned... align! */ + next_offset += align; + next_offset &= ~(align - 1); + } + if ((next_offset + length) > 0xFFFF) { + rval = 0; + printf + ("%s: pmmAllocate: Not enough memory available for allocation!\n", + __FUNCTION__); + goto exit; + } + curr_pmm_allocation_index++; + /* remember the values in pmm_allocation_array */ + pmm_alloc->handle = handle; + pmm_alloc->offset = next_offset; + pmm_alloc->length = length; + /* return the 32bit "physical" address, i.e. combination of segment and offset */ + rval = ((u32) (PMM_CONV_SEGMENT << 16)) | next_offset; + DEBUG_PRINTF_PMM + ("%s: pmmAllocate: allocated memory at %x\n", + __FUNCTION__, rval); + } else { + rval = 0; + printf + ("%s: pmmAllocate: allocation in extended memory not supported!\n", + __FUNCTION__); + } + goto exit; + case 1: + /* function pmmFind */ + handle = pop_long(); /* the handle to lookup */ + DEBUG_PRINTF_PMM("%s: pmmFind: Handle: %x\n", __FUNCTION__, + handle); + i = 0; + for (i = 0; i < curr_pmm_allocation_index; i++) { + if (pmm_allocation_array[i].handle == handle) { + DEBUG_PRINTF_PMM + ("%s: pmmFind: found allocated memory at %x\n", + __FUNCTION__, rval); + /* return the 32bit "physical" address, i.e. combination of segment and offset */ + rval = + ((u32) (PMM_CONV_SEGMENT << 16)) | + pmm_allocation_array[i].offset; + } + } + if (rval == 0) { + DEBUG_PRINTF_PMM + ("%s: pmmFind: handle (%x) not found!\n", + __FUNCTION__, handle); + } + goto exit; + case 2: + /* function pmmDeallocate */ + buffer = pop_long(); + /* since argument is the address of the PMM block (including the segment, + * we need to remove the segment to get the offset + */ + buffer = buffer ^ ((u32) PMM_CONV_SEGMENT << 16); + DEBUG_PRINTF_PMM("%s: pmmDeallocate: PMM segment offset: %x\n", + __FUNCTION__, buffer); + i = 0; + /* rval = 0 means we deallocated the buffer, so set it to 1 in case we dont find it and + * thus cannot deallocate + */ + rval = 1; + for (i = 0; i < curr_pmm_allocation_index; i++) { + DEBUG_PRINTF_PMM("%d: %x\n", i, + pmm_allocation_array[i].handle); + if (pmm_allocation_array[i].offset == buffer) { + /* we found the requested buffer, rval = 0 */ + rval = 0; + DEBUG_PRINTF_PMM + ("%s: pmmDeallocate: found allocated memory at index: %d\n", + __FUNCTION__, i); + /* copy the remaining elements in pmm_allocation_array one position up */ + j = i; + for (; j < curr_pmm_allocation_index; j++) { + pmm_allocation_array[j] = + pmm_allocation_array[j + 1]; + } + /* move curr_pmm_allocation_index one up, too */ + curr_pmm_allocation_index--; + /* finally clean last element */ + pmm_allocation_array[curr_pmm_allocation_index]. + handle = 0; + pmm_allocation_array[curr_pmm_allocation_index]. + offset = 0; + pmm_allocation_array[curr_pmm_allocation_index]. + length = 0; + break; + } + } + if (rval != 0) { + DEBUG_PRINTF_PMM + ("%s: pmmDeallocate: offset (%x) not found, cannot deallocate!\n", + __FUNCTION__, buffer); + } + goto exit; + default: + /* invalid/unimplemented function */ + printf("%s: invalid PMM function (0x%04x) called!\n", + __FUNCTION__, function); + /* PMM spec says if function is invalid, return 0xFFFFFFFF */ + rval = 0xFFFFFFFF; + goto exit; + } + exit: + /* exit handler of this function, restore registers, put return value in DX:AX */ + M.x86 = backup_regs; + M.x86.R_DX = (u16) ((rval >> 16) & 0xFFFF); + M.x86.R_AX = (u16) (rval & 0xFFFF); + CHECK_DBG(DEBUG_PMM) { + DEBUG_PRINTF_PMM("%s: dump of pmm_allocation_array:\n", + __FUNCTION__); + for (i = 0; i < MAX_PMM_AREAS; i++) { + DEBUG_PRINTF_PMM + ("%d:\n\thandle: %x\n\toffset: %x\n\tlength: %x\n", + i, pmm_allocation_array[i].handle, + pmm_allocation_array[i].offset, + pmm_allocation_array[i].length); + } + } + return; +} + +/* This function tests the pmm_handleInt() function above. */ +void pmm_test(void) +{ + u32 handle, length, addr; + u16 function, flags; + /*-------------------- Test simple allocation/find/deallocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 16; /* in 16byte paragraphs, so we allocate 256 bytes... */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, + M.x86.R_DX, M.x86.R_AX); + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM("%s: found memory at: %04x:%04x (expected: %08x)\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX, addr); + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM + ("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + /*-------------------- Test aligned allocation/deallocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 257; /* in 16byte paragraphs, so we allocate 4KB + 16 bytes... */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, + M.x86.R_DX, M.x86.R_AX); + function = 0; /* pmmAllocate */ + handle = 0xf00d4b0b; + length = 128; /* in 16byte paragraphs, so we allocate 2KB... */ + flags = 0x5; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + /* the address should be aligned to 0x800, so probably it is at offset 0x1800... */ + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, + M.x86.R_DX, M.x86.R_AX); + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM + ("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + handle = 0xdeadbeef; + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM + ("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + /*-------------------- Test out of memory allocation ----------------------------- */ + function = 0; /* pmmAllocate */ + handle = 0xdeadbeef; + length = 0; /* length zero means, give me the largest possible block */ + flags = 0x1; /* conventional memory, unaligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + length = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + length /= 16; /* length in paragraphs */ + DEBUG_PRINTF_PMM("%s: largest possible length: %08x\n", __FUNCTION__, + length); + function = 0; /* pmmAllocate */ + flags = 0x1; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM("%s: allocated memory at: %04x:%04x\n", __FUNCTION__, + M.x86.R_DX, M.x86.R_AX); + function = 0; /* pmmAllocate */ + length = 1; + handle = 0xf00d4b0b; + flags = 0x1; /* conventional memory, aligned */ + /* setup stack for call to pmm_handleInt() */ + push_word(flags); + push_long(handle); + push_long(length); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + /* this should fail, so 0x0 should be returned */ + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + DEBUG_PRINTF_PMM + ("%s: allocated memory at: %04x:%04x expected: 0000:0000\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX); + handle = 0xdeadbeef; + function = 1; /* pmmFind */ + push_long(handle); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + addr = ((u32) M.x86.R_DX << 16) | M.x86.R_AX; + function = 2; /* pmmDeallocate */ + push_long(addr); + push_word(function); + push_long(0); /* This is the return address for the ABI, unused in this implementation */ + pmm_handleInt(); + DEBUG_PRINTF_PMM + ("%s: freed memory rval: %04x:%04x (expected: 0000:0000)\n", + __FUNCTION__, M.x86.R_DX, M.x86.R_AX); +} Added: coreboot-v3/util/x86emu/yabel/pmm.h =================================================================== --- coreboot-v3/util/x86emu/yabel/pmm.h (rev 0) +++ coreboot-v3/util/x86emu/yabel/pmm.h 2008-12-23 19:21:54 UTC (rev 1086) @@ -0,0 +1,41 @@ +/**************************************************************************** + * YABEL BIOS Emulator + * + * Copyright 2008 Pattrick Hueper <phueper(a)hueper.net> + ****************************************************************************/ + +#ifndef _YABEL_PMM_H_ +#define _YABEL_PMM_H_ + +#include <types.h> + +/* PMM Structure see PMM Spec Version 1.01 Chapter 3.1.1 + * (search web for specspmm101.pdf) + */ +typedef struct { + u8 signature[4]; + u8 struct_rev; + u8 length; + u8 checksum; + u32 entry_point_offset; + u8 reserved[5]; + /* Code is not part of the speced PMM struct, however, since I cannot + * put the handling of PMM in the virtual memory (I dont want to hack it + * together in x86 assembly ;-)) this code array is pointed to by + * entry_point_offset, in code there is only a INT call and a RETF, + * thus every PMM call will issue a PMM INT (only defined in YABEL, + * see interrupt.c) and the INT Handler will do the actual PMM work. + */ + u8 code[3]; +} __attribute__ ((__packed__)) pmm_information_t; + +/* This function is used to setup the PMM struct in virtual memory + * at a certain offset */ +u8 pmm_setup(u16 segment, u16 offset); + +/* This is the INT Handler mentioned above, called by my special PMM INT. */ +void pmm_handleInt(void); + +void pmm_test(void); + +#endif // _YABEL_PMM_H

1 0

[PATCH] v3: remove stage1_mtrr.c, add mtrr.c for stage2
by Corey Osgood 23 Dec '08

23 Dec '08

Patch attached, tested and seems to be working on jetway j7f2. -Corey

3 3

r1085 - in coreboot-v3: arch/x86 include/arch/x86 mainboard/amd/dbm690t mainboard/amd/serengeti mainboard/gigabyte/m57sli mainboard/jetway/j7f2 mainboard/via/epia-cn
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: rminnich Date: 2008-12-23 20:02:44 +0100 (Tue, 23 Dec 2008) New Revision: 1085 Added: coreboot-v3/arch/x86/mtrr.c Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/Makefile coreboot-v3/include/arch/x86/cpu.h coreboot-v3/include/arch/x86/mtrr.h coreboot-v3/mainboard/amd/dbm690t/Makefile coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/jetway/j7f2/Makefile coreboot-v3/mainboard/via/epia-cn/Makefile Log: Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> It could use some cleanup, but looks good. Acked-by: Peter Stuge <peter(a)stuge.se> With some cleanup. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/arch/x86/Kconfig 2008-12-23 19:02:44 UTC (rev 1085) @@ -191,6 +191,15 @@ help This option sets the size of the area used for CAR. +config MTRR + bool + default n if CPU_AMD_GEODELX + default y if CPU_AMD_K8 + default y if CPU_VIA_C7 + default y if CPU_INTEL_CORE2 + help + This option indicates if a cpu has MTRR support. + config CBMEMK hex default 0x1000 if CPU_I586 Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/arch/x86/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -205,8 +205,12 @@ STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c multiboot.c udelay_io.c STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c -STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c +STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c +ifeq ($(CONFIG_MTRR),y) +STAGE2_ARCH_X86_SRC += mtrr.c +endif + ifeq ($(CONFIG_PIRQ_TABLE),y) STAGE2_ARCH_X86_SRC += pirq_routing.c endif Added: coreboot-v3/arch/x86/mtrr.c =================================================================== --- coreboot-v3/arch/x86/mtrr.c (rev 0) +++ coreboot-v3/arch/x86/mtrr.c 2008-12-23 19:02:44 UTC (rev 1085) @@ -0,0 +1,450 @@ +/* + * mtrr.c: setting MTRR to decent values for cache initialization on P6 + * + * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel + * + * Copyright 2000 Silicon Integrated System Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming + */ + +/* + 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed + 2005.6 Eric add address bit in x86_setup_mtrrs + 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, + for AMD, it will not use x86_setup_fixed_mtrrs +*/ + +#include <types.h> +#include <console.h> +#include <arch/x86/msr.h> +#include <arch/x86/mtrr.h> +#include <arch/x86/cpu.h> + +static unsigned int mtrr_msr[] = { + MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, + MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, + MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, +}; + + +void enable_fixed_mtrr(void) +{ + struct msr msr; + + msr = rdmsr(MTRRdefType_MSR); + msr.lo |= 0xc00; + wrmsr(MTRRdefType_MSR, msr); +} + +static void enable_var_mtrr(void) +{ + struct msr msr; + + msr = rdmsr(MTRRdefType_MSR); + msr.lo |= 0x800; + wrmsr(MTRRdefType_MSR, msr); +} + +/* setting variable mtrr, comes from linux kernel source */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned long type, unsigned long address_bits) +{ + struct msr base, mask; + unsigned address_mask_high; + + if (reg >= 8) + return; + + // it is recommended that we disable and enable cache when we + // do this. + if (sizek == 0) { + disable_cache(); + + struct msr zero; + zero.lo = zero.hi = 0; + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR(reg), zero); + + enable_cache(); + return; + } + + + address_mask_high = ((1u << (address_bits - 32u)) - 1u); + + base.hi = basek >> 22; + base.lo = basek << 10; + + printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high); + + if (sizek < 4*1024*1024) { + mask.hi = address_mask_high; + mask.lo = ~((sizek << 10) -1); + } + else { + mask.hi = address_mask_high & (~((sizek >> 22) -1)); + mask.lo = 0; + } + + // it is recommended that we disable and enable cache when we + // do this. + disable_cache(); + + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + base.lo |= type; + mask.lo |= 0x800; + wrmsr (MTRRphysBase_MSR(reg), base); + wrmsr (MTRRphysMask_MSR(reg), mask); + + enable_cache(); +} + +/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +static inline unsigned int fms(unsigned int x) +{ + int r; + + __asm__("bsrl %1,%0\n\t" + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + +/* fms: find least sigificant bit set */ +static inline unsigned int fls(unsigned int x) +{ + int r; + + __asm__("bsfl %1,%0\n\t" + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); + return r; +} + +/* setting up variable and fixed mtrr + * + * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: + * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). + * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous + * requirement. So a 8K range must be 8K aligned not 4K aligned. + * + * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). + * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). + * A 124MB (128MB - 4MB SMA) example: + * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). + * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. + * + * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, + * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula + * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. + * The same 124MB example: + * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) + * or a 156MB (128MB + 32MB - 4MB SMA) example: + * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) + */ +/* 2 MTRRS are reserved for the operating system */ +#if 0 +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#else +#define BIOS_MTRRS 8 +#define OS_MTRRS 0 +#endif +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) +{ + unsigned int i; + unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; + struct msr msr; + msr.lo = msr.hi = 0; /* Shut up gcc */ + for(i = first; i < last; i++) { + /* When I switch to a new msr read it in */ + if (fixed_msr != i >> 3) { + /* But first write out the old msr */ + if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { + disable_cache(); + wrmsr(mtrr_msr[fixed_msr], msr); + enable_cache(); + } + fixed_msr = i>>3; + msr = rdmsr(mtrr_msr[fixed_msr]); + } + if ((i & 7) < 4) { + msr.lo &= ~(0xff << ((i&3)*8)); + msr.lo |= type << ((i&3)*8); + } else { + msr.hi &= ~(0xff << ((i&3)*8)); + msr.hi |= type << ((i&3)*8); + } + } + /* Write out the final msr */ + if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { + disable_cache(); + wrmsr(mtrr_msr[fixed_msr], msr); + enable_cache(); + } +} + +static unsigned fixed_mtrr_index(unsigned long addrk) +{ + unsigned index; + index = (addrk - 0) >> 6; + if (index >= 8) { + index = ((addrk - 8*64) >> 4) + 8; + } + if (index >= 24) { + index = ((addrk - (8*64 + 16*16)) >> 2) + 24; + } + if (index > NUM_FIXED_RANGES) { + index = NUM_FIXED_RANGES; + } + return index; +} + +static unsigned int range_to_mtrr(unsigned int reg, + unsigned long range_startk, unsigned long range_sizek, + unsigned long next_range_startk, unsigned char type, unsigned address_bits) +{ + if (!range_sizek || (reg >= BIOS_MTRRS)) { + return reg; + } + while(range_sizek) { + unsigned long max_align, align; + unsigned long sizek; + /* Compute the maximum size I can make a range */ + max_align = fls(range_startk); + align = fms(range_sizek); + if (align > max_align) { + align = max_align; + } + sizek = 1 << align; + printk(BIOS_DEBUG, "Setting variable MTRR %d, range: %ldMB, size: %ldMB, type %s\n", + reg, range_startk >>10, sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); + set_var_mtrr(reg++, range_startk, sizek, type, address_bits); + range_startk += sizek; + range_sizek -= sizek; + if (reg >= BIOS_MTRRS) + break; + } + return reg; +} + +static unsigned long resk(u64 value) +{ + unsigned long resultk; + if (value < (1ULL << 42)) { + resultk = value >> 10; + } + else { + resultk = 0xffffffff; + } + return resultk; +} + +static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) +{ + unsigned int start_mtrr; + unsigned int last_mtrr; + start_mtrr = fixed_mtrr_index(resk(res->base)); + last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); + if (start_mtrr >= NUM_FIXED_RANGES) { + return; + } + printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", + start_mtrr, last_mtrr); + set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); + +} + +#ifndef CONFIG_VAR_MTRR_HOLE +#define CONFIG_VAR_MTRR_HOLE 1 +#endif + +struct var_mtrr_state { + unsigned long range_startk, range_sizek; + unsigned int reg; +#if CONFIG_VAR_MTRR_HOLE + unsigned long hole_startk, hole_sizek; +#endif + unsigned address_bits; +}; + +void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) +{ + struct var_mtrr_state *state = gp; + unsigned long basek, sizek; + if (state->reg >= BIOS_MTRRS) + return; + basek = resk(res->base); + sizek = resk(res->size); + /* See if I can merge with the last range + * Either I am below 1M and the fixed mtrrs handle it, or + * the ranges touch. + */ + if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { + unsigned long endk = basek + sizek; + state->range_sizek = endk - state->range_startk; + return; + } + /* Write the range mtrrs */ + if (state->range_sizek != 0) { +#if CONFIG_VAR_MTRR_HOLE + if (state->hole_sizek == 0) { + /* We need to put that on to hole */ + unsigned long endk = basek + sizek; + state->hole_startk = state->range_startk + state->range_sizek; + state->hole_sizek = basek - state->hole_startk; + state->range_sizek = endk - state->range_startk; + return; + } +#endif + state->reg = range_to_mtrr(state->reg, state->range_startk, + state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits); +#if CONFIG_VAR_MTRR_HOLE + state->reg = range_to_mtrr(state->reg, state->hole_startk, + state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits); +#endif + state->range_startk = 0; + state->range_sizek = 0; +#if CONFIG_VAR_MTRR_HOLE + state->hole_startk = 0; + state->hole_sizek = 0; +#endif + } + /* Allocate an msr */ + printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); + state->range_startk = basek; + state->range_sizek = sizek; +} + +void x86_setup_fixed_mtrrs(void) +{ + /* Try this the simple way of incrementally adding together + * mtrrs. If this doesn't work out we can get smart again + * and clear out the mtrrs. + */ + + printk(BIOS_DEBUG, "\n"); + /* Initialized the fixed_mtrrs to uncached */ + printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", + 0, NUM_FIXED_RANGES); + set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); + + /* Now see which of the fixed mtrrs cover ram. + */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + set_fixed_mtrr_resource, NULL); + printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); + + /* enable fixed MTRR */ + printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); + enable_fixed_mtrr(); + +} +void x86_setup_var_mtrrs(unsigned address_bits) +/* this routine needs to know how many address bits a given processor + * supports. CPUs get grumpy when you set too many bits in + * their mtrr registers :( I would generically call cpuid here + * and find out how many physically supported but some cpus are + * buggy, and report more bits then they actually support. + */ +{ + /* Try this the simple way of incrementally adding together + * mtrrs. If this doesn't work out we can get smart again + * and clear out the mtrrs. + */ + struct var_mtrr_state var_state; + + /* Cache as many memory areas as possible */ + /* FIXME is there an algorithm for computing the optimal set of mtrrs? + * In some cases it is definitely possible to do better. + */ + var_state.range_startk = 0; + var_state.range_sizek = 0; +#if CONFIG_VAR_MTRR_HOLE + var_state.hole_startk = 0; + var_state.hole_sizek = 0; +#endif + var_state.reg = 0; + var_state.address_bits = address_bits; + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + set_var_mtrr_resource, &var_state); + + /* Write the last range */ + var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, + var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits); +#if CONFIG_VAR_MTRR_HOLE + var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, + var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits); +#endif + printk(BIOS_DEBUG, "DONE variable MTRRs\n"); + printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); + /* Clear out the extra MTRR's */ + while(var_state.reg < MTRRS) { + set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); + } + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); + enable_var_mtrr(); + printk(BIOS_SPEW, "Leave %s\n", __FUNCTION__); + post_code(0x6A); +} + +void x86_setup_mtrrs(unsigned address_bits) +{ + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(address_bits); +} + + +int x86_mtrr_check(void) +{ + /* Only Pentium Pro and later have MTRR */ + struct msr msr; + printk(BIOS_DEBUG, "\nMTRR check\n"); + + msr = rdmsr(0x2ff); + msr.lo >>= 10; + + printk(BIOS_DEBUG, "Fixed MTRRs : "); + if (msr.lo & 0x01) + printk(BIOS_DEBUG, "Enabled\n"); + else + printk(BIOS_DEBUG, "Disabled\n"); + + printk(BIOS_DEBUG, "Variable MTRRs: "); + if (msr.lo & 0x02) + printk(BIOS_DEBUG, "Enabled\n"); + else + printk(BIOS_DEBUG, "Disabled\n"); + + printk(BIOS_DEBUG, "\n"); + + post_code(0x93); + return ((int) msr.lo); +} Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/include/arch/x86/cpu.h 2008-12-23 19:02:44 UTC (rev 1085) @@ -107,7 +107,7 @@ void set_var_mtrr_x( unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type); void set_var_mtrr( - unsigned long reg, unsigned long base, unsigned long size, unsigned long type); + unsigned int reg, unsigned long basek, unsigned long sizek, unsigned long type, unsigned long address_bits); /* generic SMP functions required to be supported (even by non-SMP) */ Modified: coreboot-v3/include/arch/x86/mtrr.h =================================================================== --- coreboot-v3/include/arch/x86/mtrr.h 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/include/arch/x86/mtrr.h 2008-12-23 19:02:44 UTC (rev 1085) @@ -35,7 +35,6 @@ void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); -void early_mtrr_init(void); #endif Modified: coreboot-v3/mainboard/amd/dbm690t/Makefile =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/mainboard/amd/dbm690t/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -22,7 +22,6 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/northbridge/amd/k8/get_nodes.c \ @@ -36,7 +35,6 @@ $(src)/northbridge/amd/k8/incoherent_ht.c \ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/arch/x86/pci_ops_conf1.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ $(src)/arch/x86/amd/model_fxx/fidvid.c \ $(src)/arch/x86/amd/model_fxx/init_cpus.c \ Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -22,7 +22,6 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/arch/x86/resourcemap.c \ @@ -42,7 +41,6 @@ $(src)/northbridge/amd/k8/incoherent_ht.c \ $(src)/northbridge/amd/k8/util.c \ $(src)/arch/x86/pci_ops_conf1.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ $(src)/arch/x86/amd/model_fxx/fidvid.c \ Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -22,7 +22,6 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/arch/x86/resourcemap.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/northbridge/amd/k8/get_nodes.c \ Modified: coreboot-v3/mainboard/jetway/j7f2/Makefile =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/mainboard/jetway/j7f2/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -23,7 +23,6 @@ STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/northbridge/via/cn700/stage1.c \ $(src)/southbridge/via/vt8237/stage1.c \ - $(src)/arch/x86/stage1_mtrr.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \ Modified: coreboot-v3/mainboard/via/epia-cn/Makefile =================================================================== --- coreboot-v3/mainboard/via/epia-cn/Makefile 2008-12-23 07:09:46 UTC (rev 1084) +++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-12-23 19:02:44 UTC (rev 1085) @@ -19,7 +19,6 @@ ## STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ - $(src)/arch/x86/stage1_mtrr.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/southbridge/via/vt8237/stage1.c \ $(src)/northbridge/via/cn700/stage1.c \

1 0

patch: mtrr Kconfig variable
by ron minnich 23 Dec '08

23 Dec '08

attached ron

2 1

r3842 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
by svn＠coreboot.org 23 Dec '08

23 Dec '08

Author: ruik Date: 2008-12-23 19:29:50 +0100 (Tue, 23 Dec 2008) New Revision: 3842 Added: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl Log: This belongs to changeset: 3840 The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/amdk8_util.asl 2008-12-23 18:29:50 UTC (rev 3842) @@ -0,0 +1,307 @@ +/* + * Copyright 2005 AMD + */ + +//AMD k8 util for BUSB and res range + + Scope (\_SB) + { + + Name (OSTB, Ones) + Method (OSTP, 0, NotSerialized) + { + If (LEqual (^OSTB, Ones)) + { + Store (0x00, ^OSTB) + } + + Return (^OSTB) + } + + Method (SEQL, 2, Serialized) + { + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) + } + + + Method (DADD, 2, NotSerialized) + { + Store( Arg1, Local0) + Store( Arg0, Local1) + Add( ShiftLeft(Local1,16), Local0, Local0) + Return (Local0) + } + + + Method (GHCE, 1, NotSerialized) // check if the HC enabled + { + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) } + Else { Return (0x00) } + } + + Method (GHCN, 1, NotSerialized) // get the node num for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0) + Return (Local0) + } + + Method (GHCL, 1, NotSerialized) // get the link num on node for the HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1) + Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0) + Return (Local0) + } + + Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC + { + Store (0x00, Local0) + Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1) + Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0 + Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0 + Store (And (ShiftRight( Local1, Local2), 0xff), Local0) + Return (Local0) + } + + Method (GBUS, 2, NotSerialized) + { + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Return (ShiftRight (And (Local1, 0x00FF0000), 0x10)) + } + } + } + + Increment (Local0) + } + + Return (0x00) + } + + Method (GWBN, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0000, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0000,,,) + }) + CreateWordField (BUF0, 0x08, BMIN) + CreateWordField (BUF0, 0x0A, BMAX) + CreateWordField (BUF0, 0x0E, BLEN) + Store (0x00, Local0) + While (LLess (Local0, 0x04)) + { + Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08)))) + { + Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN) + Store (ShiftRight (Local1, 0x18), BMAX) + Subtract (BMAX, BMIN, BLEN) + Increment (BLEN) + Return (RTAG (BUF0)) + } + } + } + + Increment (Local0) + } + + Return (RTAG (BUF0)) + } + + Method (GMEM, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x10)) + { + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (BUF0, Local3) + } + + Return (Local3) + } + + Method (GIOR, 2, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000000,,, + , TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, PMIN) + CreateDWordField (BUF0, 0x0E, PMAX) + CreateDWordField (BUF0, 0x16, PLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x08)) + { + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) + { + If (LEqual (Arg0, And (Local2, 0x07))) + { + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + Store (And (Local1, 0x01FFF000), PMIN) + Store (And (Local2, 0x01FFF000), PMAX) + Or (PMAX, 0x0FFF, PMAX) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + If (LGreater (PMAX, PMIN)) + { + If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK))) + { + Store (0x0D00, PMIN) + Subtract (PMAX, PMIN, PLEN) + Increment (PLEN) + } + Store (RTAG (BUF0), Local3) + Increment (Local4) + } + + If (And (Local1, 0x10)) + { + Store (0x03B0, PMIN) + Store (0x03DF, PMAX) + Store (0x30, PLEN) + + If (Local4) + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + } + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) + } + + Method (RTAG, 1, NotSerialized) + { + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) + } + } +

1 0

r3840 build service
by coreboot information 23 Dec '08

23 Dec '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3840 to the coreboot source repository and caused the following changes: Change Log: The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy. The FADT bootarch flags Blacklists MSI for this chipset (maybe not needed) Adds modified amdk8_util.asl Adds the SSDT table to chain of tables Aligns the FACS correctly (this should be done for other boards) Adds the _CRS method to Asus M2V-MX SE acpi DSDT. Fixes the FACS table length. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3840&device=m2v-mx_se&vend… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] fix SATA _PRT
by Rudolf Marek 23 Dec '08

23 Dec '08

Hello, Following patch fixes error code 12 in Windows XP and Vista. The function field of _PRT entry must be always 0xffff (any function). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf

2 2

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coreboot December 2008