r1087 - in coreboot-v3: arch/x86/via mainboard/jetway mainboard/jetway/j7f2 northbridge/via/cn700 southbridge/via/vt8237
Author: cozzie Date: 2008-12-24 00:44:39 +0100 (Wed, 24 Dec 2008) New Revision: 1087
Modified: coreboot-v3/arch/x86/via/c7.c coreboot-v3/mainboard/jetway/Kconfig coreboot-v3/mainboard/jetway/j7f2/dts coreboot-v3/northbridge/via/cn700/cn700.h coreboot-v3/northbridge/via/cn700/initram.c coreboot-v3/northbridge/via/cn700/pci_domain.c coreboot-v3/northbridge/via/cn700/stage1.c coreboot-v3/southbridge/via/vt8237/Makefile coreboot-v3/southbridge/via/vt8237/lpc.c coreboot-v3/southbridge/via/vt8237/stage1.c coreboot-v3/southbridge/via/vt8237/vt8237.c Log: This patch fixes a few small problems and gets cn700 to read from an IDE disk and attempt to boot a linux kernel.
Signed-off-by: Corey Osgood corey.osgood@gmail.com Acked-by: Corey Osgood corey.osgood@gmail.com
Modified: coreboot-v3/arch/x86/via/c7.c =================================================================== --- coreboot-v3/arch/x86/via/c7.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/arch/x86/via/c7.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -89,7 +89,7 @@ (int)((msr.lo >> 8) & 0xff), (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
- printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo); + printk(BIOS_DEBUG, " msr.lo = %x, msr.hi = %x\n", msr.lo, msr.hi);
/* Wait while CPU is busy */ cnt = 0; @@ -109,7 +109,7 @@ new = current; switch (model) { case 10: // model A - for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { + for (i = 0; i <= ARRAY_SIZE(c7a_speed_translation); i += 2) { if ((c7a_speed_translation[i] == current) && ((c7a_speed_translation[i + 1] & 0xff00) == (msr.hi & 0xff00))) { @@ -118,7 +118,7 @@ } break; case 13: // model D - for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { + for (i = 0; i <= ARRAY_SIZE(c7d_speed_translation); i += 2) { if ((c7d_speed_translation[i] == current) && ((c7d_speed_translation[i + 1] & 0xff00) == (msr.hi & 0xff00))) { @@ -203,8 +203,8 @@
/* Set up Memory Type Range Registers */ //these don't exist yet - //x86_setup_mtrrs(36); - //x86_mtrr_check(); + x86_setup_mtrrs(36); + x86_mtrr_check();
/* Enable the local cpu apics */ //setup_lapic();
Modified: coreboot-v3/mainboard/jetway/Kconfig =================================================================== --- coreboot-v3/mainboard/jetway/Kconfig 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/mainboard/jetway/Kconfig 2008-12-23 23:44:39 UTC (rev 1087) @@ -28,6 +28,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237 select SUPERIO_FINTEK_F71805F + select PIRQ_TABLE help Jetway J7F2-Series board. endchoice
Modified: coreboot-v3/mainboard/jetway/j7f2/dts =================================================================== --- coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/mainboard/jetway/j7f2/dts 2008-12-23 23:44:39 UTC (rev 1087) @@ -43,8 +43,8 @@ /{ mainboard_vendor = "Jetway"; mainboard_name = "J7F2"; - mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */ - mainboard_pci_subsystem_device = "0xbeef"; /* TODO */ + subsystem_vendor = "0xdead"; /* TODO */ + subsystem_device = "0xbeef"; /* TODO */ cpus { /config/("arch/x86/via/c7.dts"); }; @@ -66,23 +66,33 @@ /* How do I represent the bus and pci devices hanging here? */ pci@1,0 { /config/("northbridge/via/cn700/pci.dts"); - pci@0,1 { + pci@0,0 { /config/("northbridge/via/cn700/vga.dts"); }; }; - pci@f,0 {}; - pci@10,0 { + pci@f,0 { /config/("southbridge/via/vt8237/sata.dts"); }; - pci@10,1 { + pci@f,1 { /config/("southbridge/via/vt8237/ide.dts"); + ide0_enable = "1"; + ide1_enable = "0"; + ide0_80pin_cable = "1"; + ide1_80pin_cable = "0"; }; + pci@10,0 { }; + pci@10,1 { }; + pci@10,2 { }; + pci@10,3 { }; + pci@10,4 { }; pci@11,0 { /config/("southbridge/via/vt8237/lpc.dts"); + ioport@4e { + /config/("superio/fintek/f71805f/dts"); + com2enable = "1"; + }; }; - ioport@4e { - /config/("superio/fintek/f71805f/dts"); - com2enable = "1"; - }; + pci@11,5 { }; + pci@12,0 { }; }; };
Modified: coreboot-v3/northbridge/via/cn700/cn700.h =================================================================== --- coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/cn700.h 2008-12-23 23:44:39 UTC (rev 1087) @@ -34,12 +34,12 @@ void ddr2_sdram_enable(struct board_info *);
/* VGA stuff */ -#define SR_INDEX 0x3c4 -#define SR_DATA 0x3c5 -#define CRTM_INDEX 0x3b4 -#define CRTM_DATA 0x3b5 -#define CRTC_INDEX 0x3d4 -#define CRTC_DATA 0x3d5 +#define SR_INDEX 0x3c4 +#define SR_DATA 0x3c5 +#define CRTM_INDEX 0x3b4 +#define CRTM_DATA 0x3b5 +#define CRTC_INDEX 0x3d4 +#define CRTC_DATA 0x3d5
/* Memory Controller Registers */ #define RANK0_END 0x40
Modified: coreboot-v3/northbridge/via/cn700/initram.c =================================================================== --- coreboot-v3/northbridge/via/cn700/initram.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/initram.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -232,11 +232,11 @@ * TODO: #if and option in Kconfig */ /* Set WR=5 and RFC */ - //pci_conf1_write_config8(dev->d0f3, 0x61, 0x94); + pci_conf1_write_config8(dev->d0f3, 0x61, 0x94); /* Set CAS=5 */ - //pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a); - //pci_conf1_write_config8(dev->d0f3, 0x63, 0x00); - //pci_conf1_write_config8(dev->d0f3, 0x64, 0x88); + pci_conf1_write_config8(dev->d0f3, 0x62, 0x7a); + pci_conf1_write_config8(dev->d0f3, 0x63, 0x00); + pci_conf1_write_config8(dev->d0f3, 0x64, 0x88);
/* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for BL=4) */ pci_conf1_write_config8(dev->d0f3, 0x6c, 0xc8); @@ -404,7 +404,7 @@ spd_data = check_timing(spd_data, 5, 20);
reg8 = pci_conf1_read_config8(dev->d0f3, 0x62); - if ((spd_data - 10) > (reg8 >> 4)) + if ((spd_data - 5) > (reg8 >> 4)) { reg8 &= 0x0f; reg8 |= ((spd_data -10) << 4);
Modified: coreboot-v3/northbridge/via/cn700/pci_domain.c =================================================================== --- coreboot-v3/northbridge/via/cn700/pci_domain.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/pci_domain.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -86,8 +86,8 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); -
+ /* * Once the register value is not zero, the RAM size is * this register's value multiply 64 * 1024 * 1024. @@ -108,11 +108,12 @@ } /* Report the memory regions. */ idx = 10; - /* TODO: Hole needed? */ - ram_resource(dev, idx++, 0, 640); /* First 640k */ + + ram_resource(dev, idx++, 0, 640); /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ - ram_resource(dev, idx++, 768, - (tolmk - 768 - (CONFIG_CN700_VIDEO_MB * 1024))); + /* TODO: shadow ram needs to be controlled via dts */ + ram_resource(dev, idx++, 1024, + (tolmk - 1024 - (CONFIG_CN700_VIDEO_MB * 1024))); phase4_assign_resources(&dev->link[0]); }
@@ -129,5 +130,3 @@ .phase6_init = 0, .ops_pci_bus = &pci_cf8_conf1, }; - -
Modified: coreboot-v3/northbridge/via/cn700/stage1.c =================================================================== --- coreboot-v3/northbridge/via/cn700/stage1.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/northbridge/via/cn700/stage1.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -24,59 +24,6 @@ #include <config.h> #include "cn700.h"
-static void enable_shadow_ram(void) -{ - u8 shadowreg; - - printk(BIOS_DEBUG, "Enabling shadow ram\n"); - /* Enable shadow ram as normal dram */ - /* 0xc0000-0xcffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); - /* 0xd0000-0xdffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); - /* 0xe0000-0xeffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); - - /* 0xf0000-0xfffff */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); - - /* Do it again for the vlink controller */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); - shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); -} - -static void enable_vlink(void) -{ - printk(BIOS_DEBUG, "Enabling Via V-Link\n"); - - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); - //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); - - /* This has to be done last, I think */ - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); -} - /** * Configure the bus between the cpu and the northbridge. This might be able to * be moved to post-ram code in the future. For the most part, these registers @@ -92,6 +39,7 @@ static void c7_cpu_setup(void) { u32 dev = PCI_BDF(0, 0, 2); + u8 reg8;
/* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ @@ -114,6 +62,13 @@ * 110/111 : Reserved * bits 4:0: Reserved */ + + reg8 = pci_conf1_read_config8(dev, 0x57); + reg8 &= (0x7 << 5); + //reg8 |= (0x4 << 5); + reg8 |= (0x3 << 5); + pci_conf1_write_config8(dev, 0x57, reg8); + /* CPU Miscellaneous Control */ pci_conf1_write_config8(dev, 0x59, 0x44); /* Write Policy */ @@ -179,7 +134,5 @@ pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1); pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1);
- enable_shadow_ram(); - enable_vlink(); c7_cpu_setup(); }
Modified: coreboot-v3/southbridge/via/vt8237/Makefile =================================================================== --- coreboot-v3/southbridge/via/vt8237/Makefile 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/Makefile 2008-12-23 23:44:39 UTC (rev 1087) @@ -25,4 +25,9 @@ $(src)/southbridge/via/vt8237/ide.c \ $(src)/southbridge/via/vt8237/sata.c
+ifeq ($(CONFIG_PIRQ_TABLE),y) +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82801gx/irq_tables.c endif + + +endif
Modified: coreboot-v3/southbridge/via/vt8237/lpc.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -230,44 +230,34 @@ { u8 enables, byte;
+ /* Enable the RTC. */ + byte = pci_read_config8(dev, 0x51); + byte |= (1 << 3); + pci_write_config8(dev, 0x51, byte); + /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); byte |= PCI_COMMAND_WAIT; pci_write_config8(dev, PCI_COMMAND, byte);
/* Enable the internal I/O decode. */ - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); + byte = pci_read_config8(dev, 0x6C); + byte |= 0x80; + pci_write_config8(dev, 0x6C, byte);
/* - * ROM decode - * bit range - * 7 000E0000h-000EFFFFh - * 6 FFF00000h-FFF7FFFFh - * 5 FFE80000h-FFEFFFFFh - * 4 FFE00000h-FFE7FFFFh - * 3 FFD80000h-FFDFFFFFh - * 2 FFD00000h-FFD7FFFFh - * 1 FFC80000h-FFCFFFFFh - * 0 FFC00000h-FFC7FFFFh - * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. - */ - pci_write_config8(dev, 0x41, 0x7f); - - /* * Set bit 6 of 0x40 (I/O recovery time). * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so * that PCI interrupts can be properly marked as level triggered. */ - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); + byte = pci_read_config8(dev, 0x40); + byte |= 0x44; + pci_write_config8(dev, 0x40, byte);
/* Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf8; - pci_write_config8(dev, 0x42, enables); + byte = pci_read_config8(dev, 0x42); + byte |= 0xf8; + pci_write_config8(dev, 0x42, byte);
/* Delay transaction control */ pci_write_config8(dev, 0x43, 0xb); @@ -294,16 +284,14 @@ /* Enable serial IRQ, 6PCI clocks. */ pci_write_config8(dev, 0x52, 0x9);
- /* Power management setup */ + /* Power Management setup. */ setup_pm(dev);
- /* Enable the RTC. */ - enables = pci_read_config8(dev, 0x51); - enables |= (1 << 3); - pci_write_config8(dev, 0x51, enables); - /* Start the RTC. */ rtc_init(0); + + /* Initialize ISA DMA. */ + isa_dma_init(); }
static void vt8237_read_resources(struct device *dev) @@ -314,6 +302,8 @@ struct resource *res;
pci_dev_read_resources(dev); + +#ifdef VT8237_APIC_FIXED /* Fixed APIC resource */ res = new_resource(dev, 0x44); /* Possible breakage */ @@ -324,6 +314,7 @@ res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif }
/** @@ -342,10 +333,10 @@ struct southbridge_via_vt8237_lpc_config *sb = (struct southbridge_via_vt8237_lpc_config *)dev->device_configuration;
- u8 regval; - if (sb->enable_keyboard) { + u8 regval; + /* Enable PS/2 mouse, Keyboard, and KBC Config */ regval = pci_read_config8(dev, 0x51); regval |= (1 << 2)|(1 << 1)|1; @@ -359,7 +350,7 @@ { vt8237_common_init(dev); pci_routing_fixup(dev); - setup_ioapic(dev); + //setup_ioapic(dev); setup_i8259(); init_keyboard(dev); } @@ -448,7 +439,7 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, .constructor = default_device_constructor, - .phase3_chip_setup_dev = vt8237r_init, + //.phase3_chip_setup_dev = vt8237r_init, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources,
Modified: coreboot-v3/southbridge/via/vt8237/stage1.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -155,8 +155,9 @@ */ void enable_smbus(u16 smbus_io_base) { - u32 dev; + u32 dev = PCI_BDF(0, 17, 0);
+#if 0 /* Power management controller */ pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, &dev); @@ -178,6 +179,7 @@ printk(BIOS_DEBUG, "VT8237R Power management controller found " "at 0x%x\n", dev); } +#endif
/* 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp @@ -201,37 +203,15 @@ inb(smbus_io_base + SMBHSTCTL); }
-/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it - * as early as possible. Move back to stage2 later */ -static void sata_stage1(void) -{ - u32 dev; - u8 reg; - - pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev); - - printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); - - /* Class IDE Disk */ - reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL); - reg &= 0x7f; /* Sub Class Write Protect off */ - pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); - - /* Change the device class to SATA from RAID. */ - pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1); - reg |= 0x80; /* Sub Class Write Protect on */ - pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg); -} - void vt8237_stage1(u16 smbus_io_base) { - u32 dev; - u32 ide_dev; + u32 dev = PCI_BDF(0, 17, 0); + //u32 ide_dev; printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n");
- pci_conf1_find_device(0x1106, 0x3227, &dev); - pci_conf1_find_device(0x1106, 0x0571, &ide_dev); + //pci_conf1_find_device(0x1106, 0x3227, &dev); + //pci_conf1_find_device(0x1106, 0x0571, &ide_dev); /* Disable GP3 timer, or else the system reboots when it runs out. * Datasheets say this is disabled by default, they're wrong. */ @@ -248,12 +228,12 @@
pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97 pci_conf1_write_config8(dev, 0x51, 0x1f); - pci_conf1_write_config8(dev, 0x58, 0x60); - pci_conf1_write_config8(dev, 0x59, 0x80); - pci_conf1_write_config8(dev, 0x5b, 0x08); + //pci_conf1_write_config8(dev, 0x58, 0x60); + //pci_conf1_write_config8(dev, 0x59, 0x80); + //pci_conf1_write_config8(dev, 0x5b, 0x08);
/* Make it respond to IO space */ - pci_conf1_write_config8(ide_dev, 0x04, 0x07); + //pci_conf1_write_config8(ide_dev, 0x04, 0x07);
/* Compatibility mode addresses */ //pci_conf1_write_config32(ide_dev, 0x10, 0); @@ -264,9 +244,9 @@ /* Native mode base address */ //pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1);
- pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3 - pci_conf1_write_config8(ide_dev, 0x41, 0xf2); - pci_conf1_write_config8(ide_dev, 0x42, 0x09); + //pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3 + //pci_conf1_write_config8(ide_dev, 0x41, 0xf2); + //pci_conf1_write_config8(ide_dev, 0x42, 0x09);
//sata_stage1(); enable_smbus(smbus_io_base);
Modified: coreboot-v3/southbridge/via/vt8237/vt8237.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.c 2008-12-23 19:21:54 UTC (rev 1086) +++ coreboot-v3/southbridge/via/vt8237/vt8237.c 2008-12-23 23:44:39 UTC (rev 1087) @@ -38,14 +38,14 @@ const u8 func = dev->path.pci.devfn & 0x7; const u8 device = dev->path.pci.devfn >> 3; const int d16_index[6] = {12, 13, 10, 8, 9, 7}; -
+ printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n", device, func);
if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA) return; - + lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0)); sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8; sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51);
-
svn＠coreboot.org